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authorPraneeth Bajjuri2016-03-18 17:45:56 -0500
committerPraneeth Bajjuri2016-03-18 17:45:56 -0500
commit1159c452bac00d64b711ed7384d6e5ee9d20d38c (patch)
treeab603933985ba293e2b714ec1de56cd597e2a48b
parent967b38f390945064adacc396e0c7eb82666fff62 (diff)
parent7a9ce2cdb5492362670cd58b30ae40ee2db14279 (diff)
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Merge branch 'p-ti-linux-3.14.y-common' into p-ti-linux-3.14.y-androidandroid-3.14-6AM.1.0
* p-ti-linux-3.14.y-common: pm: dra7: Restrict vip/vpe power domain state to INA pm: dra7: Update power domain states as per new spec ARM: OMAP: DRA7: powerdomain data: Remove CSWR with the exception of MPU ARM: OMAP: DRA7: powerdomain data: Fix "ON" state for memories ARM: OMAP: DRA7: powerdomain data: Remove wrong OSWR capability ARM: dts: dra7-evm: mmc: fix typos in register names and values Change-Id: I3a327104320949e44fd891d790f145e3d27ff0b1 Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts46
-rw-r--r--arch/arm/mach-omap2/powerdomains7xx_data.c158
2 files changed, 103 insertions, 101 deletions
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 2d9eab18524..0f295e29490 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -500,17 +500,17 @@
500 500
501 mmc1_iodelay_sdr104_conf_sr20: mmc1_iodelay_sdr104_conf_sr20 { 501 mmc1_iodelay_sdr104_conf_sr20: mmc1_iodelay_sdr104_conf_sr20 {
502 pinctrl-single,pins = < 502 pinctrl-single,pins = <
503 0x620 (A_DELAY(1063) | G_DELAY(17)) /* CFG_MMC1_CLK_OUT */ 503 0x620 (A_DELAY(600) | G_DELAY(400)) /* CFG_MMC1_CLK_OUT */
504 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ 504 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
505 0x62c (A_DELAY(23) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ 505 0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
506 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ 506 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
507 0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ 507 0x638 (A_DELAY(30) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
508 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ 508 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
509 0x644 (A_DELAY(2) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ 509 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
510 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ 510 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
511 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ 511 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
512 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ 512 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
513 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ 513 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
514 >; 514 >;
515 }; 515 };
516 516
@@ -650,10 +650,10 @@
650 0x870 (A_DELAY(582) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */ 650 0x870 (A_DELAY(582) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
651 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */ 651 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
652 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */ 652 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
653 0x87C (A_DELAY(391) | G_DELAY(0)) /* RCFG_UART2_RTSN_IN */ 653 0x87C (A_DELAY(391) | G_DELAY(0)) /* CFG_UART2_RTSN_IN */
654 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */ 654 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
655 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */ 655 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
656 0x888 (A_DELAY(561) | G_DELAY(0)) /* RCFG_UART2_RXD_IN */ 656 0x888 (A_DELAY(561) | G_DELAY(0)) /* CFG_UART2_RXD_IN */
657 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */ 657 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
658 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */ 658 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
659 0x894 (A_DELAY(588) | G_DELAY(0)) /* CFG_UART2_TXD_IN */ 659 0x894 (A_DELAY(588) | G_DELAY(0)) /* CFG_UART2_TXD_IN */
@@ -672,10 +672,10 @@
672 0x870 (A_DELAY(1913) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */ 672 0x870 (A_DELAY(1913) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
673 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */ 673 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
674 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */ 674 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
675 0x87C (A_DELAY(1721) | G_DELAY(0)) /* RCFG_UART2_RTSN_IN */ 675 0x87C (A_DELAY(1721) | G_DELAY(0)) /* CFG_UART2_RTSN_IN */
676 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */ 676 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
677 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */ 677 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
678 0x888 (A_DELAY(1891) | G_DELAY(0)) /* RCFG_UART2_RXD_IN */ 678 0x888 (A_DELAY(1891) | G_DELAY(0)) /* CFG_UART2_RXD_IN */
679 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */ 679 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
680 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */ 680 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
681 0x894 (A_DELAY(1919) | G_DELAY(0)) /* CFG_UART2_TXD_IN */ 681 0x894 (A_DELAY(1919) | G_DELAY(0)) /* CFG_UART2_TXD_IN */
@@ -691,16 +691,16 @@
691 0x84c (A_DELAY(307) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */ 691 0x84c (A_DELAY(307) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */
692 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */ 692 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */
693 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */ 693 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */
694 0x870 (A_DELAY(683) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */ 694 0x870 (A_DELAY(785) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
695 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */ 695 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
696 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */ 696 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
697 0x87C (A_DELAY(835) | G_DELAY(0)) /* RCFG_UART2_RTSN_IN */ 697 0x87C (A_DELAY(613) | G_DELAY(0)) /* CFG_UART2_RTSN_IN */
698 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */ 698 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
699 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */ 699 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
700 0x888 (A_DELAY(785) | G_DELAY(0)) /* RCFG_UART2_RXD_IN */ 700 0x888 (A_DELAY(683) | G_DELAY(0)) /* CFG_UART2_RXD_IN */
701 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */ 701 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
702 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */ 702 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
703 0x894 (A_DELAY(613) | G_DELAY(0)) /* CFG_UART2_TXD_IN */ 703 0x894 (A_DELAY(835) | G_DELAY(0)) /* CFG_UART2_TXD_IN */
704 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */ 704 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */
705 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */ 705 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */
706 >; 706 >;
@@ -713,16 +713,16 @@
713 0x84c (A_DELAY(1834) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */ 713 0x84c (A_DELAY(1834) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */
714 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */ 714 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */
715 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */ 715 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */
716 0x870 (A_DELAY(1935) | G_DELAY(128)) /* CFG_UART2_CTSN_IN */ 716 0x870 (A_DELAY(2165) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
717 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */ 717 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
718 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */ 718 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
719 0x87C (A_DELAY(2172) | G_DELAY(44)) /* RCFG_UART2_RTSN_IN */ 719 0x87C (A_DELAY(1929) | G_DELAY(64)) /* CFG_UART2_RTSN_IN */
720 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */ 720 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
721 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */ 721 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
722 0x888 (A_DELAY(2165) | G_DELAY(0)) /* RCFG_UART2_RXD_IN */ 722 0x888 (A_DELAY(1935) | G_DELAY(128)) /* CFG_UART2_RXD_IN */
723 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */ 723 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
724 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */ 724 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
725 0x894 (A_DELAY(1929) | G_DELAY(64)) /* CFG_UART2_TXD_IN */ 725 0x894 (A_DELAY(2172) | G_DELAY(44)) /* CFG_UART2_TXD_IN */
726 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */ 726 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */
727 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */ 727 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */
728 >; 728 >;
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index f2b4557124f..b7f054da997 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -35,20 +35,20 @@ static struct powerdomain iva_7xx_pwrdm = {
35 .name = "iva_pwrdm", 35 .name = "iva_pwrdm",
36 .prcm_offs = DRA7XX_PRM_IVA_INST, 36 .prcm_offs = DRA7XX_PRM_IVA_INST,
37 .prcm_partition = DRA7XX_PRM_PARTITION, 37 .prcm_partition = DRA7XX_PRM_PARTITION,
38 .pwrsts = PWRSTS_OFF_RET_ON, 38 .pwrsts = PWRSTS_OFF_ON,
39 .pwrsts_logic_ret = PWRSTS_OFF, 39 .pwrsts_logic_ret = PWRSTS_OFF,
40 .banks = 4, 40 .banks = 4,
41 .pwrsts_mem_ret = { 41 .pwrsts_mem_ret = {
42 [0] = PWRSTS_OFF_RET, /* hwa_mem */ 42 [0] = PWRSTS_OFF, /* hwa_mem */
43 [1] = PWRSTS_OFF_RET, /* sl2_mem */ 43 [1] = PWRSTS_OFF, /* sl2_mem */
44 [2] = PWRSTS_OFF_RET, /* tcm1_mem */ 44 [2] = PWRSTS_OFF, /* tcm1_mem */
45 [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 45 [3] = PWRSTS_OFF, /* tcm2_mem */
46 }, 46 },
47 .pwrsts_mem_on = { 47 .pwrsts_mem_on = {
48 [0] = PWRSTS_OFF_RET, /* hwa_mem */ 48 [0] = PWRSTS_ON, /* hwa_mem */
49 [1] = PWRSTS_OFF_RET, /* sl2_mem */ 49 [1] = PWRSTS_ON, /* sl2_mem */
50 [2] = PWRSTS_OFF_RET, /* tcm1_mem */ 50 [2] = PWRSTS_ON, /* tcm1_mem */
51 [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 51 [3] = PWRSTS_ON, /* tcm2_mem */
52 }, 52 },
53 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 53 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
54}; 54};
@@ -66,7 +66,7 @@ static struct powerdomain custefuse_7xx_pwrdm = {
66 .name = "custefuse_pwrdm", 66 .name = "custefuse_pwrdm",
67 .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST, 67 .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
68 .prcm_partition = DRA7XX_PRM_PARTITION, 68 .prcm_partition = DRA7XX_PRM_PARTITION,
69 .pwrsts = PWRSTS_OFF_ON, 69 .pwrsts = PWRSTS_ON,
70 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 70 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
71}; 71};
72 72
@@ -75,16 +75,16 @@ static struct powerdomain ipu_7xx_pwrdm = {
75 .name = "ipu_pwrdm", 75 .name = "ipu_pwrdm",
76 .prcm_offs = DRA7XX_PRM_IPU_INST, 76 .prcm_offs = DRA7XX_PRM_IPU_INST,
77 .prcm_partition = DRA7XX_PRM_PARTITION, 77 .prcm_partition = DRA7XX_PRM_PARTITION,
78 .pwrsts = PWRSTS_OFF_RET_ON, 78 .pwrsts = PWRSTS_OFF_ON,
79 .pwrsts_logic_ret = PWRSTS_OFF, 79 .pwrsts_logic_ret = PWRSTS_OFF,
80 .banks = 2, 80 .banks = 2,
81 .pwrsts_mem_ret = { 81 .pwrsts_mem_ret = {
82 [0] = PWRSTS_OFF_RET, /* aessmem */ 82 [0] = PWRSTS_OFF, /* aessmem */
83 [1] = PWRSTS_OFF_RET, /* periphmem */ 83 [1] = PWRSTS_OFF, /* periphmem */
84 }, 84 },
85 .pwrsts_mem_on = { 85 .pwrsts_mem_on = {
86 [0] = PWRSTS_OFF_RET, /* aessmem */ 86 [0] = PWRSTS_ON, /* aessmem */
87 [1] = PWRSTS_OFF_RET, /* periphmem */ 87 [1] = PWRSTS_ON, /* periphmem */
88 }, 88 },
89 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 89 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
90}; 90};
@@ -94,14 +94,14 @@ static struct powerdomain dss_7xx_pwrdm = {
94 .name = "dss_pwrdm", 94 .name = "dss_pwrdm",
95 .prcm_offs = DRA7XX_PRM_DSS_INST, 95 .prcm_offs = DRA7XX_PRM_DSS_INST,
96 .prcm_partition = DRA7XX_PRM_PARTITION, 96 .prcm_partition = DRA7XX_PRM_PARTITION,
97 .pwrsts = PWRSTS_OFF_RET_ON, 97 .pwrsts = PWRSTS_OFF_ON,
98 .pwrsts_logic_ret = PWRSTS_OFF, 98 .pwrsts_logic_ret = PWRSTS_OFF,
99 .banks = 1, 99 .banks = 1,
100 .pwrsts_mem_ret = { 100 .pwrsts_mem_ret = {
101 [0] = PWRSTS_OFF_RET, /* dss_mem */ 101 [0] = PWRSTS_OFF, /* dss_mem */
102 }, 102 },
103 .pwrsts_mem_on = { 103 .pwrsts_mem_on = {
104 [0] = PWRSTS_OFF_RET, /* dss_mem */ 104 [0] = PWRSTS_ON, /* dss_mem */
105 }, 105 },
106 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 106 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
107}; 107};
@@ -111,16 +111,17 @@ static struct powerdomain l4per_7xx_pwrdm = {
111 .name = "l4per_pwrdm", 111 .name = "l4per_pwrdm",
112 .prcm_offs = DRA7XX_PRM_L4PER_INST, 112 .prcm_offs = DRA7XX_PRM_L4PER_INST,
113 .prcm_partition = DRA7XX_PRM_PARTITION, 113 .prcm_partition = DRA7XX_PRM_PARTITION,
114 .pwrsts = PWRSTS_RET_ON, 114 .pwrsts = PWRSTS_ON,
115 .pwrsts_logic_ret = PWRSTS_OFF_RET, 115 /* Due to assymetric aging constraints */
116 .pwrsts_logic_ret = PWRSTS_RET,
116 .banks = 2, 117 .banks = 2,
117 .pwrsts_mem_ret = { 118 .pwrsts_mem_ret = {
118 [0] = PWRSTS_OFF_RET, /* nonretained_bank */ 119 [0] = PWRSTS_ON, /* nonretained_bank */
119 [1] = PWRSTS_OFF_RET, /* retained_bank */ 120 [1] = PWRSTS_ON, /* retained_bank */
120 }, 121 },
121 .pwrsts_mem_on = { 122 .pwrsts_mem_on = {
122 [0] = PWRSTS_OFF_RET, /* nonretained_bank */ 123 [0] = PWRSTS_ON, /* nonretained_bank */
123 [1] = PWRSTS_OFF_RET, /* retained_bank */ 124 [1] = PWRSTS_ON, /* retained_bank */
124 }, 125 },
125 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 126 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
126}; 127};
@@ -133,10 +134,10 @@ static struct powerdomain gpu_7xx_pwrdm = {
133 .pwrsts = PWRSTS_OFF_ON, 134 .pwrsts = PWRSTS_OFF_ON,
134 .banks = 1, 135 .banks = 1,
135 .pwrsts_mem_ret = { 136 .pwrsts_mem_ret = {
136 [0] = PWRSTS_OFF_RET, /* gpu_mem */ 137 [0] = PWRSTS_OFF, /* gpu_mem */
137 }, 138 },
138 .pwrsts_mem_on = { 139 .pwrsts_mem_on = {
139 [0] = PWRSTS_OFF_RET, /* gpu_mem */ 140 [0] = PWRSTS_ON, /* gpu_mem */
140 }, 141 },
141 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 142 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
142}; 143};
@@ -164,18 +165,18 @@ static struct powerdomain core_7xx_pwrdm = {
164 .pwrsts_logic_ret = PWRSTS_RET, 165 .pwrsts_logic_ret = PWRSTS_RET,
165 .banks = 5, 166 .banks = 5,
166 .pwrsts_mem_ret = { 167 .pwrsts_mem_ret = {
167 [0] = PWRSTS_OFF_RET, /* core_nret_bank */ 168 [0] = PWRSTS_ON, /* core_nret_bank */
168 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 169 [1] = PWRSTS_ON, /* core_ocmram */
169 [2] = PWRSTS_OFF_RET, /* core_other_bank */ 170 [2] = PWRSTS_ON, /* core_other_bank */
170 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ 171 [3] = PWRSTS_ON, /* ipu_l2ram */
171 [4] = PWRSTS_OFF_RET, /* ipu_unicache */ 172 [4] = PWRSTS_ON, /* ipu_unicache */
172 }, 173 },
173 .pwrsts_mem_on = { 174 .pwrsts_mem_on = {
174 [0] = PWRSTS_OFF_RET, /* core_nret_bank */ 175 [0] = PWRSTS_ON, /* core_nret_bank */
175 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 176 [1] = PWRSTS_ON, /* core_ocmram */
176 [2] = PWRSTS_OFF_RET, /* core_other_bank */ 177 [2] = PWRSTS_ON, /* core_other_bank */
177 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ 178 [3] = PWRSTS_ON, /* ipu_l2ram */
178 [4] = PWRSTS_OFF_RET, /* ipu_unicache */ 179 [4] = PWRSTS_ON, /* ipu_unicache */
179 }, 180 },
180 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 181 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
181}; 182};
@@ -197,7 +198,7 @@ static struct powerdomain cpu0_7xx_pwrdm = {
197 .pwrsts_logic_ret = PWRSTS_RET, 198 .pwrsts_logic_ret = PWRSTS_RET,
198 .banks = 1, 199 .banks = 1,
199 .pwrsts_mem_ret = { 200 .pwrsts_mem_ret = {
200 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ 201 [0] = PWRSTS_OFF, /* cpu0_l1 */
201 }, 202 },
202 .pwrsts_mem_on = { 203 .pwrsts_mem_on = {
203 [0] = PWRSTS_ON, /* cpu0_l1 */ 204 [0] = PWRSTS_ON, /* cpu0_l1 */
@@ -213,7 +214,7 @@ static struct powerdomain cpu1_7xx_pwrdm = {
213 .pwrsts_logic_ret = PWRSTS_RET, 214 .pwrsts_logic_ret = PWRSTS_RET,
214 .banks = 1, 215 .banks = 1,
215 .pwrsts_mem_ret = { 216 .pwrsts_mem_ret = {
216 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ 217 [0] = PWRSTS_OFF, /* cpu1_l1 */
217 }, 218 },
218 .pwrsts_mem_on = { 219 .pwrsts_mem_on = {
219 [0] = PWRSTS_ON, /* cpu1_l1 */ 220 [0] = PWRSTS_ON, /* cpu1_l1 */
@@ -225,14 +226,14 @@ static struct powerdomain vpe_7xx_pwrdm = {
225 .name = "vpe_pwrdm", 226 .name = "vpe_pwrdm",
226 .prcm_offs = DRA7XX_PRM_VPE_INST, 227 .prcm_offs = DRA7XX_PRM_VPE_INST,
227 .prcm_partition = DRA7XX_PRM_PARTITION, 228 .prcm_partition = DRA7XX_PRM_PARTITION,
228 .pwrsts = PWRSTS_OFF_RET_ON, 229 .pwrsts = PWRSTS_INA_ON,
229 .pwrsts_logic_ret = PWRSTS_OFF_RET, 230 .pwrsts_logic_ret = PWRSTS_OFF,
230 .banks = 1, 231 .banks = 1,
231 .pwrsts_mem_ret = { 232 .pwrsts_mem_ret = {
232 [0] = PWRSTS_OFF_RET, /* vpe_bank */ 233 [0] = PWRSTS_OFF, /* vpe_bank */
233 }, 234 },
234 .pwrsts_mem_on = { 235 .pwrsts_mem_on = {
235 [0] = PWRSTS_OFF_RET, /* vpe_bank */ 236 [0] = PWRSTS_ON, /* vpe_bank */
236 }, 237 },
237 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 238 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
238}; 239};
@@ -250,8 +251,8 @@ static struct powerdomain mpu_7xx_pwrdm = {
250 [1] = PWRSTS_RET, /* mpu_ram */ 251 [1] = PWRSTS_RET, /* mpu_ram */
251 }, 252 },
252 .pwrsts_mem_on = { 253 .pwrsts_mem_on = {
253 [0] = PWRSTS_OFF_RET, /* mpu_l2 */ 254 [0] = PWRSTS_ON, /* mpu_l2 */
254 [1] = PWRSTS_OFF_RET, /* mpu_ram */ 255 [1] = PWRSTS_ON, /* mpu_ram */
255 }, 256 },
256}; 257};
257 258
@@ -260,18 +261,19 @@ static struct powerdomain l3init_7xx_pwrdm = {
260 .name = "l3init_pwrdm", 261 .name = "l3init_pwrdm",
261 .prcm_offs = DRA7XX_PRM_L3INIT_INST, 262 .prcm_offs = DRA7XX_PRM_L3INIT_INST,
262 .prcm_partition = DRA7XX_PRM_PARTITION, 263 .prcm_partition = DRA7XX_PRM_PARTITION,
263 .pwrsts = PWRSTS_RET_ON, 264 /* Due to Asymettric Aging constraints */
264 .pwrsts_logic_ret = PWRSTS_OFF_RET, 265 .pwrsts = PWRSTS_ON,
266 .pwrsts_logic_ret = PWRSTS_RET,
265 .banks = 3, 267 .banks = 3,
266 .pwrsts_mem_ret = { 268 .pwrsts_mem_ret = {
267 [0] = PWRSTS_OFF_RET, /* gmac_bank */ 269 [0] = PWRSTS_ON, /* gmac_bank */
268 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */ 270 [1] = PWRSTS_ON, /* l3init_bank1 */
269 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ 271 [2] = PWRSTS_ON, /* l3init_bank2 */
270 }, 272 },
271 .pwrsts_mem_on = { 273 .pwrsts_mem_on = {
272 [0] = PWRSTS_OFF_RET, /* gmac_bank */ 274 [0] = PWRSTS_ON, /* gmac_bank */
273 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */ 275 [1] = PWRSTS_ON, /* l3init_bank1 */
274 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ 276 [2] = PWRSTS_ON, /* l3init_bank2 */
275 }, 277 },
276 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 278 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
277}; 279};
@@ -284,10 +286,10 @@ static struct powerdomain eve3_7xx_pwrdm = {
284 .pwrsts = PWRSTS_OFF_ON, 286 .pwrsts = PWRSTS_OFF_ON,
285 .banks = 1, 287 .banks = 1,
286 .pwrsts_mem_ret = { 288 .pwrsts_mem_ret = {
287 [0] = PWRSTS_OFF_RET, /* eve3_bank */ 289 [0] = PWRSTS_OFF, /* eve3_bank */
288 }, 290 },
289 .pwrsts_mem_on = { 291 .pwrsts_mem_on = {
290 [0] = PWRSTS_OFF_RET, /* eve3_bank */ 292 [0] = PWRSTS_ON, /* eve3_bank */
291 }, 293 },
292 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 294 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
293}; 295};
@@ -297,13 +299,13 @@ static struct powerdomain emu_7xx_pwrdm = {
297 .name = "emu_pwrdm", 299 .name = "emu_pwrdm",
298 .prcm_offs = DRA7XX_PRM_EMU_INST, 300 .prcm_offs = DRA7XX_PRM_EMU_INST,
299 .prcm_partition = DRA7XX_PRM_PARTITION, 301 .prcm_partition = DRA7XX_PRM_PARTITION,
300 .pwrsts = PWRSTS_OFF_ON, 302 .pwrsts = PWRSTS_ON,
301 .banks = 1, 303 .banks = 1,
302 .pwrsts_mem_ret = { 304 .pwrsts_mem_ret = {
303 [0] = PWRSTS_OFF_RET, /* emu_bank */ 305 [0] = PWRSTS_OFF, /* emu_bank */
304 }, 306 },
305 .pwrsts_mem_on = { 307 .pwrsts_mem_on = {
306 [0] = PWRSTS_OFF_RET, /* emu_bank */ 308 [0] = PWRSTS_ON, /* emu_bank */
307 }, 309 },
308}; 310};
309 311
@@ -315,14 +317,14 @@ static struct powerdomain dsp2_7xx_pwrdm = {
315 .pwrsts = PWRSTS_OFF_ON, 317 .pwrsts = PWRSTS_OFF_ON,
316 .banks = 3, 318 .banks = 3,
317 .pwrsts_mem_ret = { 319 .pwrsts_mem_ret = {
318 [0] = PWRSTS_OFF_RET, /* dsp2_edma */ 320 [0] = PWRSTS_OFF, /* dsp2_edma */
319 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */ 321 [1] = PWRSTS_OFF, /* dsp2_l1 */
320 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ 322 [2] = PWRSTS_OFF, /* dsp2_l2 */
321 }, 323 },
322 .pwrsts_mem_on = { 324 .pwrsts_mem_on = {
323 [0] = PWRSTS_OFF_RET, /* dsp2_edma */ 325 [0] = PWRSTS_ON, /* dsp2_edma */
324 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */ 326 [1] = PWRSTS_ON, /* dsp2_l1 */
325 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ 327 [2] = PWRSTS_ON, /* dsp2_l2 */
326 }, 328 },
327 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 329 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
328}; 330};
@@ -335,14 +337,14 @@ static struct powerdomain dsp1_7xx_pwrdm = {
335 .pwrsts = PWRSTS_OFF_ON, 337 .pwrsts = PWRSTS_OFF_ON,
336 .banks = 3, 338 .banks = 3,
337 .pwrsts_mem_ret = { 339 .pwrsts_mem_ret = {
338 [0] = PWRSTS_OFF_RET, /* dsp1_edma */ 340 [0] = PWRSTS_OFF, /* dsp1_edma */
339 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */ 341 [1] = PWRSTS_OFF, /* dsp1_l1 */
340 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ 342 [2] = PWRSTS_OFF, /* dsp1_l2 */
341 }, 343 },
342 .pwrsts_mem_on = { 344 .pwrsts_mem_on = {
343 [0] = PWRSTS_OFF_RET, /* dsp1_edma */ 345 [0] = PWRSTS_ON, /* dsp1_edma */
344 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */ 346 [1] = PWRSTS_ON, /* dsp1_l1 */
345 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ 347 [2] = PWRSTS_ON, /* dsp1_l2 */
346 }, 348 },
347 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 349 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
348}; 350};
@@ -352,13 +354,13 @@ static struct powerdomain cam_7xx_pwrdm = {
352 .name = "cam_pwrdm", 354 .name = "cam_pwrdm",
353 .prcm_offs = DRA7XX_PRM_CAM_INST, 355 .prcm_offs = DRA7XX_PRM_CAM_INST,
354 .prcm_partition = DRA7XX_PRM_PARTITION, 356 .prcm_partition = DRA7XX_PRM_PARTITION,
355 .pwrsts = PWRSTS_OFF_ON, 357 .pwrsts = PWRSTS_INA_ON,
356 .banks = 1, 358 .banks = 1,
357 .pwrsts_mem_ret = { 359 .pwrsts_mem_ret = {
358 [0] = PWRSTS_OFF_RET, /* vip_bank */ 360 [0] = PWRSTS_OFF, /* vip_bank */
359 }, 361 },
360 .pwrsts_mem_on = { 362 .pwrsts_mem_on = {
361 [0] = PWRSTS_OFF_RET, /* vip_bank */ 363 [0] = PWRSTS_ON, /* vip_bank */
362 }, 364 },
363 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 365 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
364}; 366};
@@ -371,10 +373,10 @@ static struct powerdomain eve4_7xx_pwrdm = {
371 .pwrsts = PWRSTS_OFF_ON, 373 .pwrsts = PWRSTS_OFF_ON,
372 .banks = 1, 374 .banks = 1,
373 .pwrsts_mem_ret = { 375 .pwrsts_mem_ret = {
374 [0] = PWRSTS_OFF_RET, /* eve4_bank */ 376 [0] = PWRSTS_OFF, /* eve4_bank */
375 }, 377 },
376 .pwrsts_mem_on = { 378 .pwrsts_mem_on = {
377 [0] = PWRSTS_OFF_RET, /* eve4_bank */ 379 [0] = PWRSTS_ON, /* eve4_bank */
378 }, 380 },
379 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 381 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
380}; 382};
@@ -387,10 +389,10 @@ static struct powerdomain eve2_7xx_pwrdm = {
387 .pwrsts = PWRSTS_OFF_ON, 389 .pwrsts = PWRSTS_OFF_ON,
388 .banks = 1, 390 .banks = 1,
389 .pwrsts_mem_ret = { 391 .pwrsts_mem_ret = {
390 [0] = PWRSTS_OFF_RET, /* eve2_bank */ 392 [0] = PWRSTS_OFF, /* eve2_bank */
391 }, 393 },
392 .pwrsts_mem_on = { 394 .pwrsts_mem_on = {
393 [0] = PWRSTS_OFF_RET, /* eve2_bank */ 395 [0] = PWRSTS_ON, /* eve2_bank */
394 }, 396 },
395 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 397 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
396}; 398};
@@ -403,10 +405,10 @@ static struct powerdomain eve1_7xx_pwrdm = {
403 .pwrsts = PWRSTS_OFF_ON, 405 .pwrsts = PWRSTS_OFF_ON,
404 .banks = 1, 406 .banks = 1,
405 .pwrsts_mem_ret = { 407 .pwrsts_mem_ret = {
406 [0] = PWRSTS_OFF_RET, /* eve1_bank */ 408 [0] = PWRSTS_OFF, /* eve1_bank */
407 }, 409 },
408 .pwrsts_mem_on = { 410 .pwrsts_mem_on = {
409 [0] = PWRSTS_OFF_RET, /* eve1_bank */ 411 [0] = PWRSTS_ON, /* eve1_bank */
410 }, 412 },
411 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 413 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
412}; 414};