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author | Nishanth Menon | 2016-02-04 17:35:47 -0600 |
---|---|---|
committer | Praneeth Bajjuri | 2016-03-18 17:35:06 -0500 |
commit | 6d214e2744799283c4566b271b4049414dc28885 (patch) | |
tree | 9d8259841b73a2894b6b6941bc1ed10469a3f769 | |
parent | e5d8fd1f81810d8172f1a9fff05e8a2e8546d660 (diff) | |
download | kernel-video-6d214e2744799283c4566b271b4049414dc28885.tar.gz kernel-video-6d214e2744799283c4566b271b4049414dc28885.tar.xz kernel-video-6d214e2744799283c4566b271b4049414dc28885.zip |
ARM: OMAP: DRA7: powerdomain data: Remove wrong OSWR capability
Open Switch Retention(OSWR) is a retention state which is unsupported
in DRA7 SoC. This state is achieved when power state is set to
retention and logic power state is set to OFF.
Even though DRA7 architecture is a OMAP5 derivative, none of the
powerdomains are actually designed to achieve OSWR in the SoC.
Change-Id: I7f2ac011502e90a6b5da2afd9a1826193ca26cfe
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Ravikumar Kattekola <rk@ti.com>
-rw-r--r-- | arch/arm/mach-omap2/powerdomains7xx_data.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c index f2b4557124f..714d4d71f80 100644 --- a/arch/arm/mach-omap2/powerdomains7xx_data.c +++ b/arch/arm/mach-omap2/powerdomains7xx_data.c | |||
@@ -35,7 +35,7 @@ static struct powerdomain iva_7xx_pwrdm = { | |||
35 | .name = "iva_pwrdm", | 35 | .name = "iva_pwrdm", |
36 | .prcm_offs = DRA7XX_PRM_IVA_INST, | 36 | .prcm_offs = DRA7XX_PRM_IVA_INST, |
37 | .prcm_partition = DRA7XX_PRM_PARTITION, | 37 | .prcm_partition = DRA7XX_PRM_PARTITION, |
38 | .pwrsts = PWRSTS_OFF_RET_ON, | 38 | .pwrsts = PWRSTS_OFF_ON, |
39 | .pwrsts_logic_ret = PWRSTS_OFF, | 39 | .pwrsts_logic_ret = PWRSTS_OFF, |
40 | .banks = 4, | 40 | .banks = 4, |
41 | .pwrsts_mem_ret = { | 41 | .pwrsts_mem_ret = { |
@@ -75,7 +75,7 @@ static struct powerdomain ipu_7xx_pwrdm = { | |||
75 | .name = "ipu_pwrdm", | 75 | .name = "ipu_pwrdm", |
76 | .prcm_offs = DRA7XX_PRM_IPU_INST, | 76 | .prcm_offs = DRA7XX_PRM_IPU_INST, |
77 | .prcm_partition = DRA7XX_PRM_PARTITION, | 77 | .prcm_partition = DRA7XX_PRM_PARTITION, |
78 | .pwrsts = PWRSTS_OFF_RET_ON, | 78 | .pwrsts = PWRSTS_OFF_ON, |
79 | .pwrsts_logic_ret = PWRSTS_OFF, | 79 | .pwrsts_logic_ret = PWRSTS_OFF, |
80 | .banks = 2, | 80 | .banks = 2, |
81 | .pwrsts_mem_ret = { | 81 | .pwrsts_mem_ret = { |
@@ -94,7 +94,7 @@ static struct powerdomain dss_7xx_pwrdm = { | |||
94 | .name = "dss_pwrdm", | 94 | .name = "dss_pwrdm", |
95 | .prcm_offs = DRA7XX_PRM_DSS_INST, | 95 | .prcm_offs = DRA7XX_PRM_DSS_INST, |
96 | .prcm_partition = DRA7XX_PRM_PARTITION, | 96 | .prcm_partition = DRA7XX_PRM_PARTITION, |
97 | .pwrsts = PWRSTS_OFF_RET_ON, | 97 | .pwrsts = PWRSTS_OFF_ON, |
98 | .pwrsts_logic_ret = PWRSTS_OFF, | 98 | .pwrsts_logic_ret = PWRSTS_OFF, |
99 | .banks = 1, | 99 | .banks = 1, |
100 | .pwrsts_mem_ret = { | 100 | .pwrsts_mem_ret = { |
@@ -112,7 +112,7 @@ static struct powerdomain l4per_7xx_pwrdm = { | |||
112 | .prcm_offs = DRA7XX_PRM_L4PER_INST, | 112 | .prcm_offs = DRA7XX_PRM_L4PER_INST, |
113 | .prcm_partition = DRA7XX_PRM_PARTITION, | 113 | .prcm_partition = DRA7XX_PRM_PARTITION, |
114 | .pwrsts = PWRSTS_RET_ON, | 114 | .pwrsts = PWRSTS_RET_ON, |
115 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 115 | .pwrsts_logic_ret = PWRSTS_RET, |
116 | .banks = 2, | 116 | .banks = 2, |
117 | .pwrsts_mem_ret = { | 117 | .pwrsts_mem_ret = { |
118 | [0] = PWRSTS_OFF_RET, /* nonretained_bank */ | 118 | [0] = PWRSTS_OFF_RET, /* nonretained_bank */ |
@@ -225,8 +225,8 @@ static struct powerdomain vpe_7xx_pwrdm = { | |||
225 | .name = "vpe_pwrdm", | 225 | .name = "vpe_pwrdm", |
226 | .prcm_offs = DRA7XX_PRM_VPE_INST, | 226 | .prcm_offs = DRA7XX_PRM_VPE_INST, |
227 | .prcm_partition = DRA7XX_PRM_PARTITION, | 227 | .prcm_partition = DRA7XX_PRM_PARTITION, |
228 | .pwrsts = PWRSTS_OFF_RET_ON, | 228 | .pwrsts = PWRSTS_OFF_ON, |
229 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 229 | .pwrsts_logic_ret = PWRSTS_OFF, |
230 | .banks = 1, | 230 | .banks = 1, |
231 | .pwrsts_mem_ret = { | 231 | .pwrsts_mem_ret = { |
232 | [0] = PWRSTS_OFF_RET, /* vpe_bank */ | 232 | [0] = PWRSTS_OFF_RET, /* vpe_bank */ |
@@ -261,7 +261,7 @@ static struct powerdomain l3init_7xx_pwrdm = { | |||
261 | .prcm_offs = DRA7XX_PRM_L3INIT_INST, | 261 | .prcm_offs = DRA7XX_PRM_L3INIT_INST, |
262 | .prcm_partition = DRA7XX_PRM_PARTITION, | 262 | .prcm_partition = DRA7XX_PRM_PARTITION, |
263 | .pwrsts = PWRSTS_RET_ON, | 263 | .pwrsts = PWRSTS_RET_ON, |
264 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 264 | .pwrsts_logic_ret = PWRSTS_RET, |
265 | .banks = 3, | 265 | .banks = 3, |
266 | .pwrsts_mem_ret = { | 266 | .pwrsts_mem_ret = { |
267 | [0] = PWRSTS_OFF_RET, /* gmac_bank */ | 267 | [0] = PWRSTS_OFF_RET, /* gmac_bank */ |