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authorNishanth Menon2016-02-04 17:35:49 -0600
committerPraneeth Bajjuri2016-03-18 17:35:07 -0500
commit6d3d728516f4975be139aa66d23abb1ad64d6e3c (patch)
tree0355f4fa97030c350d75d7db42d059b7e62c7887
parentf6c0d755c485701e519aff3276b3fc9954bf98f7 (diff)
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ARM: OMAP: DRA7: powerdomain data: Remove CSWR with the exception of MPU
As per the latest definitions for DRA7/AM57xx SoCs, the internal memories of SoC do not support retention mode any longer (with the exception of MPU), as a result of the same, we also end up losing CSWR (where powerdomain state can be programmed to retention state). This implies that, with the exception of MPU power domain, all other power domains can either operate in "ON" mode OR where possible "OFF" mode (when permitted by lack of silicon errata). Change-Id: I34dbf9b2b5732cdf57172728859bce405f1d739b Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Ravikumar Kattekola <rk@ti.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/powerdomains7xx_data.c72
1 files changed, 37 insertions, 35 deletions
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index 0ec2d00f423..9fb8c0741ae 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -39,10 +39,10 @@ static struct powerdomain iva_7xx_pwrdm = {
39 .pwrsts_logic_ret = PWRSTS_OFF, 39 .pwrsts_logic_ret = PWRSTS_OFF,
40 .banks = 4, 40 .banks = 4,
41 .pwrsts_mem_ret = { 41 .pwrsts_mem_ret = {
42 [0] = PWRSTS_OFF_RET, /* hwa_mem */ 42 [0] = PWRSTS_OFF, /* hwa_mem */
43 [1] = PWRSTS_OFF_RET, /* sl2_mem */ 43 [1] = PWRSTS_OFF, /* sl2_mem */
44 [2] = PWRSTS_OFF_RET, /* tcm1_mem */ 44 [2] = PWRSTS_OFF, /* tcm1_mem */
45 [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 45 [3] = PWRSTS_OFF, /* tcm2_mem */
46 }, 46 },
47 .pwrsts_mem_on = { 47 .pwrsts_mem_on = {
48 [0] = PWRSTS_ON, /* hwa_mem */ 48 [0] = PWRSTS_ON, /* hwa_mem */
@@ -79,8 +79,8 @@ static struct powerdomain ipu_7xx_pwrdm = {
79 .pwrsts_logic_ret = PWRSTS_OFF, 79 .pwrsts_logic_ret = PWRSTS_OFF,
80 .banks = 2, 80 .banks = 2,
81 .pwrsts_mem_ret = { 81 .pwrsts_mem_ret = {
82 [0] = PWRSTS_OFF_RET, /* aessmem */ 82 [0] = PWRSTS_OFF, /* aessmem */
83 [1] = PWRSTS_OFF_RET, /* periphmem */ 83 [1] = PWRSTS_OFF, /* periphmem */
84 }, 84 },
85 .pwrsts_mem_on = { 85 .pwrsts_mem_on = {
86 [0] = PWRSTS_ON, /* aessmem */ 86 [0] = PWRSTS_ON, /* aessmem */
@@ -98,7 +98,7 @@ static struct powerdomain dss_7xx_pwrdm = {
98 .pwrsts_logic_ret = PWRSTS_OFF, 98 .pwrsts_logic_ret = PWRSTS_OFF,
99 .banks = 1, 99 .banks = 1,
100 .pwrsts_mem_ret = { 100 .pwrsts_mem_ret = {
101 [0] = PWRSTS_OFF_RET, /* dss_mem */ 101 [0] = PWRSTS_OFF, /* dss_mem */
102 }, 102 },
103 .pwrsts_mem_on = { 103 .pwrsts_mem_on = {
104 [0] = PWRSTS_ON, /* dss_mem */ 104 [0] = PWRSTS_ON, /* dss_mem */
@@ -111,12 +111,13 @@ static struct powerdomain l4per_7xx_pwrdm = {
111 .name = "l4per_pwrdm", 111 .name = "l4per_pwrdm",
112 .prcm_offs = DRA7XX_PRM_L4PER_INST, 112 .prcm_offs = DRA7XX_PRM_L4PER_INST,
113 .prcm_partition = DRA7XX_PRM_PARTITION, 113 .prcm_partition = DRA7XX_PRM_PARTITION,
114 .pwrsts = PWRSTS_RET_ON, 114 .pwrsts = PWRSTS_ON,
115 /* Due to assymetric aging constraints */
115 .pwrsts_logic_ret = PWRSTS_RET, 116 .pwrsts_logic_ret = PWRSTS_RET,
116 .banks = 2, 117 .banks = 2,
117 .pwrsts_mem_ret = { 118 .pwrsts_mem_ret = {
118 [0] = PWRSTS_OFF_RET, /* nonretained_bank */ 119 [0] = PWRSTS_ON, /* nonretained_bank */
119 [1] = PWRSTS_OFF_RET, /* retained_bank */ 120 [1] = PWRSTS_ON, /* retained_bank */
120 }, 121 },
121 .pwrsts_mem_on = { 122 .pwrsts_mem_on = {
122 [0] = PWRSTS_ON, /* nonretained_bank */ 123 [0] = PWRSTS_ON, /* nonretained_bank */
@@ -133,7 +134,7 @@ static struct powerdomain gpu_7xx_pwrdm = {
133 .pwrsts = PWRSTS_OFF_ON, 134 .pwrsts = PWRSTS_OFF_ON,
134 .banks = 1, 135 .banks = 1,
135 .pwrsts_mem_ret = { 136 .pwrsts_mem_ret = {
136 [0] = PWRSTS_OFF_RET, /* gpu_mem */ 137 [0] = PWRSTS_OFF, /* gpu_mem */
137 }, 138 },
138 .pwrsts_mem_on = { 139 .pwrsts_mem_on = {
139 [0] = PWRSTS_ON, /* gpu_mem */ 140 [0] = PWRSTS_ON, /* gpu_mem */
@@ -164,11 +165,11 @@ static struct powerdomain core_7xx_pwrdm = {
164 .pwrsts_logic_ret = PWRSTS_RET, 165 .pwrsts_logic_ret = PWRSTS_RET,
165 .banks = 5, 166 .banks = 5,
166 .pwrsts_mem_ret = { 167 .pwrsts_mem_ret = {
167 [0] = PWRSTS_OFF_RET, /* core_nret_bank */ 168 [0] = PWRSTS_ON, /* core_nret_bank */
168 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 169 [1] = PWRSTS_ON, /* core_ocmram */
169 [2] = PWRSTS_OFF_RET, /* core_other_bank */ 170 [2] = PWRSTS_ON, /* core_other_bank */
170 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ 171 [3] = PWRSTS_ON, /* ipu_l2ram */
171 [4] = PWRSTS_OFF_RET, /* ipu_unicache */ 172 [4] = PWRSTS_ON, /* ipu_unicache */
172 }, 173 },
173 .pwrsts_mem_on = { 174 .pwrsts_mem_on = {
174 [0] = PWRSTS_ON, /* core_nret_bank */ 175 [0] = PWRSTS_ON, /* core_nret_bank */
@@ -197,7 +198,7 @@ static struct powerdomain cpu0_7xx_pwrdm = {
197 .pwrsts_logic_ret = PWRSTS_RET, 198 .pwrsts_logic_ret = PWRSTS_RET,
198 .banks = 1, 199 .banks = 1,
199 .pwrsts_mem_ret = { 200 .pwrsts_mem_ret = {
200 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ 201 [0] = PWRSTS_OFF, /* cpu0_l1 */
201 }, 202 },
202 .pwrsts_mem_on = { 203 .pwrsts_mem_on = {
203 [0] = PWRSTS_ON, /* cpu0_l1 */ 204 [0] = PWRSTS_ON, /* cpu0_l1 */
@@ -213,7 +214,7 @@ static struct powerdomain cpu1_7xx_pwrdm = {
213 .pwrsts_logic_ret = PWRSTS_RET, 214 .pwrsts_logic_ret = PWRSTS_RET,
214 .banks = 1, 215 .banks = 1,
215 .pwrsts_mem_ret = { 216 .pwrsts_mem_ret = {
216 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ 217 [0] = PWRSTS_OFF, /* cpu1_l1 */
217 }, 218 },
218 .pwrsts_mem_on = { 219 .pwrsts_mem_on = {
219 [0] = PWRSTS_ON, /* cpu1_l1 */ 220 [0] = PWRSTS_ON, /* cpu1_l1 */
@@ -229,7 +230,7 @@ static struct powerdomain vpe_7xx_pwrdm = {
229 .pwrsts_logic_ret = PWRSTS_OFF, 230 .pwrsts_logic_ret = PWRSTS_OFF,
230 .banks = 1, 231 .banks = 1,
231 .pwrsts_mem_ret = { 232 .pwrsts_mem_ret = {
232 [0] = PWRSTS_OFF_RET, /* vpe_bank */ 233 [0] = PWRSTS_OFF, /* vpe_bank */
233 }, 234 },
234 .pwrsts_mem_on = { 235 .pwrsts_mem_on = {
235 [0] = PWRSTS_ON, /* vpe_bank */ 236 [0] = PWRSTS_ON, /* vpe_bank */
@@ -260,13 +261,14 @@ static struct powerdomain l3init_7xx_pwrdm = {
260 .name = "l3init_pwrdm", 261 .name = "l3init_pwrdm",
261 .prcm_offs = DRA7XX_PRM_L3INIT_INST, 262 .prcm_offs = DRA7XX_PRM_L3INIT_INST,
262 .prcm_partition = DRA7XX_PRM_PARTITION, 263 .prcm_partition = DRA7XX_PRM_PARTITION,
263 .pwrsts = PWRSTS_RET_ON, 264 /* Due to Asymettric Aging constraints */
265 .pwrsts = PWRSTS_ON,
264 .pwrsts_logic_ret = PWRSTS_RET, 266 .pwrsts_logic_ret = PWRSTS_RET,
265 .banks = 3, 267 .banks = 3,
266 .pwrsts_mem_ret = { 268 .pwrsts_mem_ret = {
267 [0] = PWRSTS_OFF_RET, /* gmac_bank */ 269 [0] = PWRSTS_ON, /* gmac_bank */
268 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */ 270 [1] = PWRSTS_ON, /* l3init_bank1 */
269 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ 271 [2] = PWRSTS_ON, /* l3init_bank2 */
270 }, 272 },
271 .pwrsts_mem_on = { 273 .pwrsts_mem_on = {
272 [0] = PWRSTS_ON, /* gmac_bank */ 274 [0] = PWRSTS_ON, /* gmac_bank */
@@ -284,7 +286,7 @@ static struct powerdomain eve3_7xx_pwrdm = {
284 .pwrsts = PWRSTS_OFF_ON, 286 .pwrsts = PWRSTS_OFF_ON,
285 .banks = 1, 287 .banks = 1,
286 .pwrsts_mem_ret = { 288 .pwrsts_mem_ret = {
287 [0] = PWRSTS_OFF_RET, /* eve3_bank */ 289 [0] = PWRSTS_OFF, /* eve3_bank */
288 }, 290 },
289 .pwrsts_mem_on = { 291 .pwrsts_mem_on = {
290 [0] = PWRSTS_ON, /* eve3_bank */ 292 [0] = PWRSTS_ON, /* eve3_bank */
@@ -300,7 +302,7 @@ static struct powerdomain emu_7xx_pwrdm = {
300 .pwrsts = PWRSTS_OFF_ON, 302 .pwrsts = PWRSTS_OFF_ON,
301 .banks = 1, 303 .banks = 1,
302 .pwrsts_mem_ret = { 304 .pwrsts_mem_ret = {
303 [0] = PWRSTS_OFF_RET, /* emu_bank */ 305 [0] = PWRSTS_OFF, /* emu_bank */
304 }, 306 },
305 .pwrsts_mem_on = { 307 .pwrsts_mem_on = {
306 [0] = PWRSTS_ON, /* emu_bank */ 308 [0] = PWRSTS_ON, /* emu_bank */
@@ -315,9 +317,9 @@ static struct powerdomain dsp2_7xx_pwrdm = {
315 .pwrsts = PWRSTS_OFF_ON, 317 .pwrsts = PWRSTS_OFF_ON,
316 .banks = 3, 318 .banks = 3,
317 .pwrsts_mem_ret = { 319 .pwrsts_mem_ret = {
318 [0] = PWRSTS_OFF_RET, /* dsp2_edma */ 320 [0] = PWRSTS_OFF, /* dsp2_edma */
319 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */ 321 [1] = PWRSTS_OFF, /* dsp2_l1 */
320 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ 322 [2] = PWRSTS_OFF, /* dsp2_l2 */
321 }, 323 },
322 .pwrsts_mem_on = { 324 .pwrsts_mem_on = {
323 [0] = PWRSTS_ON, /* dsp2_edma */ 325 [0] = PWRSTS_ON, /* dsp2_edma */
@@ -335,9 +337,9 @@ static struct powerdomain dsp1_7xx_pwrdm = {
335 .pwrsts = PWRSTS_OFF_ON, 337 .pwrsts = PWRSTS_OFF_ON,
336 .banks = 3, 338 .banks = 3,
337 .pwrsts_mem_ret = { 339 .pwrsts_mem_ret = {
338 [0] = PWRSTS_OFF_RET, /* dsp1_edma */ 340 [0] = PWRSTS_OFF, /* dsp1_edma */
339 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */ 341 [1] = PWRSTS_OFF, /* dsp1_l1 */
340 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ 342 [2] = PWRSTS_OFF, /* dsp1_l2 */
341 }, 343 },
342 .pwrsts_mem_on = { 344 .pwrsts_mem_on = {
343 [0] = PWRSTS_ON, /* dsp1_edma */ 345 [0] = PWRSTS_ON, /* dsp1_edma */
@@ -355,7 +357,7 @@ static struct powerdomain cam_7xx_pwrdm = {
355 .pwrsts = PWRSTS_OFF_ON, 357 .pwrsts = PWRSTS_OFF_ON,
356 .banks = 1, 358 .banks = 1,
357 .pwrsts_mem_ret = { 359 .pwrsts_mem_ret = {
358 [0] = PWRSTS_OFF_RET, /* vip_bank */ 360 [0] = PWRSTS_OFF, /* vip_bank */
359 }, 361 },
360 .pwrsts_mem_on = { 362 .pwrsts_mem_on = {
361 [0] = PWRSTS_ON, /* vip_bank */ 363 [0] = PWRSTS_ON, /* vip_bank */
@@ -371,7 +373,7 @@ static struct powerdomain eve4_7xx_pwrdm = {
371 .pwrsts = PWRSTS_OFF_ON, 373 .pwrsts = PWRSTS_OFF_ON,
372 .banks = 1, 374 .banks = 1,
373 .pwrsts_mem_ret = { 375 .pwrsts_mem_ret = {
374 [0] = PWRSTS_OFF_RET, /* eve4_bank */ 376 [0] = PWRSTS_OFF, /* eve4_bank */
375 }, 377 },
376 .pwrsts_mem_on = { 378 .pwrsts_mem_on = {
377 [0] = PWRSTS_ON, /* eve4_bank */ 379 [0] = PWRSTS_ON, /* eve4_bank */
@@ -387,7 +389,7 @@ static struct powerdomain eve2_7xx_pwrdm = {
387 .pwrsts = PWRSTS_OFF_ON, 389 .pwrsts = PWRSTS_OFF_ON,
388 .banks = 1, 390 .banks = 1,
389 .pwrsts_mem_ret = { 391 .pwrsts_mem_ret = {
390 [0] = PWRSTS_OFF_RET, /* eve2_bank */ 392 [0] = PWRSTS_OFF, /* eve2_bank */
391 }, 393 },
392 .pwrsts_mem_on = { 394 .pwrsts_mem_on = {
393 [0] = PWRSTS_ON, /* eve2_bank */ 395 [0] = PWRSTS_ON, /* eve2_bank */
@@ -403,7 +405,7 @@ static struct powerdomain eve1_7xx_pwrdm = {
403 .pwrsts = PWRSTS_OFF_ON, 405 .pwrsts = PWRSTS_OFF_ON,
404 .banks = 1, 406 .banks = 1,
405 .pwrsts_mem_ret = { 407 .pwrsts_mem_ret = {
406 [0] = PWRSTS_OFF_RET, /* eve1_bank */ 408 [0] = PWRSTS_OFF, /* eve1_bank */
407 }, 409 },
408 .pwrsts_mem_on = { 410 .pwrsts_mem_on = {
409 [0] = PWRSTS_ON, /* eve1_bank */ 411 [0] = PWRSTS_ON, /* eve1_bank */
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