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authorVishal Mahaveer2016-03-18 11:47:14 -0500
committerVishal Mahaveer2016-03-18 11:58:21 -0500
commite5d8fd1f81810d8172f1a9fff05e8a2e8546d660 (patch)
tree26a57c0b54200229bd37667ba6d09ac9686e4b4e
parent123a433acc383461b513cee46acc9a2d550c5a9b (diff)
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ARM: dts: dra7-evm: mmc: fix typos in register names and values
Fix typos in register names and values used for mmc1 and mmc4 manual mode values. Change-Id: I7294e95580e0622b552d896aff78bbab4d8464a9 Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts46
1 files changed, 23 insertions, 23 deletions
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 181d6e55975..5e33ddb8326 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -500,17 +500,17 @@
500 500
501 mmc1_iodelay_sdr104_conf_sr20: mmc1_iodelay_sdr104_conf_sr20 { 501 mmc1_iodelay_sdr104_conf_sr20: mmc1_iodelay_sdr104_conf_sr20 {
502 pinctrl-single,pins = < 502 pinctrl-single,pins = <
503 0x620 (A_DELAY(1063) | G_DELAY(17)) /* CFG_MMC1_CLK_OUT */ 503 0x620 (A_DELAY(600) | G_DELAY(400)) /* CFG_MMC1_CLK_OUT */
504 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ 504 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
505 0x62c (A_DELAY(23) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ 505 0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
506 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ 506 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
507 0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ 507 0x638 (A_DELAY(30) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
508 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ 508 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
509 0x644 (A_DELAY(2) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ 509 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
510 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ 510 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
511 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ 511 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
512 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ 512 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
513 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ 513 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
514 >; 514 >;
515 }; 515 };
516 516
@@ -650,10 +650,10 @@
650 0x870 (A_DELAY(582) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */ 650 0x870 (A_DELAY(582) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
651 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */ 651 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
652 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */ 652 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
653 0x87C (A_DELAY(391) | G_DELAY(0)) /* RCFG_UART2_RTSN_IN */ 653 0x87C (A_DELAY(391) | G_DELAY(0)) /* CFG_UART2_RTSN_IN */
654 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */ 654 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
655 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */ 655 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
656 0x888 (A_DELAY(561) | G_DELAY(0)) /* RCFG_UART2_RXD_IN */ 656 0x888 (A_DELAY(561) | G_DELAY(0)) /* CFG_UART2_RXD_IN */
657 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */ 657 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
658 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */ 658 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
659 0x894 (A_DELAY(588) | G_DELAY(0)) /* CFG_UART2_TXD_IN */ 659 0x894 (A_DELAY(588) | G_DELAY(0)) /* CFG_UART2_TXD_IN */
@@ -672,10 +672,10 @@
672 0x870 (A_DELAY(1913) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */ 672 0x870 (A_DELAY(1913) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
673 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */ 673 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
674 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */ 674 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
675 0x87C (A_DELAY(1721) | G_DELAY(0)) /* RCFG_UART2_RTSN_IN */ 675 0x87C (A_DELAY(1721) | G_DELAY(0)) /* CFG_UART2_RTSN_IN */
676 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */ 676 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
677 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */ 677 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
678 0x888 (A_DELAY(1891) | G_DELAY(0)) /* RCFG_UART2_RXD_IN */ 678 0x888 (A_DELAY(1891) | G_DELAY(0)) /* CFG_UART2_RXD_IN */
679 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */ 679 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
680 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */ 680 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
681 0x894 (A_DELAY(1919) | G_DELAY(0)) /* CFG_UART2_TXD_IN */ 681 0x894 (A_DELAY(1919) | G_DELAY(0)) /* CFG_UART2_TXD_IN */
@@ -691,16 +691,16 @@
691 0x84c (A_DELAY(307) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */ 691 0x84c (A_DELAY(307) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */
692 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */ 692 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */
693 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */ 693 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */
694 0x870 (A_DELAY(683) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */ 694 0x870 (A_DELAY(785) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
695 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */ 695 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
696 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */ 696 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
697 0x87C (A_DELAY(835) | G_DELAY(0)) /* RCFG_UART2_RTSN_IN */ 697 0x87C (A_DELAY(613) | G_DELAY(0)) /* CFG_UART2_RTSN_IN */
698 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */ 698 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
699 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */ 699 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
700 0x888 (A_DELAY(785) | G_DELAY(0)) /* RCFG_UART2_RXD_IN */ 700 0x888 (A_DELAY(683) | G_DELAY(0)) /* CFG_UART2_RXD_IN */
701 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */ 701 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
702 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */ 702 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
703 0x894 (A_DELAY(613) | G_DELAY(0)) /* CFG_UART2_TXD_IN */ 703 0x894 (A_DELAY(835) | G_DELAY(0)) /* CFG_UART2_TXD_IN */
704 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */ 704 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */
705 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */ 705 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */
706 >; 706 >;
@@ -713,16 +713,16 @@
713 0x84c (A_DELAY(1834) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */ 713 0x84c (A_DELAY(1834) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */
714 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */ 714 0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */
715 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */ 715 0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */
716 0x870 (A_DELAY(1935) | G_DELAY(128)) /* CFG_UART2_CTSN_IN */ 716 0x870 (A_DELAY(2165) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
717 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */ 717 0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
718 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */ 718 0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
719 0x87C (A_DELAY(2172) | G_DELAY(44)) /* RCFG_UART2_RTSN_IN */ 719 0x87C (A_DELAY(1929) | G_DELAY(64)) /* CFG_UART2_RTSN_IN */
720 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */ 720 0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
721 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */ 721 0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
722 0x888 (A_DELAY(2165) | G_DELAY(0)) /* RCFG_UART2_RXD_IN */ 722 0x888 (A_DELAY(1935) | G_DELAY(128)) /* CFG_UART2_RXD_IN */
723 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */ 723 0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
724 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */ 724 0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
725 0x894 (A_DELAY(1929) | G_DELAY(64)) /* CFG_UART2_TXD_IN */ 725 0x894 (A_DELAY(2172) | G_DELAY(44)) /* CFG_UART2_TXD_IN */
726 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */ 726 0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */
727 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */ 727 0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */
728 >; 728 >;