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authorNishanth Menon2016-02-04 17:35:48 -0600
committerPraneeth Bajjuri2016-03-18 17:35:07 -0500
commitf6c0d755c485701e519aff3276b3fc9954bf98f7 (patch)
tree8973a9ff0b6a46f44ef1fc179a29d7fd47097df5
parent6d214e2744799283c4566b271b4049414dc28885 (diff)
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ARM: OMAP: DRA7: powerdomain data: Fix "ON" state for memories
When the power domain is in "ON" state, the memories should be always in "ON", even though the hardware register allows other states to be written, wrong states may confuse certain hardware blocks. Change-Id: Idcaedaf8cd97b5be78c44315126b6d1a1779aaa9 Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Ravikumar Kattekola <rk@ti.com>
-rw-r--r--arch/arm/mach-omap2/powerdomains7xx_data.c66
1 files changed, 33 insertions, 33 deletions
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index 714d4d71f80..0ec2d00f423 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -45,10 +45,10 @@ static struct powerdomain iva_7xx_pwrdm = {
45 [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 45 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
46 }, 46 },
47 .pwrsts_mem_on = { 47 .pwrsts_mem_on = {
48 [0] = PWRSTS_OFF_RET, /* hwa_mem */ 48 [0] = PWRSTS_ON, /* hwa_mem */
49 [1] = PWRSTS_OFF_RET, /* sl2_mem */ 49 [1] = PWRSTS_ON, /* sl2_mem */
50 [2] = PWRSTS_OFF_RET, /* tcm1_mem */ 50 [2] = PWRSTS_ON, /* tcm1_mem */
51 [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 51 [3] = PWRSTS_ON, /* tcm2_mem */
52 }, 52 },
53 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 53 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
54}; 54};
@@ -83,8 +83,8 @@ static struct powerdomain ipu_7xx_pwrdm = {
83 [1] = PWRSTS_OFF_RET, /* periphmem */ 83 [1] = PWRSTS_OFF_RET, /* periphmem */
84 }, 84 },
85 .pwrsts_mem_on = { 85 .pwrsts_mem_on = {
86 [0] = PWRSTS_OFF_RET, /* aessmem */ 86 [0] = PWRSTS_ON, /* aessmem */
87 [1] = PWRSTS_OFF_RET, /* periphmem */ 87 [1] = PWRSTS_ON, /* periphmem */
88 }, 88 },
89 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 89 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
90}; 90};
@@ -101,7 +101,7 @@ static struct powerdomain dss_7xx_pwrdm = {
101 [0] = PWRSTS_OFF_RET, /* dss_mem */ 101 [0] = PWRSTS_OFF_RET, /* dss_mem */
102 }, 102 },
103 .pwrsts_mem_on = { 103 .pwrsts_mem_on = {
104 [0] = PWRSTS_OFF_RET, /* dss_mem */ 104 [0] = PWRSTS_ON, /* dss_mem */
105 }, 105 },
106 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 106 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
107}; 107};
@@ -119,8 +119,8 @@ static struct powerdomain l4per_7xx_pwrdm = {
119 [1] = PWRSTS_OFF_RET, /* retained_bank */ 119 [1] = PWRSTS_OFF_RET, /* retained_bank */
120 }, 120 },
121 .pwrsts_mem_on = { 121 .pwrsts_mem_on = {
122 [0] = PWRSTS_OFF_RET, /* nonretained_bank */ 122 [0] = PWRSTS_ON, /* nonretained_bank */
123 [1] = PWRSTS_OFF_RET, /* retained_bank */ 123 [1] = PWRSTS_ON, /* retained_bank */
124 }, 124 },
125 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 125 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
126}; 126};
@@ -136,7 +136,7 @@ static struct powerdomain gpu_7xx_pwrdm = {
136 [0] = PWRSTS_OFF_RET, /* gpu_mem */ 136 [0] = PWRSTS_OFF_RET, /* gpu_mem */
137 }, 137 },
138 .pwrsts_mem_on = { 138 .pwrsts_mem_on = {
139 [0] = PWRSTS_OFF_RET, /* gpu_mem */ 139 [0] = PWRSTS_ON, /* gpu_mem */
140 }, 140 },
141 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 141 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
142}; 142};
@@ -171,11 +171,11 @@ static struct powerdomain core_7xx_pwrdm = {
171 [4] = PWRSTS_OFF_RET, /* ipu_unicache */ 171 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
172 }, 172 },
173 .pwrsts_mem_on = { 173 .pwrsts_mem_on = {
174 [0] = PWRSTS_OFF_RET, /* core_nret_bank */ 174 [0] = PWRSTS_ON, /* core_nret_bank */
175 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 175 [1] = PWRSTS_ON, /* core_ocmram */
176 [2] = PWRSTS_OFF_RET, /* core_other_bank */ 176 [2] = PWRSTS_ON, /* core_other_bank */
177 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ 177 [3] = PWRSTS_ON, /* ipu_l2ram */
178 [4] = PWRSTS_OFF_RET, /* ipu_unicache */ 178 [4] = PWRSTS_ON, /* ipu_unicache */
179 }, 179 },
180 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 180 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
181}; 181};
@@ -232,7 +232,7 @@ static struct powerdomain vpe_7xx_pwrdm = {
232 [0] = PWRSTS_OFF_RET, /* vpe_bank */ 232 [0] = PWRSTS_OFF_RET, /* vpe_bank */
233 }, 233 },
234 .pwrsts_mem_on = { 234 .pwrsts_mem_on = {
235 [0] = PWRSTS_OFF_RET, /* vpe_bank */ 235 [0] = PWRSTS_ON, /* vpe_bank */
236 }, 236 },
237 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 237 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
238}; 238};
@@ -250,8 +250,8 @@ static struct powerdomain mpu_7xx_pwrdm = {
250 [1] = PWRSTS_RET, /* mpu_ram */ 250 [1] = PWRSTS_RET, /* mpu_ram */
251 }, 251 },
252 .pwrsts_mem_on = { 252 .pwrsts_mem_on = {
253 [0] = PWRSTS_OFF_RET, /* mpu_l2 */ 253 [0] = PWRSTS_ON, /* mpu_l2 */
254 [1] = PWRSTS_OFF_RET, /* mpu_ram */ 254 [1] = PWRSTS_ON, /* mpu_ram */
255 }, 255 },
256}; 256};
257 257
@@ -269,9 +269,9 @@ static struct powerdomain l3init_7xx_pwrdm = {
269 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ 269 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
270 }, 270 },
271 .pwrsts_mem_on = { 271 .pwrsts_mem_on = {
272 [0] = PWRSTS_OFF_RET, /* gmac_bank */ 272 [0] = PWRSTS_ON, /* gmac_bank */
273 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */ 273 [1] = PWRSTS_ON, /* l3init_bank1 */
274 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ 274 [2] = PWRSTS_ON, /* l3init_bank2 */
275 }, 275 },
276 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 276 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
277}; 277};
@@ -287,7 +287,7 @@ static struct powerdomain eve3_7xx_pwrdm = {
287 [0] = PWRSTS_OFF_RET, /* eve3_bank */ 287 [0] = PWRSTS_OFF_RET, /* eve3_bank */
288 }, 288 },
289 .pwrsts_mem_on = { 289 .pwrsts_mem_on = {
290 [0] = PWRSTS_OFF_RET, /* eve3_bank */ 290 [0] = PWRSTS_ON, /* eve3_bank */
291 }, 291 },
292 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 292 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
293}; 293};
@@ -303,7 +303,7 @@ static struct powerdomain emu_7xx_pwrdm = {
303 [0] = PWRSTS_OFF_RET, /* emu_bank */ 303 [0] = PWRSTS_OFF_RET, /* emu_bank */
304 }, 304 },
305 .pwrsts_mem_on = { 305 .pwrsts_mem_on = {
306 [0] = PWRSTS_OFF_RET, /* emu_bank */ 306 [0] = PWRSTS_ON, /* emu_bank */
307 }, 307 },
308}; 308};
309 309
@@ -320,9 +320,9 @@ static struct powerdomain dsp2_7xx_pwrdm = {
320 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ 320 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
321 }, 321 },
322 .pwrsts_mem_on = { 322 .pwrsts_mem_on = {
323 [0] = PWRSTS_OFF_RET, /* dsp2_edma */ 323 [0] = PWRSTS_ON, /* dsp2_edma */
324 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */ 324 [1] = PWRSTS_ON, /* dsp2_l1 */
325 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ 325 [2] = PWRSTS_ON, /* dsp2_l2 */
326 }, 326 },
327 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 327 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
328}; 328};
@@ -340,9 +340,9 @@ static struct powerdomain dsp1_7xx_pwrdm = {
340 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ 340 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
341 }, 341 },
342 .pwrsts_mem_on = { 342 .pwrsts_mem_on = {
343 [0] = PWRSTS_OFF_RET, /* dsp1_edma */ 343 [0] = PWRSTS_ON, /* dsp1_edma */
344 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */ 344 [1] = PWRSTS_ON, /* dsp1_l1 */
345 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ 345 [2] = PWRSTS_ON, /* dsp1_l2 */
346 }, 346 },
347 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 347 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
348}; 348};
@@ -358,7 +358,7 @@ static struct powerdomain cam_7xx_pwrdm = {
358 [0] = PWRSTS_OFF_RET, /* vip_bank */ 358 [0] = PWRSTS_OFF_RET, /* vip_bank */
359 }, 359 },
360 .pwrsts_mem_on = { 360 .pwrsts_mem_on = {
361 [0] = PWRSTS_OFF_RET, /* vip_bank */ 361 [0] = PWRSTS_ON, /* vip_bank */
362 }, 362 },
363 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 363 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
364}; 364};
@@ -374,7 +374,7 @@ static struct powerdomain eve4_7xx_pwrdm = {
374 [0] = PWRSTS_OFF_RET, /* eve4_bank */ 374 [0] = PWRSTS_OFF_RET, /* eve4_bank */
375 }, 375 },
376 .pwrsts_mem_on = { 376 .pwrsts_mem_on = {
377 [0] = PWRSTS_OFF_RET, /* eve4_bank */ 377 [0] = PWRSTS_ON, /* eve4_bank */
378 }, 378 },
379 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 379 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
380}; 380};
@@ -390,7 +390,7 @@ static struct powerdomain eve2_7xx_pwrdm = {
390 [0] = PWRSTS_OFF_RET, /* eve2_bank */ 390 [0] = PWRSTS_OFF_RET, /* eve2_bank */
391 }, 391 },
392 .pwrsts_mem_on = { 392 .pwrsts_mem_on = {
393 [0] = PWRSTS_OFF_RET, /* eve2_bank */ 393 [0] = PWRSTS_ON, /* eve2_bank */
394 }, 394 },
395 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 395 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
396}; 396};
@@ -406,7 +406,7 @@ static struct powerdomain eve1_7xx_pwrdm = {
406 [0] = PWRSTS_OFF_RET, /* eve1_bank */ 406 [0] = PWRSTS_OFF_RET, /* eve1_bank */
407 }, 407 },
408 .pwrsts_mem_on = { 408 .pwrsts_mem_on = {
409 [0] = PWRSTS_OFF_RET, /* eve1_bank */ 409 [0] = PWRSTS_ON, /* eve1_bank */
410 }, 410 },
411 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 411 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
412}; 412};