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author | Suman Anna | 2013-12-16 14:19:46 -0600 |
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committer | Suman Anna | 2014-08-28 22:21:45 -0500 |
commit | 6d6dd44c55638d54a151bf2ae6cc77b2f4e459d0 (patch) | |
tree | 9c6cd1b8fa4505ba5356e43810207f19933d5e9b | |
parent | 99c903651a2050d14a8cad866d1e284fb4f15b71 (diff) | |
download | kernel-video-6d6dd44c55638d54a151bf2ae6cc77b2f4e459d0.tar.gz kernel-video-6d6dd44c55638d54a151bf2ae6cc77b2f4e459d0.tar.xz kernel-video-6d6dd44c55638d54a151bf2ae6cc77b2f4e459d0.zip |
ARM: OMAP: DRA7: change IPU1 clk domain to SWSUP for proper boot
This patch fixes a boot hang of the IPU1 processor on DRA7xx caused
by an improper AMMU/Unicache state upon initial deassertion of reset.
All the Cortex M3/M4 IPU processor subsystems in OMAP SoCs have a
AMMU/Unicache IP that dictates the memory attributes for addresses
seen by the processor cores. The AMMU/Unicache is configured/enabled
by the SCACHE_CONFIG.BYPASS bit - a value of 1 enables the cache and
mandates all addresses accessed by M3/M4 be defined in the AMMU. This
bit is not programmable from the host processor. The M3/M4 boot
sequence starts out with the AMMU/Unicache in disabled state, and
SYS/BIOS programs the AMMU regions and enables the Unicache during
one of its initial boot steps. This SCACHE_CONFIG.BYPASS bit is
however enabled by default whenever a RET reset is applied to the
IP, irrespective of whether it was previously enabled or not. The
AMMU registers lose their context whenever the reset is applied. The
reset is effective as long as the MMU portion of the subsystem is
enabled and clocked. This behavior is common to all the IPU subsystems
that have an AMMU/Unicache.
The IPU boot sequence involves enabling and programming the MMU, and
loading the processor and releasing the reset(s) for the processor.
The PM setup code currently sets the target state for most of the
power domains to RET, including the IPU1 power domain. The L2 MMU
can be enabled, programmed and accessed properly just fine with the
domain in hardware supervised mode, while the power domain goes
through a RET->ON->RET transition during the programming sequence.
However, the ON->RET transition asserts a RET reset, and the
SCACHE_CONFIG.BYPASS bit gets auto-set. An AMMU fault is thrown
immediately when the M3/M4 core's reset is released since the
first instruction address itself will not be defined in any valid
AMMU regions.
The ON->RET transition happens automatically on the power domain after
enabling the iommu due to the hardware supervised mode. Changing the
mode to SWSUP only maintains the domain in ON state after the iommu
is programmed and results in having the AMMU/Unicache in the expected
reset condition when booting the IPU processor.
Note that the current issue is seen only on kernels with Power
Management enabled and only for IPU1 as the IPU2 subsystem is within
CORE power domain, and CORE RET is not supported at the moment.
Signed-off-by: Suman Anna <s-anna@ti.com>
-rw-r--r-- | arch/arm/mach-omap2/clockdomains7xx_data.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c index 57d5df0c1fb..9df148dd30e 100644 --- a/arch/arm/mach-omap2/clockdomains7xx_data.c +++ b/arch/arm/mach-omap2/clockdomains7xx_data.c | |||
@@ -373,7 +373,7 @@ static struct clockdomain ipu1_7xx_clkdm = { | |||
373 | .dep_bit = DRA7XX_IPU1_STATDEP_SHIFT, | 373 | .dep_bit = DRA7XX_IPU1_STATDEP_SHIFT, |
374 | .wkdep_srcs = ipu1_wkup_sleep_deps, | 374 | .wkdep_srcs = ipu1_wkup_sleep_deps, |
375 | .sleepdep_srcs = ipu1_wkup_sleep_deps, | 375 | .sleepdep_srcs = ipu1_wkup_sleep_deps, |
376 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 376 | .flags = CLKDM_CAN_SWSUP, |
377 | }; | 377 | }; |
378 | 378 | ||
379 | static struct clockdomain ipu2_7xx_clkdm = { | 379 | static struct clockdomain ipu2_7xx_clkdm = { |