Merge branch 'p-ti-linux-3.8.y' into p-ti-android-3.8.y

* p-ti-linux-3.8.y:
  clk: omap5: Add CLK_SET_RATE_PARENT flag to gpu clocks
  clk: dra7xx: Add CLK_SET_RATE_PARENT flag to gpu clocks

Change-Id: Ie676c6535e575f87a7ce6f978dd574898de2ace8
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

2 files changed, 15 insertions, 11 deletions

diff --git a/arch/arm/mach-omap2/cclock54xx_data.c b/arch/arm/mach-omap2/cclock54xx_data.c
index 4a17f12caa9..4228e2ba37a 100644
--- a/arch/arm/mach-omap2/cclock54xx_data.c
+++ b/arch/arm/mach-omap2/cclock54xx_data.c
@@ -1018,12 +1018,14 @@ static const char *gpu_core_gclk_mux_parents[] = {
         "dpll_core_h14x2_ck", "dpll_per_h14x2_ck",
 };
 
-DEFINE_CLK_MUX(gpu_core_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0,
-               OMAP54XX_CM_GPU_GPU_CLKCTRL, OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT,
+DEFINE_CLK_MUX(gpu_core_gclk_mux, gpu_core_gclk_mux_parents, NULL,
+               CLK_SET_RATE_PARENT, OMAP54XX_CM_GPU_GPU_CLKCTRL,
+               OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT,
                OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH, 0x0, NULL);
 
-DEFINE_CLK_MUX(gpu_hyd_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0,
-               OMAP54XX_CM_GPU_GPU_CLKCTRL, OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT,
+DEFINE_CLK_MUX(gpu_hyd_gclk_mux, gpu_core_gclk_mux_parents, NULL,
+               CLK_SET_RATE_PARENT, OMAP54XX_CM_GPU_GPU_CLKCTRL,
+               OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT,
                OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH, 0x0, NULL);
 
 DEFINE_CLK_DIVIDER(hsi_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
diff --git a/arch/arm/mach-omap2/cclock7xx_data.c b/arch/arm/mach-omap2/cclock7xx_data.c
index e77d58771c7..66aec148260 100644
--- a/arch/arm/mach-omap2/cclock7xx_data.c
+++ b/arch/arm/mach-omap2/cclock7xx_data.c
@@ -1525,13 +1525,15 @@ static const char *gpu_core_gclk_mux_parents[] = {
         "dpll_core_h14x2_ck", "dpll_per_h14x2_ck", "dpll_gpu_m2_ck",
 };
 
-DEFINE_CLK_MUX(gpu_core_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0,
-               DRA7XX_CM_GPU_GPU_CLKCTRL, DRA7XX_CLKSEL_CORE_CLK_SHIFT,
-               DRA7XX_CLKSEL_CORE_CLK_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(gpu_hyd_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0,
-               DRA7XX_CM_GPU_GPU_CLKCTRL, DRA7XX_CLKSEL_HYD_CLK_SHIFT,
-               DRA7XX_CLKSEL_HYD_CLK_WIDTH, 0x0, NULL);
+DEFINE_CLK_MUX(gpu_core_gclk_mux, gpu_core_gclk_mux_parents, NULL,
+               CLK_SET_RATE_PARENT, DRA7XX_CM_GPU_GPU_CLKCTRL,
+               DRA7XX_CLKSEL_CORE_CLK_SHIFT, DRA7XX_CLKSEL_CORE_CLK_WIDTH,
+               0x0, NULL);
+
+DEFINE_CLK_MUX(gpu_hyd_gclk_mux, gpu_core_gclk_mux_parents, NULL,
+               CLK_SET_RATE_PARENT, DRA7XX_CM_GPU_GPU_CLKCTRL,
+               DRA7XX_CLKSEL_HYD_CLK_SHIFT, DRA7XX_CLKSEL_HYD_CLK_WIDTH,
+               0x0, NULL);
 
 static const char *ipu1_gfclk_mux_parents[] = {
         "dpll_abe_m2x2_ck", "dpll_core_h22x2_ck",