diff options
Diffstat (limited to 'arch/arm/mach-omap2/cclock7xx_data.c')
-rw-r--r-- | arch/arm/mach-omap2/cclock7xx_data.c | 39 |
1 files changed, 22 insertions, 17 deletions
diff --git a/arch/arm/mach-omap2/cclock7xx_data.c b/arch/arm/mach-omap2/cclock7xx_data.c index e77d58771c7..70bbe2c7760 100644 --- a/arch/arm/mach-omap2/cclock7xx_data.c +++ b/arch/arm/mach-omap2/cclock7xx_data.c | |||
@@ -40,8 +40,9 @@ | |||
40 | #include "prm-regbits-7xx.h" | 40 | #include "prm-regbits-7xx.h" |
41 | #include "control.h" | 41 | #include "control.h" |
42 | 42 | ||
43 | #define DRA7_DPLL_ABE_DEFFREQ 361267200 | 43 | #define DRA7_DPLL_ABE_DEFFREQ 180633600 |
44 | #define DRA7_DPLL_GMAC_DEFFREQ 1000000000 | 44 | #define DRA7_DPLL_GMAC_DEFFREQ 1000000000 |
45 | #define DRA7_DPLL_USB_DEFFREQ 960000000 | ||
45 | 46 | ||
46 | /* Root clocks */ | 47 | /* Root clocks */ |
47 | 48 | ||
@@ -51,7 +52,7 @@ DEFINE_CLK_FIXED_RATE(atl_clkin1_ck, CLK_IS_ROOT, 0, 0x0); | |||
51 | 52 | ||
52 | DEFINE_CLK_FIXED_RATE(atl_clkin2_ck, CLK_IS_ROOT, 0, 0x0); | 53 | DEFINE_CLK_FIXED_RATE(atl_clkin2_ck, CLK_IS_ROOT, 0, 0x0); |
53 | 54 | ||
54 | DEFINE_CLK_FIXED_RATE(atlclkin3_ck, CLK_IS_ROOT, 0, 0x0); | 55 | DEFINE_CLK_FIXED_RATE(atl_clkin3_ck, CLK_IS_ROOT, 0, 0x0); |
55 | 56 | ||
56 | DEFINE_CLK_FIXED_RATE(hdmi_clkin_ck, CLK_IS_ROOT, 0, 0x0); | 57 | DEFINE_CLK_FIXED_RATE(hdmi_clkin_ck, CLK_IS_ROOT, 0, 0x0); |
57 | 58 | ||
@@ -1245,7 +1246,7 @@ static struct clk_hw_omap hdmi_div_clk_hw = { | |||
1245 | DEFINE_STRUCT_CLK(hdmi_div_clk, hdmi_dclk_div_parents, apll_pcie_clkvcoldo_ops); | 1246 | DEFINE_STRUCT_CLK(hdmi_div_clk, hdmi_dclk_div_parents, apll_pcie_clkvcoldo_ops); |
1246 | 1247 | ||
1247 | DEFINE_CLK_MUX(hdmi_dpll_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0, | 1248 | DEFINE_CLK_MUX(hdmi_dpll_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0, |
1248 | DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT, | 1249 | DRA7XX_CM_CLKSEL_HDMI_PLL_SYS, DRA7XX_CLKSEL_SHIFT, |
1249 | DRA7XX_CLKSEL_WIDTH, 0x0, NULL); | 1250 | DRA7XX_CLKSEL_WIDTH, 0x0, NULL); |
1250 | 1251 | ||
1251 | static struct clk l3_iclk_div; | 1252 | static struct clk l3_iclk_div; |
@@ -1525,13 +1526,15 @@ static const char *gpu_core_gclk_mux_parents[] = { | |||
1525 | "dpll_core_h14x2_ck", "dpll_per_h14x2_ck", "dpll_gpu_m2_ck", | 1526 | "dpll_core_h14x2_ck", "dpll_per_h14x2_ck", "dpll_gpu_m2_ck", |
1526 | }; | 1527 | }; |
1527 | 1528 | ||
1528 | DEFINE_CLK_MUX(gpu_core_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0, | 1529 | DEFINE_CLK_MUX(gpu_core_gclk_mux, gpu_core_gclk_mux_parents, NULL, |
1529 | DRA7XX_CM_GPU_GPU_CLKCTRL, DRA7XX_CLKSEL_CORE_CLK_SHIFT, | 1530 | CLK_SET_RATE_PARENT, DRA7XX_CM_GPU_GPU_CLKCTRL, |
1530 | DRA7XX_CLKSEL_CORE_CLK_WIDTH, 0x0, NULL); | 1531 | DRA7XX_CLKSEL_CORE_CLK_SHIFT, DRA7XX_CLKSEL_CORE_CLK_WIDTH, |
1532 | 0x0, NULL); | ||
1531 | 1533 | ||
1532 | DEFINE_CLK_MUX(gpu_hyd_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0, | 1534 | DEFINE_CLK_MUX(gpu_hyd_gclk_mux, gpu_core_gclk_mux_parents, NULL, |
1533 | DRA7XX_CM_GPU_GPU_CLKCTRL, DRA7XX_CLKSEL_HYD_CLK_SHIFT, | 1535 | CLK_SET_RATE_PARENT, DRA7XX_CM_GPU_GPU_CLKCTRL, |
1534 | DRA7XX_CLKSEL_HYD_CLK_WIDTH, 0x0, NULL); | 1536 | DRA7XX_CLKSEL_HYD_CLK_SHIFT, DRA7XX_CLKSEL_HYD_CLK_WIDTH, |
1537 | 0x0, NULL); | ||
1535 | 1538 | ||
1536 | static const char *ipu1_gfclk_mux_parents[] = { | 1539 | static const char *ipu1_gfclk_mux_parents[] = { |
1537 | "dpll_abe_m2x2_ck", "dpll_core_h22x2_ck", | 1540 | "dpll_abe_m2x2_ck", "dpll_core_h22x2_ck", |
@@ -1555,9 +1558,9 @@ DEFINE_CLK_DIVIDER_TABLE(l3instr_ts_gclk_div, "wkupaon_iclk_mux", | |||
1555 | 1558 | ||
1556 | static const char *mcasp1_ahclkr_mux_parents[] = { | 1559 | static const char *mcasp1_ahclkr_mux_parents[] = { |
1557 | "abe_24m_fclk", "abe_sys_clk_div", "func_24m_clk", | 1560 | "abe_24m_fclk", "abe_sys_clk_div", "func_24m_clk", |
1558 | "atlclkin3", "atl_clkin2", "atl_clkin1", | 1561 | "atl_clkin3_ck", "atl_clkin2_ck", "atl_clkin1_ck", |
1559 | "atl_clkin0", "sys_clkin2", "ref_clkin0", | 1562 | "atl_clkin0_ck", "sys_clkin2", "ref_clkin0_ck", |
1560 | "ref_clkin1", "ref_clkin2", "ref_clkin3", | 1563 | "ref_clkin1_ck", "ref_clkin2_ck", "ref_clkin3_ck", |
1561 | "mlb_clk", "mlbp_clk", | 1564 | "mlb_clk", "mlbp_clk", |
1562 | }; | 1565 | }; |
1563 | 1566 | ||
@@ -1692,8 +1695,8 @@ DEFINE_CLK_DIVIDER(qspi_gfclk_div, "qspi_gfclk_mux", &qspi_gfclk_mux, 0x0, | |||
1692 | 1695 | ||
1693 | static const char *timer10_gfclk_mux_parents[] = { | 1696 | static const char *timer10_gfclk_mux_parents[] = { |
1694 | "timer_sys_clk_div", "sys_32k_ck", "sys_clkin2", | 1697 | "timer_sys_clk_div", "sys_32k_ck", "sys_clkin2", |
1695 | "ref_clkin0", "ref_clkin1", "ref_clkin2", | 1698 | "ref_clkin0_ck", "ref_clkin1_ck", "ref_clkin2_ck", |
1696 | "ref_clkin3", "abe_giclk_div", "video1_div_clk", | 1699 | "ref_clkin3_ck", "abe_giclk_div", "video1_div_clk", |
1697 | "video2_div_clk", "hdmi_div_clk", | 1700 | "video2_div_clk", "hdmi_div_clk", |
1698 | }; | 1701 | }; |
1699 | 1702 | ||
@@ -1739,8 +1742,8 @@ DEFINE_CLK_MUX(timer4_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0, | |||
1739 | 1742 | ||
1740 | static const char *timer5_gfclk_mux_parents[] = { | 1743 | static const char *timer5_gfclk_mux_parents[] = { |
1741 | "timer_sys_clk_div", "sys_32k_ck", "sys_clkin2", | 1744 | "timer_sys_clk_div", "sys_32k_ck", "sys_clkin2", |
1742 | "ref_clkin0", "ref_clkin1", "ref_clkin2", | 1745 | "ref_clkin0_ck", "ref_clkin1_ck", "ref_clkin2_ck", |
1743 | "ref_clkin3", "abe_giclk_div", "video1_div_clk", | 1746 | "ref_clkin3_ck", "abe_giclk_div", "video1_div_clk", |
1744 | "video2_div_clk", "hdmi_div_clk", "clkoutmux0_clk_mux", | 1747 | "video2_div_clk", "hdmi_div_clk", "clkoutmux0_clk_mux", |
1745 | }; | 1748 | }; |
1746 | 1749 | ||
@@ -1828,7 +1831,7 @@ static struct omap_clk dra7xx_clks[] = { | |||
1828 | CLK(NULL, "atl_clkin0_ck", &atl_clkin0_ck, CK_7XX), | 1831 | CLK(NULL, "atl_clkin0_ck", &atl_clkin0_ck, CK_7XX), |
1829 | CLK(NULL, "atl_clkin1_ck", &atl_clkin1_ck, CK_7XX), | 1832 | CLK(NULL, "atl_clkin1_ck", &atl_clkin1_ck, CK_7XX), |
1830 | CLK(NULL, "atl_clkin2_ck", &atl_clkin2_ck, CK_7XX), | 1833 | CLK(NULL, "atl_clkin2_ck", &atl_clkin2_ck, CK_7XX), |
1831 | CLK(NULL, "atlclkin3_ck", &atlclkin3_ck, CK_7XX), | 1834 | CLK(NULL, "atl_clkin3_ck", &atl_clkin3_ck, CK_7XX), |
1832 | CLK(NULL, "hdmi_clkin_ck", &hdmi_clkin_ck, CK_7XX), | 1835 | CLK(NULL, "hdmi_clkin_ck", &hdmi_clkin_ck, CK_7XX), |
1833 | CLK(NULL, "mlb_clkin_ck", &mlb_clkin_ck, CK_7XX), | 1836 | CLK(NULL, "mlb_clkin_ck", &mlb_clkin_ck, CK_7XX), |
1834 | CLK(NULL, "mlbp_clkin_ck", &mlbp_clkin_ck, CK_7XX), | 1837 | CLK(NULL, "mlbp_clkin_ck", &mlbp_clkin_ck, CK_7XX), |
@@ -2123,7 +2126,9 @@ static struct reparent_init_clks reparent_clks[] = { | |||
2123 | 2126 | ||
2124 | static struct rate_init_clks rate_clks[] = { | 2127 | static struct rate_init_clks rate_clks[] = { |
2125 | { .name = "dpll_abe_ck", .rate = DRA7_DPLL_ABE_DEFFREQ }, | 2128 | { .name = "dpll_abe_ck", .rate = DRA7_DPLL_ABE_DEFFREQ }, |
2129 | { .name = "dpll_abe_m2x2_ck", .rate = DRA7_DPLL_ABE_DEFFREQ * 2 }, | ||
2126 | { .name = "dpll_gmac_ck", .rate = DRA7_DPLL_GMAC_DEFFREQ }, | 2130 | { .name = "dpll_gmac_ck", .rate = DRA7_DPLL_GMAC_DEFFREQ }, |
2131 | { .name = "dpll_usb_ck", .rate = DRA7_DPLL_USB_DEFFREQ }, | ||
2127 | }; | 2132 | }; |
2128 | 2133 | ||
2129 | int __init dra7xx_clk_init(void) | 2134 | int __init dra7xx_clk_init(void) |