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author | Jesse Barnes | 2013-02-02 04:10:24 -0600 |
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committer | Nikhil Devshatwar | 2013-05-17 04:51:32 -0500 |
commit | 2041b4bb1cfaa1a4565eb28a0148e6fa37493f3d (patch) | |
tree | 11300f85c3d52ce5682befcf27c68352c41ee115 | |
parent | 7264168c5068b875e54ca19f83a0e2d324152b46 (diff) | |
download | libdrm-2041b4bb1cfaa1a4565eb28a0148e6fa37493f3d.tar.gz libdrm-2041b4bb1cfaa1a4565eb28a0148e6fa37493f3d.tar.xz libdrm-2041b4bb1cfaa1a4565eb28a0148e6fa37493f3d.zip |
intel: add more VLV PCI IDs
-rw-r--r-- | intel/intel_chipset.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index a2eb8947..ebec2f8a 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h | |||
@@ -84,6 +84,9 @@ | |||
84 | #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A | 84 | #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A |
85 | 85 | ||
86 | #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* power on board */ | 86 | #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* power on board */ |
87 | #define PCI_CHIP_VALLEYVIEW_1 0x0f31 | ||
88 | #define PCI_CHIP_VALLEYVIEW_2 0x0f32 | ||
89 | #define PCI_CHIP_VALLEYVIEW_3 0x0f33 | ||
87 | 90 | ||
88 | #define IS_830(dev) (dev == 0x3577) | 91 | #define IS_830(dev) (dev == 0x3577) |
89 | #define IS_845(dev) (dev == 0x2562) | 92 | #define IS_845(dev) (dev == 0x2562) |
@@ -124,7 +127,10 @@ | |||
124 | 127 | ||
125 | #define IS_I965GM(dev) (dev == 0x2A02) | 128 | #define IS_I965GM(dev) (dev == 0x2A02) |
126 | 129 | ||
127 | #define IS_VALLEYVIEW(dev) (dev == 0xf30) | 130 | #define IS_VALLEYVIEW(dev) (((dev) == PCI_CHIP_VALLEYVIEW_PO) || \ |
131 | ((dev) == PCI_CHIP_VALLEYVIEW_1) || \ | ||
132 | ((dev) == PCI_CHIP_VALLEYVIEW_2) || \ | ||
133 | ((dev) == PCI_CHIP_VALLEYVIEW_3)) | ||
128 | 134 | ||
129 | #define IS_GEN4(dev) (dev == 0x2972 || \ | 135 | #define IS_GEN4(dev) (dev == 0x2972 || \ |
130 | dev == 0x2982 || \ | 136 | dev == 0x2982 || \ |