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author | Marek Olšák | 2012-07-29 08:20:15 -0500 |
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committer | Marek Olšák | 2012-08-09 09:37:20 -0500 |
commit | 23372955730048bbcddafc74365d911f9a74fb13 (patch) | |
tree | 9ebb2ef122e1a697612262627c649b2e5a9438ff | |
parent | ad66c17209811acdae21e44290a449523882a734 (diff) | |
download | libdrm-23372955730048bbcddafc74365d911f9a74fb13.tar.gz libdrm-23372955730048bbcddafc74365d911f9a74fb13.tar.xz libdrm-23372955730048bbcddafc74365d911f9a74fb13.zip |
radeon: optimize allocation for depth w/o stencil and stencil w/o depth on EG
If we don't need stencil, don't allocate it.
If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth.
v2: actually do it correctly
Reviewed-by: Christian König <christian.koenig@amd.com>
-rw-r--r-- | radeon/radeon_surface.c | 23 |
1 files changed, 8 insertions, 15 deletions
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 5800c334..874a0927 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c | |||
@@ -604,7 +604,11 @@ static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, | |||
604 | } | 604 | } |
605 | } | 605 | } |
606 | 606 | ||
607 | if (surf->flags & RADEON_SURF_SBUFFER) { | 607 | /* The depth and stencil buffers are in separate resources on evergreen. |
608 | * We allocate them in one buffer next to each other to simplify | ||
609 | * communication between the DDX and the Mesa driver. */ | ||
610 | if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) == | ||
611 | (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { | ||
608 | surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); | 612 | surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); |
609 | surf->bo_size = surf->stencil_offset + surf->bo_size / 4; | 613 | surf->bo_size = surf->stencil_offset + surf->bo_size / 4; |
610 | } | 614 | } |
@@ -656,7 +660,8 @@ static int eg_surface_init_2d(struct radeon_surface_manager *surf_man, | |||
656 | } | 660 | } |
657 | } | 661 | } |
658 | 662 | ||
659 | if (surf->flags & RADEON_SURF_SBUFFER) { | 663 | if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) == |
664 | (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { | ||
660 | surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); | 665 | surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); |
661 | surf->bo_size = surf->stencil_offset + surf->bo_size / 4; | 666 | surf->bo_size = surf->stencil_offset + surf->bo_size / 4; |
662 | } | 667 | } |
@@ -752,14 +757,7 @@ static int eg_surface_init(struct radeon_surface_manager *surf_man, | |||
752 | /* tiling mode */ | 757 | /* tiling mode */ |
753 | mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; | 758 | mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; |
754 | 759 | ||
755 | /* for some reason eg need to have room for stencil right after depth */ | 760 | if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { |
756 | if (surf->flags & RADEON_SURF_ZBUFFER) { | ||
757 | surf->flags |= RADEON_SURF_SBUFFER; | ||
758 | } | ||
759 | if (surf->flags & RADEON_SURF_SBUFFER) { | ||
760 | surf->flags |= RADEON_SURF_ZBUFFER; | ||
761 | } | ||
762 | if (surf->flags & RADEON_SURF_ZBUFFER) { | ||
763 | /* zbuffer only support 1D or 2D tiled surface */ | 761 | /* zbuffer only support 1D or 2D tiled surface */ |
764 | switch (mode) { | 762 | switch (mode) { |
765 | case RADEON_SURF_MODE_1D: | 763 | case RADEON_SURF_MODE_1D: |
@@ -828,11 +826,6 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, | |||
828 | /* tiling mode */ | 826 | /* tiling mode */ |
829 | mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; | 827 | mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; |
830 | 828 | ||
831 | /* for some reason eg need to have room for stencil right after depth */ | ||
832 | if (surf->flags & RADEON_SURF_ZBUFFER) { | ||
833 | surf->flags |= RADEON_SURF_SBUFFER; | ||
834 | } | ||
835 | |||
836 | /* set some default value to avoid sanity check choking on them */ | 829 | /* set some default value to avoid sanity check choking on them */ |
837 | surf->tile_split = 1024; | 830 | surf->tile_split = 1024; |
838 | surf->bankw = 1; | 831 | surf->bankw = 1; |