radeon: Sampling pitch for non-mipmaps seems padded to slice alignment on SI.

Another corner case that isn't well-explained yet.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

1 files changed, 8 insertions, 3 deletions

diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 98faa0b9..80b15056 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -974,10 +974,15 @@ static void si_surf_minify_linear_aligned(struct radeon_surface *surf,
         surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d;
     }
 
-    /* XXX: Second smallest level uses larger pitch, not sure of the real reason,
-     * my best guess so far: rows evenly distributed across slice
+    /* XXX: Texture sampling uses unexpectedly large pitches in some cases,
+     * these are just guesses for the rules behind those
      */
-    xalign = MAX2(xalign, slice_align / surf->bpe / surf->level[level].npix_y);
+    if (level == 0 && surf->last_level == 0)
+        /* Non-mipmap pitch padded to slice alignment */
+        xalign = MAX2(xalign, slice_align / surf->bpe);
+    else
+        /* Small rows evenly distributed across slice */
+        xalign = MAX2(xalign, slice_align / surf->bpe / surf->level[level].npix_y);
 
     surf->level[level].nblk_x  = ALIGN(surf->level[level].nblk_x, xalign);
     surf->level[level].nblk_y  = ALIGN(surf->level[level].nblk_y, yalign);