radeon: fix tile_split of 128-bit surface formats with 8x MSAA

The calculation led to the number 8192, which is too high.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 66c24449..eb587d24 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man,
         } else {
             /* tile split must be >= 256 for colorbuffer surfaces */
             surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
+            if (surf->tile_split > 4096)
+                surf->tile_split = 4096;
         }
     } else {
         /* set tile split to row size */