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authorMarek Olšák2012-10-15 19:08:02 -0500
committerMarek Olšák2012-10-26 13:00:59 -0500
commite32fff8e9ea8d522679eaab21a9555cab134fb36 (patch)
tree7d64d94e069c1283cc74d859218e9c9c583effbf
parentbc494b310d76f701798aee0f2b0b472d608cbfaf (diff)
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radeon: fix tile_split of 128-bit surface formats with 8x MSAA
The calculation led to the number 8192, which is too high. Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--radeon/radeon_surface.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 66c24449..eb587d24 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man,
939 } else { 939 } else {
940 /* tile split must be >= 256 for colorbuffer surfaces */ 940 /* tile split must be >= 256 for colorbuffer surfaces */
941 surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256); 941 surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
942 if (surf->tile_split > 4096)
943 surf->tile_split = 4096;
942 } 944 }
943 } else { 945 } else {
944 /* set tile split to row size */ 946 /* set tile split to row size */