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authorDaniel Vetter2012-04-02 06:08:09 -0500
committerDaniel Vetter2012-04-02 08:57:36 -0500
commit437042568301269bb78df2def61436c1cd97411c (patch)
tree6a550ae0a5dfe8e6dd55804e3d0241e3e73cee9e /intel
parente057a56448e2e785f74bc13dbd6ead8572ebed91 (diff)
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intel/decode: decode MI_WAIT_FOR_EVENT
... and add support to decode MI instructions with functions. Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'intel')
-rw-r--r--intel/intel_decode.c77
1 files changed, 75 insertions, 2 deletions
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index df9b704c..bf237061 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -139,6 +139,74 @@ instr_out(struct drm_intel_decode *ctx, unsigned int index,
139} 139}
140 140
141static int 141static int
142decode_MI_WAIT_FOR_EVENT(struct drm_intel_decode *ctx)
143{
144 const char *cc_wait;
145 int cc_shift = 0;
146 uint32_t data = ctx->data[0];
147
148 if (ctx->gen <= 5)
149 cc_shift = 9;
150 else
151 cc_shift = 16;
152
153 switch ((data >> cc_shift) & 0x1f) {
154 case 1:
155 cc_wait = ", cc wait 1";
156 break;
157 case 2:
158 cc_wait = ", cc wait 2";
159 break;
160 case 3:
161 cc_wait = ", cc wait 3";
162 break;
163 case 4:
164 cc_wait = ", cc wait 4";
165 break;
166 case 5:
167 cc_wait = ", cc wait 4";
168 break;
169 default:
170 cc_wait = "";
171 break;
172 }
173
174 if (ctx->gen <= 5) {
175 instr_out(ctx, 0, "MI_WAIT_FOR_EVENT%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
176 data & (1<<18)? ", pipe B start vblank wait": "",
177 data & (1<<17)? ", pipe A start vblank wait": "",
178 data & (1<<16)? ", overlay flip pending wait": "",
179 data & (1<<14)? ", pipe B hblank wait": "",
180 data & (1<<13)? ", pipe A hblank wait": "",
181 cc_wait,
182 data & (1<<8)? ", plane C pending flip wait": "",
183 data & (1<<7)? ", pipe B vblank wait": "",
184 data & (1<<6)? ", plane B pending flip wait": "",
185 data & (1<<5)? ", pipe B scan line wait": "",
186 data & (1<<4)? ", fbc idle wait": "",
187 data & (1<<3)? ", pipe A vblank wait": "",
188 data & (1<<2)? ", plane A pending flip wait": "",
189 data & (1<<1)? ", plane A scan line wait": "");
190 } else {
191 instr_out(ctx, 0, "MI_WAIT_FOR_EVENT%s%s%s%s%s%s%s%s%s%s%s%s\n",
192 data & (1<<20)? ", sprite C pending flip wait": "", /* ivb */
193 cc_wait,
194 data & (1<<13)? ", pipe B hblank wait": "",
195 data & (1<<11)? ", pipe B vblank wait": "",
196 data & (1<<10)? ", sprite B pending flip wait": "",
197 data & (1<<9)? ", plane B pending flip wait": "",
198 data & (1<<8)? ", plane B scan line wait": "",
199 data & (1<<5)? ", pipe A hblank wait": "",
200 data & (1<<3)? ", pipe A vblank wait": "",
201 data & (1<<2)? ", sprite A pending flip wait": "",
202 data & (1<<1)? ", plane A pending flip wait": "",
203 data & (1<<0)? ", plane A scan line wait": "");
204 }
205
206 return 1;
207}
208
209static int
142decode_mi(struct drm_intel_decode *ctx) 210decode_mi(struct drm_intel_decode *ctx)
143{ 211{
144 unsigned int opcode, len = -1; 212 unsigned int opcode, len = -1;
@@ -151,6 +219,7 @@ decode_mi(struct drm_intel_decode *ctx)
151 unsigned int min_len; 219 unsigned int min_len;
152 unsigned int max_len; 220 unsigned int max_len;
153 const char *name; 221 const char *name;
222 int (*func)(struct drm_intel_decode *ctx);
154 } opcodes_mi[] = { 223 } opcodes_mi[] = {
155 { 0x08, 0, 1, 1, "MI_ARB_ON_OFF" }, 224 { 0x08, 0, 1, 1, "MI_ARB_ON_OFF" },
156 { 0x0a, 0, 1, 1, "MI_BATCH_BUFFER_END" }, 225 { 0x0a, 0, 1, 1, "MI_BATCH_BUFFER_END" },
@@ -169,11 +238,11 @@ decode_mi(struct drm_intel_decode *ctx)
169 { 0x21, 0x3f, 3, 4, "MI_STORE_DATA_INDEX" }, 238 { 0x21, 0x3f, 3, 4, "MI_STORE_DATA_INDEX" },
170 { 0x24, 0x3f, 3, 3, "MI_STORE_REGISTER_MEM" }, 239 { 0x24, 0x3f, 3, 3, "MI_STORE_REGISTER_MEM" },
171 { 0x02, 0, 1, 1, "MI_USER_INTERRUPT" }, 240 { 0x02, 0, 1, 1, "MI_USER_INTERRUPT" },
172 { 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT" }, 241 { 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT", decode_MI_WAIT_FOR_EVENT },
173 { 0x16, 0x7f, 3, 3, "MI_SEMAPHORE_MBOX" }, 242 { 0x16, 0x7f, 3, 3, "MI_SEMAPHORE_MBOX" },
174 { 0x26, 0x1f, 3, 4, "MI_FLUSH_DW" }, 243 { 0x26, 0x1f, 3, 4, "MI_FLUSH_DW" },
175 { 0x0b, 0, 1, 1, "MI_SUSPEND_FLUSH"}, 244 { 0x0b, 0, 1, 1, "MI_SUSPEND_FLUSH"},
176 }; 245 }, *opcode_mi = NULL;
177 246
178 /* check instruction length */ 247 /* check instruction length */
179 for (opcode = 0; opcode < sizeof(opcodes_mi) / sizeof(opcodes_mi[0]); 248 for (opcode = 0; opcode < sizeof(opcodes_mi) / sizeof(opcodes_mi[0]);
@@ -192,10 +261,14 @@ decode_mi(struct drm_intel_decode *ctx)
192 opcodes_mi[opcode].max_len); 261 opcodes_mi[opcode].max_len);
193 } 262 }
194 } 263 }
264 opcode_mi = &opcodes_mi[opcode];
195 break; 265 break;
196 } 266 }
197 } 267 }
198 268
269 if (opcode_mi && opcode_mi->func)
270 return opcode_mi->func(ctx);
271
199 switch ((data[0] & 0x1f800000) >> 23) { 272 switch ((data[0] & 0x1f800000) >> 23) {
200 case 0x0a: 273 case 0x0a:
201 instr_out(ctx, 0, "MI_BATCH_BUFFER_END\n"); 274 instr_out(ctx, 0, "MI_BATCH_BUFFER_END\n");