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author | Vishal Mahaveer | 2017-03-21 14:26:42 -0500 |
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committer | Vishal Mahaveer | 2017-03-21 14:27:51 -0500 |
commit | 999672f9eab156409fd826c07ac5ccaf650e26e6 (patch) | |
tree | 59d9e81f9d9bd461b5f1a5c6ada606ee571030ba | |
parent | 850ffc07baa399451d16057285fcfa793ff8db2c (diff) | |
download | u-boot-999672f9eab156409fd826c07ac5ccaf650e26e6.tar.gz u-boot-999672f9eab156409fd826c07ac5ccaf650e26e6.tar.xz u-boot-999672f9eab156409fd826c07ac5ccaf650e26e6.zip |
dra72x/dra71x: update sdram config
Update latest values for J6 Eco / J6 Entry
Change-Id: I51f34fb0e3b677b47048b6a0aa4ce9789a58ecde
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
-rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 2 | ||||
-rw-r--r-- | board/ti/dra7xx/evm.c | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index ce5d01985b..a08c0bc578 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c | |||
@@ -720,7 +720,7 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = { | |||
720 | const struct ctrl_ioregs ioregs_dra72x_es2 = { | 720 | const struct ctrl_ioregs ioregs_dra72x_es2 = { |
721 | .ctrl_ddrch = 0x40404040, | 721 | .ctrl_ddrch = 0x40404040, |
722 | .ctrl_lpddr2ch = 0x40404040, | 722 | .ctrl_lpddr2ch = 0x40404040, |
723 | .ctrl_ddr3ch = 0x60606060, | 723 | .ctrl_ddr3ch = 0x80808080, |
724 | .ctrl_ddrio_0 = 0x00094A40, | 724 | .ctrl_ddrio_0 = 0x00094A40, |
725 | .ctrl_ddrio_1 = 0x00000000, | 725 | .ctrl_ddrio_1 = 0x00000000, |
726 | .ctrl_ddrio_2 = 0x00000000, | 726 | .ctrl_ddrio_2 = 0x00000000, |
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 1b8c898c19..f2e54276f6 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c | |||
@@ -136,12 +136,12 @@ static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { | |||
136 | }; | 136 | }; |
137 | 137 | ||
138 | const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = { | 138 | const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = { |
139 | .sdram_config_init = 0x61862BB2, | 139 | .sdram_config_init = 0x62822BB2, |
140 | .sdram_config = 0x61862BB2, | 140 | .sdram_config = 0x62822BB2, |
141 | .sdram_config2 = 0x00000000, | 141 | .sdram_config2 = 0x00000000, |
142 | .ref_ctrl = 0x0000514D, | 142 | .ref_ctrl = 0x0000514D, |
143 | .ref_ctrl_final = 0x0000144A, | 143 | .ref_ctrl_final = 0x0000144A, |
144 | .sdram_tim1 = 0xD1137824, | 144 | .sdram_tim1 = 0xD113783C, |
145 | .sdram_tim2 = 0x30B37FE3, | 145 | .sdram_tim2 = 0x30B37FE3, |
146 | .sdram_tim3 = 0x409F8AD8, | 146 | .sdram_tim3 = 0x409F8AD8, |
147 | .read_idle_ctrl = 0x00050000, | 147 | .read_idle_ctrl = 0x00050000, |