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authorKishon Vijay Abraham I2016-12-20 02:28:43 -0600
committerLokesh Vutla2016-12-20 07:19:03 -0600
commitaa5a3ec38c4151ad6528d786d70c26aa5eeddd33 (patch)
treebeaac4e22efc09e777077e5bd32466f85944cf93
parentfc013906ade6dd919beb8dc49f4df3b685e2821e (diff)
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drivers: mmc: omap_hsmmc: update phase delay value per latest TRM
While performing tuning, known data pattern is sent and received with different phase delay values and the centered DLL ratio of the largest passing window is selected as the final DLL ratio. However The 3/4th DLL ratio value of the largest passing window has better reliability and is more stable. So use the 3/4th DLL ratio value instead of the centered DLL ratio suggested in earlier TRMs. Newer TRMs have been updated to reflect this. 25.5.1.2.4 SDR104/HS200 DLL Tuning Procedure of TRM vAE (SPRUHI2AE–November 2012–Revised November 2016) Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Ravikumar Kattekola <rk@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
-rw-r--r--drivers/mmc/omap_hsmmc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index e3c64bb05b..2849519a58 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -633,7 +633,7 @@ static int omap_hsmmc_execute_tuning(struct mmc *mmc, uint opcode)
633 goto tuning_error; 633 goto tuning_error;
634 } 634 }
635 635
636 phase_delay = max_window + 4 * (max_len >> 1); 636 phase_delay = max_window + 4 * ((3 * max_len) >> 2);
637 omap_hsmmc_set_dll(mmc, phase_delay); 637 omap_hsmmc_set_dll(mmc, phase_delay);
638 638
639 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); 639 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);