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authorVenkateswara Rao Mandela2017-05-18 07:24:04 -0500
committerBuddy Liong2017-05-18 17:16:45 -0500
commitc2c3b96a1597fcda3c4459fccb76c447a308ee04 (patch)
tree1b0065335f110f6e27cb7f4fc807b9e199e51e89
parentc1296ad284c222e4f00a29d6bd93e5f547fabe98 (diff)
downloadu-boot-c2c3b96a1597fcda3c4459fccb76c447a308ee04.tar.gz
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Added tc35768 file
Change-Id: I563313ffa7c7d054254df7ddf44103d5c4985816
-rw-r--r--board/ti/dra7xx/Makefile2
-rw-r--r--board/ti/dra7xx/tc358768.c551
2 files changed, 552 insertions, 1 deletions
diff --git a/board/ti/dra7xx/Makefile b/board/ti/dra7xx/Makefile
index 0a3180603a..c26739af6f 100644
--- a/board/ti/dra7xx/Makefile
+++ b/board/ti/dra7xx/Makefile
@@ -7,4 +7,4 @@
7 7
8obj-y := evm.o 8obj-y := evm.o
9 9
10obj-$(CONFIG_LATE_ATTACH) += lateattach.o display.o 10obj-$(CONFIG_LATE_ATTACH) += lateattach.o display.o tc358768.o
diff --git a/board/ti/dra7xx/tc358768.c b/board/ti/dra7xx/tc358768.c
new file mode 100644
index 0000000000..d3584e49d6
--- /dev/null
+++ b/board/ti/dra7xx/tc358768.c
@@ -0,0 +1,551 @@
1/*
2 * Copyright (c) Texas Instruments Incorporated 2012-2015
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33
34/* ========================================================================== */
35/* Include Files */
36/* ========================================================================== */
37#include <common.h>
38#include <i2c.h>
39
40/* ========================================================================== */
41/* Macros & Typedefs */
42/* ========================================================================== */
43
44#define UInt8 uint8_t
45#define UInt16 uint16_t
46#define UInt32 uint32_t
47#define Int32 int32_t
48#define UInt64 uint64_t
49#define Bool uint32_t
50
51#define FALSE (0)
52#define TRUE (1)
53#define FVID2_SOK (0)
54#define BSP_SOK (0)
55#define BSP_EFAIL (1)
56
57#define BspOsal_sleep(a) mdelay((a))
58#define GT_assert(a, b) assert((b))
59#define GT_0trace(a, b, c) printf(c)
60int32_t Bsp_deviceRawWrite8(int32_t bdeviceI2cInstId,
61 int32_t slaveAddr,
62 uint8_t * data,
63 uint32_t len) {
64
65 i2c_write(slaveAddr, 0, 0, data, len);
66 return 0;
67}
68/* Register offsets */
69/* Global(16-bit addressable) */
70#define CHIPID ((UInt16)0x0000U)
71#define SYSCTL ((UInt16)0x0002U)
72#define CONFCTL ((UInt16)0x0004U)
73#define VSDLY ((UInt16)0x0006U)
74#define DATAFMT ((UInt16)0x0008U)
75#define GPIOEN ((UInt16)0x000EU)
76#define GPIODIR ((UInt16)0x0010U)
77#define GPIOIN ((UInt16)0x0012U)
78#define GPIOOUT ((UInt16)0x0014U)
79#define PLLCTL0 ((UInt16)0x0016U)
80#define PLLCTL1 ((UInt16)0x0018U)
81#define CMDBYTE ((UInt16)0x0022U)
82#define PP_MISC ((UInt16)0x0032U)
83#define DSITX_DT ((UInt16)0x0050U)
84#define FIFOSTATUS ((UInt16)0x00F8U)
85
86/* TX PHY(32-bit addressable) */
87#define CLW_DPHYCONTTX ((UInt16)0x0100U)
88#define D0W_DPHYCONTTX ((UInt16)0x0104U)
89#define D1W_DPHYCONTTX ((UInt16)0x0108U)
90#define D2W_DPHYCONTTX ((UInt16)0x010CU)
91#define D3W_DPHYCONTTX ((UInt16)0x0110U)
92#define CLW_CNTRL ((UInt16)0x0140U)
93#define D0W_CNTRL ((UInt16)0x0144U)
94#define D1W_CNTRL ((UInt16)0x0148U)
95#define D2W_CNTRL ((UInt16)0x014CU)
96#define D3W_CNTRL ((UInt16)0x0150U)
97
98/* TX PPI(32-bit addressable) */
99#define STARTCNTRL ((UInt16)0x0204U) /* DSITX Start Control Register */
100#define DSITXSTATUS ((UInt16)0x0208U) /* DSITX Status Register */
101#define LINEINITCNT ((UInt16)0x0210U) /* DSITX Line Init Control Register */
102#define LPTXTIMECNT ((UInt16)0x0214U) /* SYSLPTX Timing Generation Counter */
103#define TCLK_HEADERCNT ((UInt16)0x0218U) /* TCLK_ZERO and TCLK_PREPARE Counter */
104#define TCLK_TRAILCNT ((UInt16)0x021CU) /* TCLK_TRAIL Counter */
105#define THS_HEADERCNT ((UInt16)0x0220U) /* THS_ZERO and THS_PREPARE Counter */
106#define TWAKEUP ((UInt16)0x0224U) /* TWAKEUP Counter */
107#define TCLK_POSTCNT ((UInt16)0x0228U) /* TCLK_POST Counter */
108#define THS_TRAILCNT ((UInt16)0x022CU) /* THS_TRAIL Counter */
109#define HSTXVREGCNT ((UInt16)0x0230U) /* TX Voltage Regulator setup Wait Counter */
110#define HSTXVREGEN ((UInt16)0x0234U) /* Voltage regulator enable for
111 HSTX Data Lanes */
112#define TXOPTIONCNTRL ((UInt16)0x0238U) /* TX Option Control */
113#define BTACNTRL1 ((UInt16)0x023CU) /* BTA Control */
114
115/* TX CTRL(32-bit addressable) */
116#define DSI_CONTROL ((UInt16)0x040CU)
117#define DSI_STATUS ((UInt16)0x0410U)
118#define DSI_INT ((UInt16)0x0414U)
119#define DSI_INT_ENA ((UInt16)0x0418U)
120#define DSICMD_RXFIFO ((UInt16)0x0430U)
121#define DSI_ACKERR ((UInt16)0x0434U)
122#define DSI_ACKERR_INTENA ((UInt16)0x0438U)
123#define DSI_ACKERR_HALT ((UInt16)0x043CU)
124#define DSI_RXERR ((UInt16)0x0440U)
125#define DSI_RXERR_INTENA ((UInt16)0x0444U)
126#define DSI_RXERR_HALT ((UInt16)0x0448U)
127#define DSI_ERR ((UInt16)0x044CU)
128#define DSI_ERR_INTENA ((UInt16)0x0450U)
129#define DSI_ERR_HALT ((UInt16)0x0454U)
130#define DSI_CONFW ((UInt16)0x0500U)
131#define DSI_RESET ((UInt16)0x0504U)
132#define DSI_INT_CLR ((UInt16)0x050CU)
133#define DSI_START ((UInt16)0x0518U)
134
135/* DSITX CTRL(16-bit addressable) */
136#define DSICMD_TX ((UInt16)0x0600U)
137#define DSICMD_TYPE ((UInt16)0x0602U)
138#define DSICMD_WC ((UInt16)0x0604U)
139#define DSICMD_WD0 ((UInt16)0x0610U)
140#define DSICMD_WD1 ((UInt16)0x0612U)
141#define DSICMD_WD2 ((UInt16)0x0614U)
142#define DSICMD_WD3 ((UInt16)0x0616U)
143#define DSI_EVENT ((UInt16)0x0620U)
144#define DSI_VSW ((UInt16)0x0622U)
145#define DSI_VBPR ((UInt16)0x0624U)
146#define DSI_VACT ((UInt16)0x0626U)
147#define DSI_HSW ((UInt16)0x0628U)
148#define DSI_HBPR ((UInt16)0x062AU)
149#define DSI_HACT ((UInt16)0x062CU)
150
151/* Debug(16-bit addressable) */
152#define VBUFCTL ((UInt16)0x00E0U)
153#define DBG_WIDTH ((UInt16)0x00E2U)
154#define DBG_VBLANK ((UInt16)0x00E4U)
155#define DBG_DATA ((UInt16)0x00E8U)
156
157enum TRANSTYPE {
158 WR16=0,
159 WR32=1,
160 UPD=2,
161 SLEEP=3,
162};
163typedef struct tc3x_reg_write {
164 enum TRANSTYPE type;
165 uint32_t reg;
166 uint32_t val;
167 uint32_t update_val;
168};
169struct tc3x_reg_write trans_arr[] = {
170 {WR16 ,0x0002 ,0x00000001 ,0x0},
171 {WR16 ,0x0002 ,0x00000000 ,0x0},
172 {WR16 ,0x0016 ,0x000040e6 ,0x0},
173 {SLEEP},
174 {WR16 ,0x0018 ,0x00000203 ,0x0},
175 {SLEEP},
176 {WR16 ,0x0018 ,0x00000213 ,0x0},
177 {WR16 ,0x0006 ,0x00000001 ,0x0},
178 {WR16 ,0x0008 ,0x00000037 ,0x0},
179 {WR16 ,0x0050 ,0x0000003e ,0x0},
180 {WR32 ,0x0140 ,0x00000000 ,0x0},
181 {WR32 ,0x0144 ,0x00000000 ,0x0},
182 {WR32 ,0x0148 ,0x00000000 ,0x0},
183 {WR32 ,0x014c ,0x00000000 ,0x0},
184 {WR32 ,0x0150 ,0x00000000 ,0x0},
185 {WR32 ,0x0210 ,0x00002c88 ,0x0},
186 {WR32 ,0x0214 ,0x00000005 ,0x0},
187 {WR32 ,0x0218 ,0x00001f06 ,0x0},
188 {WR32 ,0x021c ,0x00000003 ,0x0},
189 {WR32 ,0x0220 ,0x00000606 ,0x0},
190 {WR32 ,0x0224 ,0x00004a88 ,0x0},
191 {WR32 ,0x0228 ,0x0000000b ,0x0},
192 {WR32 ,0x022c ,0x00000004 ,0x0},
193 {WR32 ,0x0234 ,0x0000001f ,0x0},
194 {WR32 ,0x0238 ,0x00000001 ,0x0},
195 {WR32 ,0x023c ,0x00050005 ,0x0},
196 {WR32 ,0x0204 ,0x00000001 ,0x0},
197 {WR16 ,0x0620 ,0x00000001 ,0x0},
198 {WR16 ,0x0622 ,0x00000012 ,0x0},
199 {WR16 ,0x0624 ,0x00000000 ,0x0},
200 {WR16 ,0x0626 ,0x000004b0 ,0x0},
201 {WR16 ,0x0628 ,0x00000090 ,0x0},
202 {WR16 ,0x062a ,0x00000000 ,0x0},
203 {WR16 ,0x062c ,0x00001680 ,0x0},
204 {WR32 ,0x0518 ,0x00000001 ,0x0},
205 {WR32 ,0x0500 ,0xa30000a7 ,0x0},
206 {WR32 ,0x0500 ,0xc3008000 ,0x0},
207 { UPD ,0x0032 ,0x00000c00 ,0x00000c00},
208 { UPD ,0x0004 ,0x00008004 ,0x00008044},
209 {WR16 ,0x0004 ,0x00008044 ,0x0},
210 {WR16 ,0x0602 ,0x00001032 ,0x0},
211 {WR16 ,0x0604 ,0x00000000 ,0x0},
212 {WR16 ,0x0610 ,0x00000000 ,0x0},
213 {WR16 ,0x0600 ,0x00000001 ,0x0},
214};
215
216/**
217 * \brief FVID2 Mode information structure.
218 */
219typedef struct
220{
221 UInt32 standard;
222 /**< [IN] Standard for which to get the info.
223 * For valid values see #Fvid2_Standard. */
224 UInt32 width;
225 /**< Active video frame width in pixels. */
226 UInt32 height;
227 /**< Active video frame height in lines. */
228 UInt32 scanFormat;
229 /**< Scan format of standard. For valid values see #Fvid2_ScanFormat. */
230 UInt32 pixelClock;
231 /**< Pixel clock of standard in KHz. This assumes 8-bit interface for
232 * NTSC/PAL/480I/576I resolutions and 16/24-bit interface for other
233 * resolutions including 480P and 576P. */
234 UInt32 fps;
235 /**< Frames per second. */
236 UInt32 hFrontPorch;
237 /**< Horizontal front porch. Same for both fields in case of interlaced
238 * display. */
239 UInt32 hBackPorch;
240 /**< Horizontal back porch. */
241 UInt32 hSyncLen;
242 /**< Horizontal sync length. Same for both fields in case of interlaced
243 * display. */
244 UInt32 vFrontPorch;
245 /**< Vertical front porch for each field or frame. */
246 UInt32 vBackPorch;
247 /**< Vertical back porch for each field or frame. */
248 UInt32 vSyncLen;
249 /**< Vertical sync length for each field. */
250 UInt32 reserved[4U];
251 /**< For future use. Not used currently. */
252} Fvid2_ModeInfo;
253/* ========================================================================== */
254/* Structure Declarations */
255/* ========================================================================== */
256
257typedef struct
258{
259 UInt32 fbd;
260 UInt32 prd;
261 UInt32 frs;
262 UInt32 bitclk;
263} BspDrv_lcdBridgeParams;
264
265/* ========================================================================== */
266/* Function Declarations */
267/* ========================================================================== */
268static Int32 LcdBridge_16bWrite(UInt32 deviceI2cInstId,
269 UInt32 slaveAddr,
270 UInt16 reg,
271 UInt16 data);
272static Int32 LcdBridge_32bWrite(UInt32 deviceI2cInstId,
273 UInt32 slaveAddr,
274 UInt16 reg,
275 UInt32 data);
276static Int32 Tc358778_setupPll(UInt32 deviceI2cInstId,
277 UInt32 slaveAddr,
278 BspDrv_lcdBridgeParams *bridgeParams,
279 const Fvid2_ModeInfo *mInfo);
280static void Tc358778_getLcdTiming (Fvid2_ModeInfo *mInfo);
281
282/* ========================================================================== */
283/* Global Variables */
284/* ========================================================================== */
285
286/* None */
287
288/* ========================================================================== */
289/* Function Definitions */
290/* ========================================================================== */
291
292static Int32 LcdBridge_16bWrite(UInt32 deviceI2cInstId,
293 UInt32 slaveAddr,
294 UInt16 reg,
295 UInt16 data)
296{
297 UInt8 i2cdata[4];
298 Int32 retVal = FVID2_SOK;
299
300 i2cdata[0] = (UInt8)((reg & (UInt16)0xFF00U) >> 8); /*Register[15:8] */
301 i2cdata[1] = (UInt8)(reg & (UInt16)0x00FFU); /*Register[7:0]*/
302 i2cdata[2] = (UInt8)((data & (UInt16)0xFF00U) >> 8); /*data[15:8]*/
303 i2cdata[3] = (UInt8)(data & (UInt16)0x00FFU); /*data[7:0]*/
304 printf("WR16 %04x %08x\n", reg, data);
305 retVal = Bsp_deviceRawWrite8(deviceI2cInstId,
306 slaveAddr,
307 i2cdata,
308 (UInt32)4U);
309 BspOsal_sleep(2U);
310 return retVal;
311}
312
313static Int32 LcdBridge_32bWrite(UInt32 deviceI2cInstId,
314 UInt32 slaveAddr,
315 UInt16 reg,
316 UInt32 data)
317{
318 UInt8 i2cdata[6];
319 Int32 retVal = FVID2_SOK;
320
321 i2cdata[0] = (UInt8)((reg & (UInt16)0xFF00U) >> 8); /*Register[15:8] */
322 i2cdata[1] = (UInt8)(reg & (UInt16)0x00FFU); /*Register[7:0]*/
323
324 #if 0
325 i2cdata[2] = (UInt8)((data & (UInt32)0xFF00U) >> 8); /*data[15:8]*/
326 i2cdata[3] = (UInt8)(data & (UInt32)0x00FFU); /*data[7:0]*/
327 i2cdata[4] = (UInt8)((data & (UInt32)0xFF000000U) >> 24); /*data[31:24]*/
328 i2cdata[5] = (UInt8)((data & (UInt32)0x00FF0000U) >> 16); /*data[23:16]*/
329 printf("WR32 %04x %08x\n", reg, data);
330 retVal = Bsp_deviceRawWrite8(deviceI2cInstId,
331 slaveAddr,
332 i2cdata,
333 (UInt32)6U);
334 BspOsal_sleep(2U);
335 #else
336 LcdBridge_16bWrite(deviceI2cInstId,
337 slaveAddr,
338 reg,
339 (data&0xFFFF));
340 LcdBridge_16bWrite(deviceI2cInstId,
341 slaveAddr,
342 reg+2,
343 (data&0xFFFF0000)>>16);
344 #endif
345 return retVal;
346}
347
348static void Tc358778_getLcdTiming (Fvid2_ModeInfo *mInfo)
349{
350 GT_assert(BspAppTrace, (NULL != mInfo));
351#if defined (BSP_LCDCTRL_IDK_LCD_32FPS)
352 mInfo->width = 1920;
353 mInfo->height = 1200;
354 mInfo->pixelClock = 78000;
355 mInfo->hFrontPorch = 112;
356 mInfo->hBackPorch = 32;
357 mInfo->hSyncLen = 16;
358 mInfo->vFrontPorch = 17;
359 mInfo->vBackPorch = 16;
360 mInfo->vSyncLen = 2;
361#else
362 mInfo->width = 1920;
363 mInfo->height = 1200;
364 mInfo->pixelClock = 147000;
365 mInfo->hFrontPorch = 32;
366 mInfo->hBackPorch = 32;
367 mInfo->hSyncLen = 16;
368 mInfo->vFrontPorch = 7;
369 mInfo->vBackPorch = 16;
370 mInfo->vSyncLen = 2;
371#endif
372}
373static Int32 Tc358778_setupPll(UInt32 deviceI2cInstId,
374 UInt32 slaveAddr,
375 BspDrv_lcdBridgeParams *bridgeParams,
376 const Fvid2_ModeInfo *mInfo)
377{
378 Int32 retVal = BSP_SOK;
379 UInt32 fbd = 230, prd = 4, frs = 0;
380 UInt32 pll = 0;
381 Bool found = FALSE;
382
383 bridgeParams->fbd = fbd;
384 bridgeParams->prd = prd;
385 bridgeParams->frs = frs;
386 bridgeParams->bitclk = pll / 2U;
387
388 if (retVal == BSP_SOK)
389 {
390 UInt32 tempVal;
391 /* Program DSI Tx PLL */
392#if defined (BSP_LCDCTRL_IDK_LCD_32FPS)
393 tempVal = (prd << 12) | fbd;
394 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, PLLCTL0,
395 (UInt16) tempVal);
396#else
397 /* For 60 FPS configuration calculated value doesnot work.
398 * Hardcoded as of now. */
399 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, PLLCTL0,
400 (UInt16) 0x40e6);
401#endif
402 tempVal = (frs << 10) | ((UInt32) 0x2 << 8) | ((UInt32) 0 << 4) |
403 ((UInt32) 1 << 1) | ((UInt32) 1 << 0);
404 /* PRD[15:12], FBD[8:0] */
405 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, PLLCTL1,
406 (UInt16) tempVal);
407 /* FRS[11:10],LBWS[9:8], Clock Enable[4], ResetB[1], PLL En[0] */
408 BspOsal_sleep(10U);
409 tempVal = (frs << 10) | ((UInt32) 0x2 << 8) | ((UInt32) 1 << 4) |
410 ((UInt32) 1 << 1) | ((UInt32) 1 << 0);
411 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, PLLCTL1,
412 (UInt16) tempVal);
413 /* FRS[11:10],LBWS[9:8], Clock Enable[4], ResetB[1], PLL En[0] */
414 }
415 return retVal;
416}
417
418void Tc358778_lcdBridgeInit2(UInt32 deviceI2cInstId, UInt32 slaveAddr) {
419 uint32_t i = 0;
420
421 for(i = 0; i < sizeof(trans_arr)/sizeof(struct tc3x_reg_write); i++) {
422 struct tc3x_reg_write *ptr = &trans_arr[i];
423 switch (ptr->type) {
424 case WR16:
425 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr,
426 ptr->reg,
427 ptr->val);
428 break;
429 case WR32:
430 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr,
431 ptr->reg,
432 ptr->val);
433 break;
434 case UPD:
435 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr,
436 ptr->reg,
437 ptr->update_val);
438 break;
439 case SLEEP:
440 mdelay(10);
441 break;
442 }
443 mdelay(10);
444 }
445}
446void Tc358778_lcdBridgeInit(UInt32 deviceI2cInstId, UInt32 slaveAddr)
447{
448 BspDrv_lcdBridgeParams bridgeParams = {0};
449 Fvid2_ModeInfo mInfo = {0};
450 Tc358778_getLcdTiming(&mInfo);
451 /* user defined */
452 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, CONFCTL, (UInt16)0x0004U);
453 /* Disable Parallel Input */
454 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, SYSCTL, (UInt16)0x0001U);
455 /* Assert Reset [0]=1 */
456 BspOsal_sleep(10U);
457 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, SYSCTL, (UInt16)0x0000U);
458 /* Release Reset, Exit Sleep */
459
460 /* Program DSI Tx PLL */
461 Tc358778_setupPll(deviceI2cInstId, slaveAddr, &bridgeParams, &mInfo);
462
463 /* DPI Input Control */
464 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, VSDLY, (UInt16)0x00D0U);
465 /* V/Hsync Delay */
466 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, DATAFMT, (UInt16)0x0037U);
467 /* DataFmt[7:4]=3, Loose Pk=0, Rsvrd=1, DSITx_En=1, Rsvrd=1 */
468 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, DSITX_DT, (UInt16)0x003eU);
469 /* DSITx DataID, RGB888 0x3E */
470
471 /* DSI Tx PHY */
472 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, CLW_CNTRL, (UInt32)0x00000000U);
473 /* Disable DSI Clock Lane */
474 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, D0W_CNTRL, (UInt32)0x00000000U);
475 /* Disable DSI Data Lane0 */
476 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, D1W_CNTRL, (UInt32)0x00000000U);
477 /* Disable DSI Data Lane1 */
478 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, D2W_CNTRL, (UInt32)0x00000000U);
479 /* Disable DSI Data Lane2 */
480 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, D3W_CNTRL, (UInt32)0x00000000U);
481 /* Disable DSI Data Lane3 */
482
483 /* DSI Tx PPI */
484 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, LINEINITCNT, (UInt32)0x00002C88U);
485 /* LP11 = 100 us for D-PHY Rx Init */
486 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, LPTXTIMECNT, (UInt32)0x00000005U);
487 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, TCLK_HEADERCNT, (UInt32)0x00001F06U);
488 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, TCLK_TRAILCNT, (UInt32)0x00000003U);
489 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, THS_HEADERCNT, (UInt32)0x00000606U);
490 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, TWAKEUP, (UInt32)0x00004A88U);
491 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, TCLK_POSTCNT, (UInt32)0x0000000BU);
492 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, THS_TRAILCNT, (UInt32)0x00000004U);
493 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, HSTXVREGEN, (UInt32)0x0000001FU);
494 /* Enable Voltage Regulator for CSI (4 Data + Clk) Lanes */
495 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, TXOPTIONCNTRL, (UInt32)0x00000001U);
496 /* [0] = 1, Continuous Clock */
497 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, BTACNTRL1, (UInt32)0x00050005U);
498 /* Disable DSI Data Lane3 */
499 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, STARTCNTRL, (UInt32)0x00000001U);
500 /* Start PPI */
501
502 /* DSI Tx Timing Control */
503 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, DSI_EVENT, (UInt16)0x0001U);
504 /* Set Event Mode */
505 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, DSI_VSW,
506 (UInt16)(mInfo.vBackPorch + mInfo.vSyncLen));
507 /* Set This register to: Vertical Sync Width + VBP */
508 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, DSI_VBPR, (UInt16)0x0U);
509 /* VPBR not used in event mode */
510 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, DSI_VACT,
511 (UInt16) mInfo.height);
512 /* Set Vertical Active line */
513
514 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, DSI_HSW,
515 (((mInfo.hBackPorch + mInfo.hSyncLen) * (bridgeParams.bitclk / 4U) *
516 4U) / mInfo.pixelClock));
517 /* (HSW+HBPR)/PClkFreq*ByteClkFreq*#Lanes */
518 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, DSI_HBPR, (UInt16)0x0U);
519 /* hbp (not used in event mode) */
520 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, DSI_HACT,
521 (UInt16)(mInfo.width * 3));
522 /* Set Horizontal Active line byte count */
523
524 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, DSI_START, (UInt32)0x00000001U);
525 /* Start DSI Tx */
526 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, DSI_CONFW, (UInt32)0xA30000A7U);
527 LcdBridge_32bWrite(deviceI2cInstId, slaveAddr, DSI_CONFW, (UInt32)0xC3008001U);
528
529 /* clear FrmStop and RstPtr */
530 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, PP_MISC, (UInt16)0x0U);
531 /* DSI Panel Programming */
532 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, CONFCTL, (UInt16)0x0044U);
533 /* Set Event Mode */
534
535 return;
536}
537
538void Tc358778_lcdBridgeDeinit(UInt32 deviceI2cInstId, UInt32 slaveAddr)
539{
540 /* set FrmStop */
541 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, PP_MISC, (UInt16)0x1000U);
542
543 /* wait at least for one frame */
544 BspOsal_sleep(50U);
545
546 /* clear PP_en */
547 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, CONFCTL, (UInt16)0x0004U);
548
549 /* set RstPtr */
550 LcdBridge_16bWrite(deviceI2cInstId, slaveAddr, PP_MISC, (UInt16)0xC000U);
551}