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author | Subash Lakkimsetti | 2017-01-17 14:48:29 -0600 |
---|---|---|
committer | Buddy Liong | 2017-02-08 15:45:06 -0600 |
commit | c98472cd4bf87b94f8e578c964bc176bf878ebb9 (patch) | |
tree | f021a419a06cb11cf2de02046787e7364610d2f5 | |
parent | 02a5e345c9cdf4ceca6698013013a00dcc0550a7 (diff) | |
download | u-boot-c98472cd4bf87b94f8e578c964bc176bf878ebb9.tar.gz u-boot-c98472cd4bf87b94f8e578c964bc176bf878ebb9.tar.xz u-boot-c98472cd4bf87b94f8e578c964bc176bf878ebb9.zip |
DRA7XX - Late Attach - Use reserved memory for IOUMM tablervc-3.0
IOMMU Table memory for remote cores is carved out. With page table
allocation from end of CMA-POOL from u-boot, kernel treats this region
as free memory. This causes an MMU faults on remote cores in low memory
situations.
IOMMU table region 0xbfc00000 - 0xbfd00000 has to carved out with
reserved_mem in kernel.
Kernel commit details: 41a8818d9675804bd3054395ca893c99bfce88be
http://review.omapzoom.org/#/c/38093/
Change-Id: I09ec250f3a8ec4a934ad73437981c5dea8930a34
Signed-off-by: Subash Lakkimsetti <x0091084@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
-rw-r--r-- | board/ti/dra7xx/lateattach.c | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/board/ti/dra7xx/lateattach.c b/board/ti/dra7xx/lateattach.c index 6b368f00dd..95687668fc 100644 --- a/board/ti/dra7xx/lateattach.c +++ b/board/ti/dra7xx/lateattach.c | |||
@@ -164,6 +164,11 @@ | |||
164 | 164 | ||
165 | #define VAYU_ES10_CHIPSETID 0x5436 | 165 | #define VAYU_ES10_CHIPSETID 0x5436 |
166 | 166 | ||
167 | #define DRA7_PGTBL_BASE_IPU1 0xbfc00000 | ||
168 | #define DRA7_PGTBL_BASE_IPU2 0xbfc08000 | ||
169 | #define DRA7_PGTBL_BASE_DSP1 0xbfc10000 | ||
170 | #define DRA7_PGTBL_BASE_DSP2 0xbfc18000 | ||
171 | |||
167 | /* | 172 | /* |
168 | * The page table (32 KB) is placed at the end of the CMA reserved area. | 173 | * The page table (32 KB) is placed at the end of the CMA reserved area. |
169 | * It's possible that this location is needed by the firmware (in which | 174 | * It's possible that this location is needed by the firmware (in which |
@@ -1202,7 +1207,7 @@ struct rproc ipu1_config = { | |||
1202 | .num_iommus = 1, | 1207 | .num_iommus = 1, |
1203 | .cma_base = DRA7_RPROC_CMA_BASE_IPU1, | 1208 | .cma_base = DRA7_RPROC_CMA_BASE_IPU1, |
1204 | .cma_size = DRA7_RPROC_CMA_SIZE_IPU1, | 1209 | .cma_size = DRA7_RPROC_CMA_SIZE_IPU1, |
1205 | .page_table_addr = 0, | 1210 | .page_table_addr = DRA7_PGTBL_BASE_IPU1, |
1206 | .mmu_base_addr = {0x58882000, 0}, | 1211 | .mmu_base_addr = {0x58882000, 0}, |
1207 | .load_addr = IPU1_LOAD_ADDR, | 1212 | .load_addr = IPU1_LOAD_ADDR, |
1208 | .core_name = "IPU1", | 1213 | .core_name = "IPU1", |
@@ -1223,7 +1228,7 @@ struct rproc ipu2_config = { | |||
1223 | .num_iommus = 1, | 1228 | .num_iommus = 1, |
1224 | .cma_base = DRA7_RPROC_CMA_BASE_IPU2, | 1229 | .cma_base = DRA7_RPROC_CMA_BASE_IPU2, |
1225 | .cma_size = DRA7_RPROC_CMA_SIZE_IPU2, | 1230 | .cma_size = DRA7_RPROC_CMA_SIZE_IPU2, |
1226 | .page_table_addr = 0, | 1231 | .page_table_addr = DRA7_PGTBL_BASE_IPU2, |
1227 | .mmu_base_addr = {0x55082000, 0}, | 1232 | .mmu_base_addr = {0x55082000, 0}, |
1228 | .load_addr = IPU2_LOAD_ADDR, | 1233 | .load_addr = IPU2_LOAD_ADDR, |
1229 | .core_name = "IPU2", | 1234 | .core_name = "IPU2", |
@@ -1244,7 +1249,7 @@ struct rproc dsp1_config = { | |||
1244 | .num_iommus = 2, | 1249 | .num_iommus = 2, |
1245 | .cma_base = DRA7_RPROC_CMA_BASE_DSP1, | 1250 | .cma_base = DRA7_RPROC_CMA_BASE_DSP1, |
1246 | .cma_size = DRA7_RPROC_CMA_SIZE_DSP1, | 1251 | .cma_size = DRA7_RPROC_CMA_SIZE_DSP1, |
1247 | .page_table_addr = 0, | 1252 | .page_table_addr = DRA7_PGTBL_BASE_DSP1, |
1248 | .mmu_base_addr = {0x40D01000, 0x40D02000}, | 1253 | .mmu_base_addr = {0x40D01000, 0x40D02000}, |
1249 | .load_addr = DSP1_LOAD_ADDR, | 1254 | .load_addr = DSP1_LOAD_ADDR, |
1250 | .core_name = "DSP1", | 1255 | .core_name = "DSP1", |
@@ -1265,7 +1270,7 @@ struct rproc dsp2_config = { | |||
1265 | .num_iommus = 2, | 1270 | .num_iommus = 2, |
1266 | .cma_base = DRA7_RPROC_CMA_BASE_DSP2, | 1271 | .cma_base = DRA7_RPROC_CMA_BASE_DSP2, |
1267 | .cma_size = DRA7_RPROC_CMA_SIZE_DSP2, | 1272 | .cma_size = DRA7_RPROC_CMA_SIZE_DSP2, |
1268 | .page_table_addr = 0, | 1273 | .page_table_addr = DRA7_PGTBL_BASE_DSP2, |
1269 | .mmu_base_addr = {0x41501000, 0x41502000}, | 1274 | .mmu_base_addr = {0x41501000, 0x41502000}, |
1270 | .load_addr = DSP2_LOAD_ADDR, | 1275 | .load_addr = DSP2_LOAD_ADDR, |
1271 | .core_name = "DSP2", | 1276 | .core_name = "DSP2", |
@@ -1317,10 +1322,6 @@ u32 spl_boot_core(u32 core_id) | |||
1317 | if (cfg->start_clocks) | 1322 | if (cfg->start_clocks) |
1318 | cfg->start_clocks(core_id, cfg); | 1323 | cfg->start_clocks(core_id, cfg); |
1319 | 1324 | ||
1320 | /* Calculate the page table address */ | ||
1321 | cfg->page_table_addr = | ||
1322 | cfg->cma_base + cfg->cma_size - (PAGE_TABLE_SIZE); | ||
1323 | |||
1324 | debug("Configuring IOMMU\n"); | 1325 | debug("Configuring IOMMU\n"); |
1325 | 1326 | ||
1326 | /* Configure the MMU */ | 1327 | /* Configure the MMU */ |