diff options
author | Praneeth Bajjuri | 2017-08-28 01:07:30 -0500 |
---|---|---|
committer | Praneeth Bajjuri | 2017-08-28 01:07:30 -0500 |
commit | 5802ae3ccc85b19f98fdfbd6e9174a1875f351f9 (patch) | |
tree | 86321e1420323bd48652c8abcdb1ea2e03cd4fc2 | |
parent | ff48c7935985248c67743425c0ce58167f81d9a2 (diff) | |
parent | 299ebd66e11c2481a29ddcbfe65e196f6c9e0b41 (diff) | |
download | u-boot-5802ae3ccc85b19f98fdfbd6e9174a1875f351f9.tar.gz u-boot-5802ae3ccc85b19f98fdfbd6e9174a1875f351f9.tar.xz u-boot-5802ae3ccc85b19f98fdfbd6e9174a1875f351f9.zip |
Merge branch 'ti-u-boot-2016.05' of git://git.ti.com/ti-u-boot/ti-u-boot into p-ti-u-boot-2016.05
* 'ti-u-boot-2016.05' of git://git.ti.com/ti-u-boot/ti-u-boot:
arm: omap: enable high speed mode support in SPL for the eMMC on DRA76x
ARM: dts: dra76-evm: add higher speed MMC/SD modes
ARM: dts: dra76-evm: shift to using common IOdelay data
ARM: dts: dra76x: create a common file with MMC/SD IOdelay data
ARM: DRA72x: Add support for detection of DRA71x SR 2.1
Change-Id: I6e100695a70d55683a66bf8c8430e5245831e6dc
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
-rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap5/hwinit.c | 3 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap5/sdram.c | 2 | ||||
-rw-r--r-- | arch/arm/dts/dra76-evm.dts | 51 | ||||
-rw-r--r-- | arch/arm/dts/dra76x-mmc-iodelay.dtsi | 244 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-omap5/omap.h | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/omap_common.h | 1 | ||||
-rw-r--r-- | board/ti/dra7xx/evm.c | 13 | ||||
-rw-r--r-- | board/ti/dra7xx/mux_data.h | 29 |
9 files changed, 304 insertions, 42 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index ed016cb7de..ae25a74638 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c | |||
@@ -753,6 +753,7 @@ void __weak hw_data_init(void) | |||
753 | 753 | ||
754 | case DRA722_ES1_0: | 754 | case DRA722_ES1_0: |
755 | case DRA722_ES2_0: | 755 | case DRA722_ES2_0: |
756 | case DRA722_ES2_1: | ||
756 | *prcm = &dra7xx_prcm; | 757 | *prcm = &dra7xx_prcm; |
757 | *dplls_data = &dra72x_dplls; | 758 | *dplls_data = &dra72x_dplls; |
758 | *ctrl = &dra7xx_ctrl; | 759 | *ctrl = &dra7xx_ctrl; |
@@ -788,6 +789,7 @@ void get_ioregs(const struct ctrl_ioregs **regs) | |||
788 | *regs = &ioregs_dra72x_es1; | 789 | *regs = &ioregs_dra72x_es1; |
789 | break; | 790 | break; |
790 | case DRA722_ES2_0: | 791 | case DRA722_ES2_0: |
792 | case DRA722_ES2_1: | ||
791 | *regs = &ioregs_dra72x_es2; | 793 | *regs = &ioregs_dra72x_es2; |
792 | break; | 794 | break; |
793 | 795 | ||
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 434d304686..03e50ba891 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c | |||
@@ -380,6 +380,9 @@ void init_omap_revision(void) | |||
380 | case DRA722_CONTROL_ID_CODE_ES2_0: | 380 | case DRA722_CONTROL_ID_CODE_ES2_0: |
381 | *omap_si_rev = DRA722_ES2_0; | 381 | *omap_si_rev = DRA722_ES2_0; |
382 | break; | 382 | break; |
383 | case DRA722_CONTROL_ID_CODE_ES2_1: | ||
384 | *omap_si_rev = DRA722_ES2_1; | ||
385 | break; | ||
383 | default: | 386 | default: |
384 | *omap_si_rev = OMAP5430_SILICON_ID_INVALID; | 387 | *omap_si_rev = OMAP5430_SILICON_ID_INVALID; |
385 | } | 388 | } |
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 67ff63b9f6..8fb962e39d 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c | |||
@@ -482,6 +482,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, | |||
482 | break; | 482 | break; |
483 | case DRA762_ES1_0: | 483 | case DRA762_ES1_0: |
484 | case DRA722_ES2_0: | 484 | case DRA722_ES2_0: |
485 | case DRA722_ES2_1: | ||
485 | *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; | 486 | *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; |
486 | *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); | 487 | *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); |
487 | break; | 488 | break; |
@@ -716,6 +717,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations) | |||
716 | case DRA752_ES2_0: | 717 | case DRA752_ES2_0: |
717 | case DRA722_ES1_0: | 718 | case DRA722_ES1_0: |
718 | case DRA722_ES2_0: | 719 | case DRA722_ES2_0: |
720 | case DRA722_ES2_1: | ||
719 | bug_00339_regs_ptr = dra_bug_00339_regs; | 721 | bug_00339_regs_ptr = dra_bug_00339_regs; |
720 | *iterations = sizeof(dra_bug_00339_regs)/ | 722 | *iterations = sizeof(dra_bug_00339_regs)/ |
721 | sizeof(dra_bug_00339_regs[0]); | 723 | sizeof(dra_bug_00339_regs[0]); |
diff --git a/arch/arm/dts/dra76-evm.dts b/arch/arm/dts/dra76-evm.dts index 5b14dbf72a..1a149fa5fe 100644 --- a/arch/arm/dts/dra76-evm.dts +++ b/arch/arm/dts/dra76-evm.dts | |||
@@ -9,6 +9,7 @@ | |||
9 | 9 | ||
10 | #include "dra76x.dtsi" | 10 | #include "dra76x.dtsi" |
11 | #include "dra7-evm-common.dtsi" | 11 | #include "dra7-evm-common.dtsi" |
12 | #include "dra76x-mmc-iodelay.dtsi" | ||
12 | #include <dt-bindings/net/ti-dp83867.h> | 13 | #include <dt-bindings/net/ti-dp83867.h> |
13 | 14 | ||
14 | / { | 15 | / { |
@@ -100,46 +101,6 @@ | |||
100 | }; | 101 | }; |
101 | }; | 102 | }; |
102 | 103 | ||
103 | &dra7_pmx_core { | ||
104 | mmc1_pins_default: mmc1_pins_default { | ||
105 | pinctrl-single,pins = < | ||
106 | 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ | ||
107 | 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ | ||
108 | 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
109 | 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
110 | 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
111 | 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
112 | 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
113 | >; | ||
114 | }; | ||
115 | |||
116 | mmc2_pins_default: mmc2_pins_default { | ||
117 | pinctrl-single,pins = < | ||
118 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | ||
119 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | ||
120 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | ||
121 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | ||
122 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | ||
123 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | ||
124 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | ||
125 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | ||
126 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | ||
127 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | ||
128 | >; | ||
129 | }; | ||
130 | |||
131 | mmc4_pins_default: mmc4_pins_default { | ||
132 | pinctrl-single,pins = < | ||
133 | 0x3e (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ | ||
134 | 0x3e (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ | ||
135 | 0x3f (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ | ||
136 | 0x3f (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ | ||
137 | 0x3f (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ | ||
138 | 0x3f (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ | ||
139 | >; | ||
140 | }; | ||
141 | }; | ||
142 | |||
143 | &i2c1 { | 104 | &i2c1 { |
144 | status = "okay"; | 105 | status = "okay"; |
145 | clock-frequency = <400000>; | 106 | clock-frequency = <400000>; |
@@ -352,16 +313,22 @@ | |||
352 | * is always hardwired. | 313 | * is always hardwired. |
353 | */ | 314 | */ |
354 | cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; | 315 | cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; |
355 | pinctrl-names = "default"; | 316 | max-frequency = <192000000>; |
317 | pinctrl-names = "default", "hs"; | ||
356 | pinctrl-0 = <&mmc1_pins_default>; | 318 | pinctrl-0 = <&mmc1_pins_default>; |
319 | pinctrl-1 = <&mmc1_pins_hs>; | ||
357 | }; | 320 | }; |
358 | 321 | ||
359 | &mmc2 { | 322 | &mmc2 { |
360 | status = "okay"; | 323 | status = "okay"; |
361 | vmmc-supply = <&vio_1v8>; | 324 | vmmc-supply = <&vio_1v8>; |
362 | bus-width = <8>; | 325 | bus-width = <8>; |
363 | pinctrl-names = "default"; | 326 | max-frequency = <192000000>; |
327 | pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; | ||
364 | pinctrl-0 = <&mmc2_pins_default>; | 328 | pinctrl-0 = <&mmc2_pins_default>; |
329 | pinctrl-1 = <&mmc2_pins_hs>; | ||
330 | pinctrl-2 = <&mmc2_pins_ddr>; | ||
331 | pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>; | ||
365 | }; | 332 | }; |
366 | 333 | ||
367 | /* No RTC on this device */ | 334 | /* No RTC on this device */ |
diff --git a/arch/arm/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/dts/dra76x-mmc-iodelay.dtsi new file mode 100644 index 0000000000..ff578843eb --- /dev/null +++ b/arch/arm/dts/dra76x-mmc-iodelay.dtsi | |||
@@ -0,0 +1,244 @@ | |||
1 | /* | ||
2 | * MMC IOdelay values for TI's DRA76x and AM576x SoCs. | ||
3 | * | ||
4 | * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License as | ||
8 | * published by the Free Software Foundation version 2. | ||
9 | * | ||
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
11 | * kind, whether express or implied; without even the implied warranty | ||
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | |||
16 | /* | ||
17 | * Rules for modifying this file: | ||
18 | * a) Update of this file should typically correspond to a datamanual revision. | ||
19 | * Datamanual revision that was used should be updated in comment below. | ||
20 | * If there is no update to datamanual, do not update the values. If you | ||
21 | * need to use values different from that recommended by the datamanual | ||
22 | * for your design, then you should consider adding values to the device- | ||
23 | * -tree file for your board directly. | ||
24 | * b) We keep the mode names as close to the datamanual as possible. So | ||
25 | * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, | ||
26 | * we follow that in code too. | ||
27 | * c) If the values change between multiple revisions of silicon, we add | ||
28 | * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, | ||
29 | * 'rev20' for PG 2.0 and so on. | ||
30 | * d) The node name and node label should be the exact same string. This is | ||
31 | * to curb naming creativity and achieve consistency. | ||
32 | * | ||
33 | * Datamanual Revisions: | ||
34 | * | ||
35 | * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017 | ||
36 | * | ||
37 | */ | ||
38 | |||
39 | &dra7_pmx_core { | ||
40 | mmc1_pins_default: mmc1_pins_default { | ||
41 | pinctrl-single,pins = < | ||
42 | 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ | ||
43 | 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
44 | 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
45 | 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
46 | 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
47 | 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
48 | >; | ||
49 | }; | ||
50 | |||
51 | mmc1_pins_sdr12: mmc1_pins_sdr12 { | ||
52 | pinctrl-single,pins = < | ||
53 | 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ | ||
54 | 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
55 | 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
56 | 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
57 | 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
58 | 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
59 | >; | ||
60 | }; | ||
61 | |||
62 | mmc1_pins_hs: mmc1_pins_hs { | ||
63 | pinctrl-single,pins = < | ||
64 | 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ | ||
65 | 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
66 | 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
67 | 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
68 | 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
69 | 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
70 | >; | ||
71 | }; | ||
72 | |||
73 | mmc1_pins_sdr25: mmc1_pins_sdr25 { | ||
74 | pinctrl-single,pins = < | ||
75 | 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ | ||
76 | 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
77 | 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
78 | 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
79 | 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
80 | 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
81 | >; | ||
82 | }; | ||
83 | |||
84 | mmc1_pins_sdr50: mmc1_pins_sdr50 { | ||
85 | pinctrl-single,pins = < | ||
86 | 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ | ||
87 | 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
88 | 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
89 | 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
90 | 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
91 | 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
92 | >; | ||
93 | }; | ||
94 | |||
95 | mmc1_pins_ddr50: mmc1_pins_ddr50 { | ||
96 | pinctrl-single,pins = < | ||
97 | 0x354 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ | ||
98 | 0x358 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
99 | 0x35c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
100 | 0x360 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
101 | 0x364 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
102 | 0x368 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
103 | >; | ||
104 | }; | ||
105 | |||
106 | mmc1_pins_sdr104: mmc1_pins_sdr104 { | ||
107 | pinctrl-single,pins = < | ||
108 | 0x354 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ | ||
109 | 0x358 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ | ||
110 | 0x35c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ | ||
111 | 0x360 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ | ||
112 | 0x364 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ | ||
113 | 0x368 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ | ||
114 | >; | ||
115 | }; | ||
116 | |||
117 | mmc2_pins_default: mmc2_pins_default { | ||
118 | pinctrl-single,pins = < | ||
119 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | ||
120 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | ||
121 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | ||
122 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | ||
123 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | ||
124 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | ||
125 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | ||
126 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | ||
127 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | ||
128 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | ||
129 | >; | ||
130 | }; | ||
131 | |||
132 | mmc2_pins_hs: mmc2_pins_hs { | ||
133 | pinctrl-single,pins = < | ||
134 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | ||
135 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | ||
136 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | ||
137 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | ||
138 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | ||
139 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | ||
140 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | ||
141 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | ||
142 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | ||
143 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | ||
144 | >; | ||
145 | }; | ||
146 | |||
147 | mmc2_pins_ddr: mmc2_pins_ddr { | ||
148 | pinctrl-single,pins = < | ||
149 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | ||
150 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | ||
151 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | ||
152 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | ||
153 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | ||
154 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | ||
155 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | ||
156 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | ||
157 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | ||
158 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | ||
159 | >; | ||
160 | }; | ||
161 | |||
162 | mmc2_pins_hs200: mmc2_pins_hs200 { | ||
163 | pinctrl-single,pins = < | ||
164 | 0x9c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ | ||
165 | 0xb0 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ | ||
166 | 0xa0 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ | ||
167 | 0xa4 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ | ||
168 | 0xa8 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ | ||
169 | 0xac (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ | ||
170 | 0x8c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ | ||
171 | 0x90 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ | ||
172 | 0x94 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ | ||
173 | 0x98 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ | ||
174 | >; | ||
175 | }; | ||
176 | }; | ||
177 | |||
178 | &dra7_iodelay_core { | ||
179 | |||
180 | /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ | ||
181 | mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf { | ||
182 | pinctrl-single,pins = < | ||
183 | 0x618 (A_DELAY(489) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */ | ||
184 | 0x624 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_IN */ | ||
185 | 0x630 (A_DELAY(374) | G_DELAY(0)) /* CFG_MMC1_DAT0_IN */ | ||
186 | 0x63c (A_DELAY(31) | G_DELAY(0)) /* CFG_MMC1_DAT1_IN */ | ||
187 | 0x648 (A_DELAY(56) | G_DELAY(0)) /* CFG_MMC1_DAT2_IN */ | ||
188 | 0x654 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */ | ||
189 | 0x620 (A_DELAY(1355) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */ | ||
190 | 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ | ||
191 | 0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ | ||
192 | 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ | ||
193 | 0x638 (A_DELAY(0) | G_DELAY(4)) /* CFG_MMC1_DAT0_OUT */ | ||
194 | 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ | ||
195 | 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ | ||
196 | 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ | ||
197 | 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ | ||
198 | 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ | ||
199 | 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ | ||
200 | >; | ||
201 | }; | ||
202 | |||
203 | /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ | ||
204 | mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf { | ||
205 | pinctrl-single,pins = < | ||
206 | 0x620 (A_DELAY(892) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */ | ||
207 | 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ | ||
208 | 0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ | ||
209 | 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ | ||
210 | 0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ | ||
211 | 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ | ||
212 | 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ | ||
213 | 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ | ||
214 | 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ | ||
215 | 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ | ||
216 | 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ | ||
217 | >; | ||
218 | }; | ||
219 | |||
220 | /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ | ||
221 | mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf { | ||
222 | pinctrl-single,pins = < | ||
223 | 0x190 (A_DELAY(384) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */ | ||
224 | 0x194 (A_DELAY(0) | G_DELAY(174)) /* CFG_GPMC_A19_OUT */ | ||
225 | 0x1a8 (A_DELAY(410) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */ | ||
226 | 0x1ac (A_DELAY(85) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ | ||
227 | 0x1b4 (A_DELAY(468) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */ | ||
228 | 0x1b8 (A_DELAY(139) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ | ||
229 | 0x1c0 (A_DELAY(676) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */ | ||
230 | 0x1c4 (A_DELAY(69) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ | ||
231 | 0x1d0 (A_DELAY(1062) | G_DELAY(154)) /* CFG_GPMC_A23_OUT */ | ||
232 | 0x1d8 (A_DELAY(640) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */ | ||
233 | 0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ | ||
234 | 0x1e4 (A_DELAY(356) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */ | ||
235 | 0x1e8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ | ||
236 | 0x1f0 (A_DELAY(579) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */ | ||
237 | 0x1f4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ | ||
238 | 0x1fc (A_DELAY(435) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */ | ||
239 | 0x200 (A_DELAY(36) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ | ||
240 | 0x364 (A_DELAY(759) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */ | ||
241 | 0x368 (A_DELAY(72) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ | ||
242 | >; | ||
243 | }; | ||
244 | }; | ||
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index aca5af86fc..0fd3d85d29 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h | |||
@@ -64,6 +64,7 @@ | |||
64 | #define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F | 64 | #define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F |
65 | #define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F | 65 | #define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F |
66 | #define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F | 66 | #define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F |
67 | #define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F | ||
67 | 68 | ||
68 | /* UART */ | 69 | /* UART */ |
69 | #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) | 70 | #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) |
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 57f8ad2fd7..951a407515 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h | |||
@@ -755,6 +755,7 @@ static inline u8 is_dra76x(void) | |||
755 | #define DRA752_ES2_0 0x07520200 | 755 | #define DRA752_ES2_0 0x07520200 |
756 | #define DRA722_ES1_0 0x07220100 | 756 | #define DRA722_ES1_0 0x07220100 |
757 | #define DRA722_ES2_0 0x07220200 | 757 | #define DRA722_ES2_0 0x07220200 |
758 | #define DRA722_ES2_1 0x07220210 | ||
758 | 759 | ||
759 | /* | 760 | /* |
760 | * SRAM scratch space entries | 761 | * SRAM scratch space entries |
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 9f0beebcb9..145f044f88 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c | |||
@@ -294,6 +294,7 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) | |||
294 | break; | 294 | break; |
295 | case DRA722_ES1_0: | 295 | case DRA722_ES1_0: |
296 | case DRA722_ES2_0: | 296 | case DRA722_ES2_0: |
297 | case DRA722_ES2_1: | ||
297 | if (ram_size < CONFIG_MAX_MEM_MAPPED) | 298 | if (ram_size < CONFIG_MAX_MEM_MAPPED) |
298 | *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; | 299 | *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; |
299 | else | 300 | else |
@@ -358,6 +359,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) | |||
358 | break; | 359 | break; |
359 | case DRA722_ES1_0: | 360 | case DRA722_ES1_0: |
360 | case DRA722_ES2_0: | 361 | case DRA722_ES2_0: |
362 | case DRA722_ES2_1: | ||
361 | default: | 363 | default: |
362 | if (ram_size < CONFIG_MAX_MEM_MAPPED) | 364 | if (ram_size < CONFIG_MAX_MEM_MAPPED) |
363 | *dmm_lisa_regs = &lisa_map_2G_x_2; | 365 | *dmm_lisa_regs = &lisa_map_2G_x_2; |
@@ -767,6 +769,7 @@ void recalibrate_iodelay(void) | |||
767 | switch (omap_revision()) { | 769 | switch (omap_revision()) { |
768 | case DRA722_ES1_0: | 770 | case DRA722_ES1_0: |
769 | case DRA722_ES2_0: | 771 | case DRA722_ES2_0: |
772 | case DRA722_ES2_1: | ||
770 | pads = dra72x_core_padconf_array_common; | 773 | pads = dra72x_core_padconf_array_common; |
771 | npads = ARRAY_SIZE(dra72x_core_padconf_array_common); | 774 | npads = ARRAY_SIZE(dra72x_core_padconf_array_common); |
772 | if (board_is_dra71x_evm()) { | 775 | if (board_is_dra71x_evm()) { |
@@ -896,6 +899,14 @@ static struct pinctrl_desc pinctrl_descs_hsmmc2_dra72x[] = { | |||
896 | {NULL} | 899 | {NULL} |
897 | }; | 900 | }; |
898 | 901 | ||
902 | static struct pinctrl_desc pinctrl_descs_hsmmc2_dra76x[] = { | ||
903 | {"default", &hsmmc2_default_hs}, | ||
904 | {"hs", &hsmmc2_default_hs}, | ||
905 | {"ddr_1_8v", &hsmmc2_default_hs}, | ||
906 | {"hs200_1_8v", &hsmmc2_hs200_1v8_dra76}, | ||
907 | {NULL} | ||
908 | }; | ||
909 | |||
899 | struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode | 910 | struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode |
900 | (struct hsmmc *base, const char *mode) | 911 | (struct hsmmc *base, const char *mode) |
901 | { | 912 | { |
@@ -911,6 +922,8 @@ struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode | |||
911 | p = pinctrl_descs_hsmmc2_rev11; | 922 | p = pinctrl_descs_hsmmc2_rev11; |
912 | else if (is_dra72x()) | 923 | else if (is_dra72x()) |
913 | p = pinctrl_descs_hsmmc2_dra72x; | 924 | p = pinctrl_descs_hsmmc2_dra72x; |
925 | else if (is_dra76x()) | ||
926 | p = pinctrl_descs_hsmmc2_dra76x; | ||
914 | else if (is_dra7xx()) | 927 | else if (is_dra7xx()) |
915 | p = pinctrl_descs_hsmmc2_rev20; | 928 | p = pinctrl_descs_hsmmc2_rev20; |
916 | break; | 929 | break; |
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 535b4f5e1e..3fe52b19b2 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h | |||
@@ -1575,6 +1575,28 @@ static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_dra72_conf[] = { | |||
1575 | {0x364, 1039 , 0 /* CFG_GPMC_CS1_OEN */}, | 1575 | {0x364, 1039 , 0 /* CFG_GPMC_CS1_OEN */}, |
1576 | }; | 1576 | }; |
1577 | 1577 | ||
1578 | static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_dra76_conf[] = { | ||
1579 | {0x190, 384 , 0 /* CFG_GPMC_A19_OEN */}, | ||
1580 | {0x194, 0 , 174 /* CFG_GPMC_A19_OUT */}, | ||
1581 | {0x1A8, 410 , 0 /* CFG_GPMC_A20_OEN */}, | ||
1582 | {0x1AC, 85 , 0 /* CFG_GPMC_A20_OUT */}, | ||
1583 | {0x1B4, 468 , 0 /* CFG_GPMC_A21_OEN */}, | ||
1584 | {0x1B8, 139 , 0 /* CFG_GPMC_A21_OUT */}, | ||
1585 | {0x1C0, 676 , 0 /* CFG_GPMC_A22_OEN */}, | ||
1586 | {0x1C4, 69 , 0 /* CFG_GPMC_A22_OUT */}, | ||
1587 | {0x1D0, 1062, 154 /* CFG_GPMC_A23_OUT */}, | ||
1588 | {0x1D8, 640 , 0 /* CFG_GPMC_A24_OEN */}, | ||
1589 | {0x1DC, 0 , 0 /* CFG_GPMC_A24_OUT */}, | ||
1590 | {0x1E4, 356 , 0 /* CFG_GPMC_A25_OEN */}, | ||
1591 | {0x1E8, 0 , 0 /* CFG_GPMC_A25_OUT */}, | ||
1592 | {0x1F0, 579 , 0 /* CFG_GPMC_A26_OEN */}, | ||
1593 | {0x1F4, 0 , 0 /* CFG_GPMC_A26_OUT */}, | ||
1594 | {0x1FC, 435 , 0 /* CFG_GPMC_A27_OEN */}, | ||
1595 | {0x200, 36 , 0 /* CFG_GPMC_A27_OUT */}, | ||
1596 | {0x364, 759 , 0 /* CFG_GPMC_CS1_OEN */}, | ||
1597 | {0x368, 72 , 0 /* CFG_GPMC_CS1_OUT */}, | ||
1598 | }; | ||
1599 | |||
1578 | #define dimof(t) (sizeof(t) / sizeof(t[0])) | 1600 | #define dimof(t) (sizeof(t) / sizeof(t[0])) |
1579 | static struct omap_hsmmc_pinctrl_state hsmmc1_default = { | 1601 | static struct omap_hsmmc_pinctrl_state hsmmc1_default = { |
1580 | .padconf = hsmmc1_default_padconf, | 1602 | .padconf = hsmmc1_default_padconf, |
@@ -1632,6 +1654,13 @@ static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_dra72 = { | |||
1632 | .iodelay = mmc2_iodelay_hs200_1_8v_dra72_conf, | 1654 | .iodelay = mmc2_iodelay_hs200_1_8v_dra72_conf, |
1633 | .niodelays = dimof(mmc2_iodelay_hs200_1_8v_dra72_conf), | 1655 | .niodelays = dimof(mmc2_iodelay_hs200_1_8v_dra72_conf), |
1634 | }; | 1656 | }; |
1657 | |||
1658 | static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_dra76 = { | ||
1659 | .padconf = mmc2_pins_ddr_hs200_1_8v, | ||
1660 | .npads = dimof(mmc2_pins_ddr_hs200_1_8v), | ||
1661 | .iodelay = mmc2_iodelay_hs200_1_8v_dra76_conf, | ||
1662 | .niodelays = dimof(mmc2_iodelay_hs200_1_8v_dra76_conf), | ||
1663 | }; | ||
1635 | #endif | 1664 | #endif |
1636 | 1665 | ||
1637 | #endif /* _MUX_DATA_DRA7XX_H_ */ | 1666 | #endif /* _MUX_DATA_DRA7XX_H_ */ |