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authorLCPD Auto Merger2017-07-17 21:13:23 -0500
committerLCPD Auto Merger2017-07-17 21:13:23 -0500
commita979feec846a1dfffdfc2252c4a7c1a4e413dca9 (patch)
tree793e9eadf58cb5a5a7b6197d72ea99134ff72134
parentb99a5a8c86b50971fe165dc2da8a72a03e1718e1 (diff)
parent0a7a53f3a56857c11a1e3a132431cfa484318492 (diff)
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Merge branch 'maint-ti-u-boot-2016.05' of git.ti.com:ti-u-boot/maint-ti-u-boot into ti-u-boot-2016.05
TI-Feature: maint-uboot-2016 TI-Tree: git@git.ti.com:ti-u-boot/maint-ti-u-boot.git TI-Branch: maint-ti-u-boot-2016.05 * 'maint-ti-u-boot-2016.05' of git.ti.com:ti-u-boot/maint-ti-u-boot: arm: omap: enable high speed mode support in SPL for the eMMC on AM572 and AM571 arm: omap: enable high speed mode support in SPL for the eMMC on DRA7x and DRA72. drivers: omap_hsmmc: Add debug information about the selected timing drivers: omap_hsmmc: If DM_MMC is not used, get the iodelays and the pinmux from the platform code mmc: omap_hsmmc: support for HS200 and DDR52 modes without DM_MMC mmc: omap_hsmmc: re-arrange code layout. mmc: omap_hsmmc: Configure PBIAS only for MMC1 mmc: omap_hsmmc: Enable ADMA support even if DM_MMC is not used omap: Update the base address of the MMC controllers drivers: mmc: fall back to lower performance modes if HS200 or DDR52 fail during the initialization Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
-rw-r--r--arch/arm/include/asm/arch-am33xx/mmc_host_def.h4
-rw-r--r--arch/arm/include/asm/arch-omap4/mmc_host_def.h6
-rw-r--r--arch/arm/include/asm/arch-omap5/mmc_host_def.h6
-rw-r--r--arch/arm/include/asm/arch-omap5/sys_proto.h7
-rw-r--r--arch/arm/include/asm/omap_mmc.h5
-rw-r--r--arch/arm/mach-keystone/include/mach/mmc_host_def.h4
-rw-r--r--board/ti/am57xx/board.c61
-rw-r--r--board/ti/am57xx/mux_data.h132
-rw-r--r--board/ti/dra7xx/evm.c74
-rw-r--r--board/ti/dra7xx/mux_data.h261
-rw-r--r--drivers/mmc/mmc.c50
-rw-r--r--drivers/mmc/omap_hsmmc.c361
-rw-r--r--include/mmc.h1
13 files changed, 802 insertions, 170 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index 724e252946..5a2ea8faef 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -21,8 +21,8 @@
21/* 21/*
22 * OMAP HSMMC register definitions 22 * OMAP HSMMC register definitions
23 */ 23 */
24#define OMAP_HSMMC1_BASE 0x48060100 24#define OMAP_HSMMC1_BASE 0x48060000
25#define OMAP_HSMMC2_BASE 0x481D8100 25#define OMAP_HSMMC2_BASE 0x481D8000
26 26
27#if defined(CONFIG_TI814X) 27#if defined(CONFIG_TI814X)
28#undef MMC_CLOCK_REFERENCE 28#undef MMC_CLOCK_REFERENCE
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
index 9c8ccb6c83..d06779956f 100644
--- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -31,8 +31,8 @@
31 * OMAP HSMMC register definitions 31 * OMAP HSMMC register definitions
32 */ 32 */
33 33
34#define OMAP_HSMMC1_BASE 0x4809C100 34#define OMAP_HSMMC1_BASE 0x4809C000
35#define OMAP_HSMMC2_BASE 0x480B4100 35#define OMAP_HSMMC2_BASE 0x480B4000
36#define OMAP_HSMMC3_BASE 0x480AD100 36#define OMAP_HSMMC3_BASE 0x480AD000
37 37
38#endif /* MMC_HOST_DEF_H */ 38#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
index 9c8ccb6c83..d06779956f 100644
--- a/arch/arm/include/asm/arch-omap5/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
@@ -31,8 +31,8 @@
31 * OMAP HSMMC register definitions 31 * OMAP HSMMC register definitions
32 */ 32 */
33 33
34#define OMAP_HSMMC1_BASE 0x4809C100 34#define OMAP_HSMMC1_BASE 0x4809C000
35#define OMAP_HSMMC2_BASE 0x480B4100 35#define OMAP_HSMMC2_BASE 0x480B4000
36#define OMAP_HSMMC3_BASE 0x480AD100 36#define OMAP_HSMMC3_BASE 0x480AD000
37 37
38#endif /* MMC_HOST_DEF_H */ 38#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index d25e4faec3..26137f680e 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -35,6 +35,13 @@ struct pad_conf_entry {
35 u32 val; 35 u32 val;
36}; 36};
37 37
38struct omap_hsmmc_pinctrl_state {
39 struct pad_conf_entry *padconf;
40 int npads;
41 struct iodelay_cfg_entry *iodelay;
42 int niodelays;
43};
44
38struct omap_sysinfo { 45struct omap_sysinfo {
39 char *board_string; 46 char *board_string;
40}; 47};
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 767f8ec50a..406010bbbe 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -26,7 +26,7 @@
26#define OMAP_MMC_H_ 26#define OMAP_MMC_H_
27 27
28struct hsmmc { 28struct hsmmc {
29#ifdef CONFIG_DM_MMC 29#ifndef CONFIG_OMAP34XX
30 unsigned int hl_rev; 30 unsigned int hl_rev;
31 unsigned int hl_hwinfo; 31 unsigned int hl_hwinfo;
32 unsigned int hl_sysconfig; 32 unsigned int hl_sysconfig;
@@ -225,7 +225,8 @@ struct hsmmc {
225 225
226int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, 226int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
227 int wp_gpio); 227 int wp_gpio);
228
229int platform_fixup_disable_uhs_mode(void); 228int platform_fixup_disable_uhs_mode(void);
229struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
230 (struct hsmmc *base, const char *mode);
230void vmmc_pbias_config(uint voltage); 231void vmmc_pbias_config(uint voltage);
231#endif /* OMAP_MMC_H_ */ 232#endif /* OMAP_MMC_H_ */
diff --git a/arch/arm/mach-keystone/include/mach/mmc_host_def.h b/arch/arm/mach-keystone/include/mach/mmc_host_def.h
index a5050ac0f1..b8eed7d29b 100644
--- a/arch/arm/mach-keystone/include/mach/mmc_host_def.h
+++ b/arch/arm/mach-keystone/include/mach/mmc_host_def.h
@@ -16,7 +16,7 @@
16 * OMAP HSMMC register definitions 16 * OMAP HSMMC register definitions
17 */ 17 */
18 18
19#define OMAP_HSMMC1_BASE 0x23000100 19#define OMAP_HSMMC1_BASE 0x23000000
20#define OMAP_HSMMC2_BASE 0x23100100 20#define OMAP_HSMMC2_BASE 0x23100000
21 21
22#endif /* K2G_MMC_HOST_DEF_H */ 22#endif /* K2G_MMC_HOST_DEF_H */
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 00a2feab24..2732aaa983 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -718,6 +718,67 @@ int board_mmc_init(bd_t *bis)
718} 718}
719#endif 719#endif
720 720
721#if defined(CONFIG_IODELAY_RECALIBRATION) && \
722 (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC))
723
724struct pinctrl_desc {
725 const char *name;
726 struct omap_hsmmc_pinctrl_state *pinctrl;
727};
728
729static struct pinctrl_desc pinctrl_descs_hsmmc1[] = {
730 {"default", &hsmmc1_default},
731 {"hs", &hsmmc1_default},
732 {NULL}
733};
734
735static struct pinctrl_desc pinctrl_descs_hsmmc2_am572[] = {
736 {"default", &hsmmc2_default_hs},
737 {"hs", &hsmmc2_default_hs},
738 {"ddr_1_8v", &hsmmc2_ddr_am572},
739 {NULL}
740};
741
742static struct pinctrl_desc pinctrl_descs_hsmmc2_am571[] = {
743 {"default", &hsmmc2_default_hs},
744 {"hs", &hsmmc2_default_hs},
745 {"ddr_1_8v", &hsmmc2_ddr_am571},
746 {NULL}
747};
748
749struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
750 (struct hsmmc *base, const char *mode)
751{
752 struct pinctrl_desc *p = NULL;
753
754 switch ((uint32_t)base) {
755 case OMAP_HSMMC1_BASE:
756 p = pinctrl_descs_hsmmc1;
757 break;
758 case OMAP_HSMMC2_BASE:
759 if (is_dra72x())
760 p = pinctrl_descs_hsmmc2_am571;
761 else
762 p = pinctrl_descs_hsmmc2_am572;
763 break;
764 default:
765 break;
766 }
767
768 if (!p) {
769 printf("%s no pinctrl defined for MMC@%p\n", __func__,
770 base);
771 return NULL;
772 }
773 while (p->name) {
774 if (strcmp(mode, p->name) == 0)
775 return p->pinctrl;
776 p++;
777 }
778 return NULL;
779}
780#endif
781
721#ifdef CONFIG_OMAP_HSMMC 782#ifdef CONFIG_OMAP_HSMMC
722int platform_fixup_disable_uhs_mode(void) 783int platform_fixup_disable_uhs_mode(void)
723{ 784{
diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h
index aff274c74f..3c99905dd2 100644
--- a/board/ti/am57xx/mux_data.h
+++ b/board/ti/am57xx/mux_data.h
@@ -985,4 +985,136 @@ const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] = {
985}; 985};
986 986
987#endif 987#endif
988
989#if defined(CONFIG_IODELAY_RECALIBRATION) && \
990 (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC))
991
992static struct iodelay_cfg_entry mmc2_iodelay_ddr_am572[] = {
993 {0x18c, 270, 0 /* CFG_GPMC_A19_IN */},
994 {0x1a4, 0, 0 /* CFG_GPMC_A20_IN */},
995 {0x1b0, 170, 0 /* CFG_GPMC_A21_IN */},
996 {0x1bc, 758, 0 /* CFG_GPMC_A22_IN */},
997 {0x1c8, 0, 0 /* CFG_GPMC_A23_IN */},
998 {0x1d4, 81, 0 /* CFG_GPMC_A24_IN */},
999 {0x1e0, 286, 0 /* CFG_GPMC_A25_IN */},
1000 {0x1ec, 0, 0 /* CFG_GPMC_A26_IN */},
1001 {0x1f8, 123, 0 /* CFG_GPMC_A27_IN */},
1002 {0x360, 346, 0 /* CFG_GPMC_CS1_IN */},
1003 {0x190, 0, 0 /* CFG_GPMC_A19_OEN */},
1004 {0x194, 55, 0 /* CFG_GPMC_A19_OUT */},
1005 {0x1a8, 0, 0 /* CFG_GPMC_A20_OEN */},
1006 {0x1ac, 422, 0 /* CFG_GPMC_A20_OUT */},
1007 {0x1b4, 642, 0 /* CFG_GPMC_A21_OEN */},
1008 {0x1b8, 0, 0 /* CFG_GPMC_A21_OUT */},
1009 {0x1c0, 0, 0 /* CFG_GPMC_A22_OEN */},
1010 {0x1c4, 128, 0 /* CFG_GPMC_A22_OUT */},
1011 {0x1d0, 0, 0 /* CFG_GPMC_A23_OUT */},
1012 {0x1d8, 0, 0 /* CFG_GPMC_A24_OEN */},
1013 {0x1dc, 395, 0 /* CFG_GPMC_A24_OUT */},
1014 {0x1e4, 0, 0 /* CFG_GPMC_A25_OEN */},
1015 {0x1e8, 0, 0 /* CFG_GPMC_A25_OUT */},
1016 {0x1f0, 623, 0 /* CFG_GPMC_A26_OEN */},
1017 {0x1f4, 0, 0 /* CFG_GPMC_A26_OUT */},
1018 {0x1fc, 54, 0 /* CFG_GPMC_A27_OEN */},
1019 {0x200, 0, 0 /* CFG_GPMC_A27_OUT */},
1020 {0x364, 0, 0 /* CFG_GPMC_CS1_OEN */},
1021 {0x368, 0, 0 /* CFG_GPMC_CS1_OUT */},
1022};
1023
1024static struct iodelay_cfg_entry mmc2_iodelay_ddr_am571[] = {
1025 {0x18c, 0, 0, /* CFG_GPMC_A19_IN */},
1026 {0x1a4, 121, 0, /* CFG_GPMC_A20_IN */},
1027 {0x1b0, 0, 0, /* CFG_GPMC_A21_IN */},
1028 {0x1bc, 20, 0, /* CFG_GPMC_A22_IN */},
1029 {0x1c8, 108, 0, /* CFG_GPMC_A23_IN */},
1030 {0x1d4, 31, 0, /* CFG_GPMC_A24_IN */},
1031 {0x1e0, 0, 0, /* CFG_GPMC_A25_IN */},
1032 {0x1ec, 24, 0, /* CFG_GPMC_A26_IN */},
1033 {0x1f8, 0, 0, /* CFG_GPMC_A27_IN */},
1034 {0x360, 0, 0, /* CFG_GPMC_CS1_IN */},
1035 {0x194, 152, 0, /* CFG_GPMC_A19_OUT */},
1036 {0x1ac, 206, 0, /* CFG_GPMC_A20_OUT */},
1037 {0x1b8, 78, 0, /* CFG_GPMC_A21_OUT */},
1038 {0x1c4, 2, 0, /* CFG_GPMC_A22_OUT */},
1039 {0x1d0, 266, 0, /* CFG_GPMC_A23_OUT */},
1040 {0x1dc, 0, 0, /* CFG_GPMC_A24_OUT */},
1041 {0x1e8, 0, 0, /* CFG_GPMC_A25_OUT */},
1042 {0x1f4, 43, 0, /* CFG_GPMC_A26_OUT */},
1043 {0x200, 0, 0, /* CFG_GPMC_A27_OUT */},
1044 {0x368, 0, 0, /* CFG_GPMC_CS1_OUT */},
1045 {0x190, 0, 0, /* CFG_GPMC_A19_OEN */},
1046 {0x1a8, 0, 0, /* CFG_GPMC_A20_OEN */},
1047 {0x1b4, 0, 0, /* CFG_GPMC_A21_OEN */},
1048 {0x1c0, 0, 0, /* CFG_GPMC_A22_OEN */},
1049 {0x1d8, 0, 0, /* CFG_GPMC_A24_OEN */},
1050 {0x1e4, 0, 0, /* CFG_GPMC_A25_OEN */},
1051 {0x1f0, 0, 0, /* CFG_GPMC_A26_OEN */},
1052 {0x1fc, 0, 0, /* CFG_GPMC_A27_OEN */},
1053 {0x364, 0, 0, /* CFG_GPMC_CS1_OEN */},
1054};
1055
1056static struct pad_conf_entry hsmmc1_default_padconf[] = {
1057 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP) /* mmc1_clk.clk */},
1058 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP) /* mmc1_cmd.cmd */},
1059 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat0.dat0 */},
1060 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat1.dat1 */},
1061 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat2.dat2 */},
1062 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat3.dat3 */},
1063};
1064
1065static struct pad_conf_entry mmc2_pins_ddr[] = {
1066 {GPMC_A23, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a23.mmc2_clk */},
1067 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_cs1.mmc2_cmd */},
1068 {GPMC_A24, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a24.mmc2_dat0 */},
1069 {GPMC_A25, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a25.mmc2_dat1 */},
1070 {GPMC_A26, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a26.mmc2_dat2 */},
1071 {GPMC_A27, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a27.mmc2_dat3 */},
1072 {GPMC_A19, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a19.mmc2_dat4 */},
1073 {GPMC_A20, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a20.mmc2_dat5 */},
1074 {GPMC_A21, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a21.mmc2_dat6 */},
1075 {GPMC_A22, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a22.mmc2_dat7 */},
1076};
1077
1078static struct pad_conf_entry mmc2_pins_default_hs[] = {
1079 {GPMC_A23, (M1 | PIN_INPUT_PULLUP) /* g pmc_a23.mmc2_clk */},
1080 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP) /* gpmc_cs1.mmc2_cmd */},
1081 {GPMC_A24, (M1 | PIN_INPUT_PULLUP) /* gpmc_a24.mmc2_dat0 */},
1082 {GPMC_A25, (M1 | PIN_INPUT_PULLUP) /* gpmc_a25.mmc2_dat1 */},
1083 {GPMC_A26, (M1 | PIN_INPUT_PULLUP) /* gpmc_a26.mmc2_dat2 */},
1084 {GPMC_A27, (M1 | PIN_INPUT_PULLUP) /* gpmc_a27.mmc2_dat3 */},
1085 {GPMC_A19, (M1 | PIN_INPUT_PULLUP) /* gpmc_a19.mmc2_dat4 */},
1086 {GPMC_A20, (M1 | PIN_INPUT_PULLUP) /* gpmc_a20.mmc2_dat5 */},
1087 {GPMC_A21, (M1 | PIN_INPUT_PULLUP) /* gpmc_a21.mmc2_dat6 */},
1088 {GPMC_A22, (M1 | PIN_INPUT_PULLUP) /* gpmc_a22.mmc2_dat7 */},
1089};
1090
1091static struct omap_hsmmc_pinctrl_state hsmmc1_default = {
1092 .padconf = hsmmc1_default_padconf,
1093 .npads = ARRAY_SIZE(hsmmc1_default_padconf),
1094 .iodelay = NULL,
1095 .niodelays = 0,
1096};
1097
1098static struct omap_hsmmc_pinctrl_state hsmmc2_default_hs = {
1099 .padconf = mmc2_pins_default_hs,
1100 .npads = ARRAY_SIZE(mmc2_pins_default_hs),
1101 .iodelay = NULL,
1102 .niodelays = 0,
1103};
1104
1105static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_am572 = {
1106 .padconf = mmc2_pins_ddr,
1107 .npads = ARRAY_SIZE(mmc2_pins_ddr),
1108 .iodelay = mmc2_iodelay_ddr_am572,
1109 .niodelays = ARRAY_SIZE(mmc2_iodelay_ddr_am572),
1110};
1111
1112static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_am571 = {
1113 .padconf = mmc2_pins_ddr,
1114 .npads = ARRAY_SIZE(mmc2_pins_ddr),
1115 .iodelay = mmc2_iodelay_ddr_am571,
1116 .niodelays = ARRAY_SIZE(mmc2_iodelay_ddr_am571),
1117};
1118
1119#endif
988#endif /* _MUX_DATA_BEAGLE_X15_H_ */ 1120#endif /* _MUX_DATA_BEAGLE_X15_H_ */
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 00b1d5b8ba..39808474cc 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -710,6 +710,80 @@ int board_mmc_init(bd_t *bis)
710#endif 710#endif
711 711
712#ifdef CONFIG_OMAP_HSMMC 712#ifdef CONFIG_OMAP_HSMMC
713#if defined(CONFIG_IODELAY_RECALIBRATION) && \
714 (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC))
715
716struct pinctrl_desc {
717 const char *name;
718 struct omap_hsmmc_pinctrl_state *pinctrl;
719};
720
721static struct pinctrl_desc pinctrl_descs_hsmmc1[] = {
722 {"default", &hsmmc1_default},
723 {"hs", &hsmmc1_default},
724 {NULL}
725};
726
727static struct pinctrl_desc pinctrl_descs_hsmmc2_rev20[] = {
728 {"default", &hsmmc2_default_hs},
729 {"hs", &hsmmc2_default_hs},
730 {"ddr_1_8v", &hsmmc2_ddr_1v8_rev20},
731 {"hs200_1_8v", &hsmmc2_hs200_1v8_rev20},
732 {NULL}
733};
734
735static struct pinctrl_desc pinctrl_descs_hsmmc2_rev11[] = {
736 {"default", &hsmmc2_default_hs},
737 {"hs", &hsmmc2_default_hs},
738 {"ddr_1_8v", &hsmmc2_ddr_1v8_rev11},
739 {"hs200_1_8v", &hsmmc2_hs200_1v8_rev11},
740 {NULL}
741};
742
743static struct pinctrl_desc pinctrl_descs_hsmmc2_dra72x[] = {
744 {"default", &hsmmc2_default_hs},
745 {"hs", &hsmmc2_default_hs},
746 {"ddr_1_8v", &hsmmc2_ddr_1v8_dra72},
747 {"hs200_1_8v", &hsmmc2_hs200_1v8_dra72},
748 {NULL}
749};
750
751struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
752 (struct hsmmc *base, const char *mode)
753{
754 struct pinctrl_desc *p = NULL;
755
756 switch ((uint32_t)base) {
757 case OMAP_HSMMC1_BASE:
758 p = pinctrl_descs_hsmmc1;
759 break;
760 case OMAP_HSMMC2_BASE:
761 if ((omap_revision() == DRA752_ES1_0) ||
762 (omap_revision() == DRA752_ES1_1))
763 p = pinctrl_descs_hsmmc2_rev11;
764 else if (is_dra72x())
765 p = pinctrl_descs_hsmmc2_dra72x;
766 else if (is_dra7xx())
767 p = pinctrl_descs_hsmmc2_rev20;
768 break;
769 default:
770 break;
771 }
772
773 if (!p) {
774 printf("%s no pinctrl defined for MMC@%p\n", __func__,
775 base);
776 return NULL;
777 }
778 while (p->name) {
779 if (strcmp(mode, p->name) == 0)
780 return p->pinctrl;
781 p++;
782 }
783 return NULL;
784}
785#endif
786
713int platform_fixup_disable_uhs_mode(void) 787int platform_fixup_disable_uhs_mode(void)
714{ 788{
715 return omap_revision() == DRA752_ES1_1; 789 return omap_revision() == DRA752_ES1_1;
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 2cc4be31b2..54d5995628 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -828,4 +828,265 @@ const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = {
828}; 828};
829#endif 829#endif
830 830
831
832#if defined(CONFIG_IODELAY_RECALIBRATION) && \
833 (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC)) && \
834 defined(CONFIG_OMAP_HSMMC)
835
836static struct pad_conf_entry hsmmc1_default_padconf[] = {
837 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP) /* mmc1_clk.clk */},
838 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP) /* mmc1_cmd.cmd */},
839 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat0.dat0 */},
840 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat1.dat1 */},
841 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat2.dat2 */},
842 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat3.dat3 */},
843};
844
845static struct pad_conf_entry mmc2_pins_default_hs[] = {
846 {GPMC_A23, (M1 | PIN_INPUT_PULLUP) /* g pmc_a23.mmc2_clk */},
847 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP) /* gpmc_cs1.mmc2_cmd */},
848 {GPMC_A24, (M1 | PIN_INPUT_PULLUP) /* gpmc_a24.mmc2_dat0 */},
849 {GPMC_A25, (M1 | PIN_INPUT_PULLUP) /* gpmc_a25.mmc2_dat1 */},
850 {GPMC_A26, (M1 | PIN_INPUT_PULLUP) /* gpmc_a26.mmc2_dat2 */},
851 {GPMC_A27, (M1 | PIN_INPUT_PULLUP) /* gpmc_a27.mmc2_dat3 */},
852 {GPMC_A19, (M1 | PIN_INPUT_PULLUP) /* gpmc_a19.mmc2_dat4 */},
853 {GPMC_A20, (M1 | PIN_INPUT_PULLUP) /* gpmc_a20.mmc2_dat5 */},
854 {GPMC_A21, (M1 | PIN_INPUT_PULLUP) /* gpmc_a21.mmc2_dat6 */},
855 {GPMC_A22, (M1 | PIN_INPUT_PULLUP) /* gpmc_a22.mmc2_dat7 */},
856};
857
858static struct pad_conf_entry mmc2_pins_ddr_hs200_1_8v[] = {
859 {GPMC_A23, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a23.mmc2_clk */},
860 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_cs1.mmc2_cmd */},
861 {GPMC_A24, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a24.mmc2_dat0 */},
862 {GPMC_A25, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a25.mmc2_dat1 */},
863 {GPMC_A26, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a26.mmc2_dat2 */},
864 {GPMC_A27, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a27.mmc2_dat3 */},
865 {GPMC_A19, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a19.mmc2_dat4 */},
866 {GPMC_A20, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a20.mmc2_dat5 */},
867 {GPMC_A21, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a21.mmc2_dat6 */},
868 {GPMC_A22, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a22.mmc2_dat7 */},
869};
870
871static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_rev11_conf[] = {
872 {0x190, 621, 600 /* CFG_GPMC_A19_OEN */},
873 {0x194, 300, 0 /* CFG_GPMC_A19_OUT */},
874 {0x1a8, 739, 600 /* CFG_GPMC_A20_OEN */},
875 {0x1ac, 240, 0 /* CFG_GPMC_A20_OUT */},
876 {0x1b4, 812, 600 /* CFG_GPMC_A21_OEN */},
877 {0x1b8, 240, 0 /* CFG_GPMC_A21_OUT */},
878 {0x1c0, 954, 600 /* CFG_GPMC_A22_OEN */},
879 {0x1c4, 60, 0 /* CFG_GPMC_A22_OUT */},
880 {0x1d0, 1340, 420 /* CFG_GPMC_A23_OUT */},
881 {0x1d8, 935, 600 /* CFG_GPMC_A24_OEN */},
882 {0x1dc, 0, 0 /* CFG_GPMC_A24_OUT */},
883 {0x1e4, 525, 600 /* CFG_GPMC_A25_OEN */},
884 {0x1e8, 120, 0 /* CFG_GPMC_A25_OUT */},
885 {0x1f0, 767, 600 /* CFG_GPMC_A26_OEN */},
886 {0x1f4, 225, 0 /* CFG_GPMC_A26_OUT */},
887 {0x1fc, 565, 600 /* CFG_GPMC_A27_OEN */},
888 {0x200, 60, 0 /* CFG_GPMC_A27_OUT */},
889 {0x364, 969, 600 /* CFG_GPMC_CS1_OEN */},
890 {0x368, 180, 0 /* CFG_GPMC_CS1_OUT */},
891};
892
893static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_rev20_conf[] = {
894 {0x190, 274, 0 /* CFG_GPMC_A19_OEN */},
895 {0x194, 162, 0 /* CFG_GPMC_A19_OUT */},
896 {0x1a8, 401, 0 /* CFG_GPMC_A20_OEN */},
897 {0x1ac, 73, 0 /* CFG_GPMC_A20_OUT */},
898 {0x1b4, 465, 0 /* CFG_GPMC_A21_OEN */},
899 {0x1b8, 115, 0 /* CFG_GPMC_A21_OUT */},
900 {0x1c0, 633, 0 /* CFG_GPMC_A22_OEN */},
901 {0x1c4, 47, 0 /* CFG_GPMC_A22_OUT */},
902 {0x1d0, 935, 280 /* CFG_GPMC_A23_OUT */},
903 {0x1d8, 621, 0 /* CFG_GPMC_A24_OEN */},
904 {0x1dc, 0, 0 /* CFG_GPMC_A24_OUT */},
905 {0x1e4, 183, 0 /* CFG_GPMC_A25_OEN */},
906 {0x1e8, 0, 0 /* CFG_GPMC_A25_OUT */},
907 {0x1f0, 467, 0 /* CFG_GPMC_A26_OEN */},
908 {0x1f4, 0, 0 /* CFG_GPMC_A26_OUT */},
909 {0x1fc, 262, 0 /* CFG_GPMC_A27_OEN */},
910 {0x200, 46, 0 /* CFG_GPMC_A27_OUT */},
911 {0x364, 684, 0 /* CFG_GPMC_CS1_OEN */},
912 {0x368, 76, 0 /* CFG_GPMC_CS1_OUT */},
913};
914
915static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_rev11_conf[] = {
916 {0x18c, 0, 0 /* CFG_GPMC_A19_IN */},
917 {0x1a4, 274, 240 /* CFG_GPMC_A20_IN */},
918 {0x1b0, 0, 60 /* CFG_GPMC_A21_IN */},
919 {0x1bc, 0, 60 /* CFG_GPMC_A22_IN */},
920 {0x1c8, 514, 360 /* CFG_GPMC_A23_IN */},
921 {0x1d4, 187, 120 /* CFG_GPMC_A24_IN */},
922 {0x1e0, 0, 0 /* CFG_GPMC_A25_IN */},
923 {0x1ec, 0, 60 /* CFG_GPMC_A26_IN */},
924 {0x1f8, 121, 60 /* CFG_GPMC_A27_IN */},
925 {0x360, 0, 0 /* CFG_GPMC_CS1_IN */},
926 {0x190, 0, 0 /* CFG_GPMC_A19_OEN */},
927 {0x194, 174, 0 /* CFG_GPMC_A19_OUT */},
928 {0x1a8, 0, 0 /* CFG_GPMC_A20_OEN */},
929 {0x1ac, 168, 0 /* CFG_GPMC_A20_OUT */},
930 {0x1b4, 0, 0 /* CFG_GPMC_A21_OEN */},
931 {0x1b8, 136, 0 /* CFG_GPMC_A21_OUT */},
932 {0x1c0, 0, 0 /* CFG_GPMC_A22_OEN */},
933 {0x1c4, 0, 0 /* CFG_GPMC_A22_OUT */},
934 {0x1d0, 879, 0 /* CFG_GPMC_A23_OUT */},
935 {0x1d8, 0, 0 /* CFG_GPMC_A24_OEN */},
936 {0x1dc, 0, 0 /* CFG_GPMC_A24_OUT */},
937 {0x1e4, 0, 0 /* CFG_GPMC_A25_OEN */},
938 {0x1e8, 34, 0 /* CFG_GPMC_A25_OUT */},
939 {0x1f0, 0, 0 /* CFG_GPMC_A26_OEN */},
940 {0x1f4, 120, 0 /* CFG_GPMC_A26_OUT */},
941 {0x1fc, 0, 0 /* CFG_GPMC_A27_OEN */},
942 {0x200, 0, 0 /* CFG_GPMC_A27_OUT */},
943 {0x364, 0, 0 /* CFG_GPMC_CS1_OEN */},
944 {0x368, 11, 0 /* CFG_GPMC_CS1_OUT */},
945};
946
947static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_rev20_conf[] = {
948 {0x18c, 270, 0 /* CFG_GPMC_A19_IN */},
949 {0x1a4, 0, 0 /* CFG_GPMC_A20_IN */},
950 {0x1b0, 170, 0 /* CFG_GPMC_A21_IN */},
951 {0x1bc, 758, 0 /* CFG_GPMC_A22_IN */},
952 {0x1c8, 0, 0 /* CFG_GPMC_A23_IN */},
953 {0x1d4, 81, 0 /* CFG_GPMC_A24_IN */},
954 {0x1e0, 286, 0 /* CFG_GPMC_A25_IN */},
955 {0x1ec, 0, 0 /* CFG_GPMC_A26_IN */},
956 {0x1f8, 123, 0 /* CFG_GPMC_A27_IN */},
957 {0x360, 346, 0 /* CFG_GPMC_CS1_IN */},
958 {0x190, 0, 0 /* CFG_GPMC_A19_OEN */},
959 {0x194, 55, 0 /* CFG_GPMC_A19_OUT */},
960 {0x1a8, 0, 0 /* CFG_GPMC_A20_OEN */},
961 {0x1ac, 422, 0 /* CFG_GPMC_A20_OUT */},
962 {0x1b4, 642, 0 /* CFG_GPMC_A21_OEN */},
963 {0x1b8, 0, 0 /* CFG_GPMC_A21_OUT */},
964 {0x1c0, 0, 0 /* CFG_GPMC_A22_OEN */},
965 {0x1c4, 128, 0 /* CFG_GPMC_A22_OUT */},
966 {0x1d0, 0, 0 /* CFG_GPMC_A23_OUT */},
967 {0x1d8, 0, 0 /* CFG_GPMC_A24_OEN */},
968 {0x1dc, 395, 0 /* CFG_GPMC_A24_OUT */},
969 {0x1e4, 0, 0 /* CFG_GPMC_A25_OEN */},
970 {0x1e8, 0, 0 /* CFG_GPMC_A25_OUT */},
971 {0x1f0, 623, 0 /* CFG_GPMC_A26_OEN */},
972 {0x1f4, 0, 0 /* CFG_GPMC_A26_OUT */},
973 {0x1fc, 54, 0 /* CFG_GPMC_A27_OEN */},
974 {0x200, 0, 0 /* CFG_GPMC_A27_OUT */},
975 {0x364, 0, 0 /* CFG_GPMC_CS1_OEN */},
976 {0x368, 0, 0 /* CFG_GPMC_CS1_OUT */},
977};
978
979static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_dra72_conf[] = {
980 {0x18c, 0, 0, /* CFG_GPMC_A19_IN */},
981 {0x1a4, 121, 0, /* CFG_GPMC_A20_IN */},
982 {0x1b0, 0, 0, /* CFG_GPMC_A21_IN */},
983 {0x1bc, 20, 0, /* CFG_GPMC_A22_IN */},
984 {0x1c8, 108, 0, /* CFG_GPMC_A23_IN */},
985 {0x1d4, 31, 0, /* CFG_GPMC_A24_IN */},
986 {0x1e0, 0, 0, /* CFG_GPMC_A25_IN */},
987 {0x1ec, 24, 0, /* CFG_GPMC_A26_IN */},
988 {0x1f8, 0, 0, /* CFG_GPMC_A27_IN */},
989 {0x360, 0, 0, /* CFG_GPMC_CS1_IN */},
990 {0x194, 152, 0, /* CFG_GPMC_A19_OUT */},
991 {0x1ac, 206, 0, /* CFG_GPMC_A20_OUT */},
992 {0x1b8, 78, 0, /* CFG_GPMC_A21_OUT */},
993 {0x1c4, 2, 0, /* CFG_GPMC_A22_OUT */},
994 {0x1d0, 266, 0, /* CFG_GPMC_A23_OUT */},
995 {0x1dc, 0, 0, /* CFG_GPMC_A24_OUT */},
996 {0x1e8, 0, 0, /* CFG_GPMC_A25_OUT */},
997 {0x1f4, 43, 0, /* CFG_GPMC_A26_OUT */},
998 {0x200, 0, 0, /* CFG_GPMC_A27_OUT */},
999 {0x368, 0, 0, /* CFG_GPMC_CS1_OUT */},
1000 {0x190, 0, 0, /* CFG_GPMC_A19_OEN */},
1001 {0x1a8, 0, 0, /* CFG_GPMC_A20_OEN */},
1002 {0x1b4, 0, 0, /* CFG_GPMC_A21_OEN */},
1003 {0x1c0, 0, 0, /* CFG_GPMC_A22_OEN */},
1004 {0x1d8, 0, 0, /* CFG_GPMC_A24_OEN */},
1005 {0x1e4, 0, 0, /* CFG_GPMC_A25_OEN */},
1006 {0x1f0, 0, 0, /* CFG_GPMC_A26_OEN */},
1007 {0x1fc, 0, 0, /* CFG_GPMC_A27_OEN */},
1008 {0x364, 0, 0, /* CFG_GPMC_CS1_OEN */},
1009};
1010
1011static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_dra72_conf[] = {
1012 {0x194, 150 , 95 /* CFG_GPMC_A19_OUT */},
1013 {0x1AC, 250 , 0 /* CFG_GPMC_A20_OUT */},
1014 {0x1B8, 125 , 0 /* CFG_GPMC_A21_OUT */},
1015 {0x1C4, 100 , 0 /* CFG_GPMC_A22_OUT */},
1016 {0x1D0, 870 , 415 /* CFG_GPMC_A23_OUT */},
1017 {0x1DC, 30 , 0 /* CFG_GPMC_A24_OUT */},
1018 {0x1E8, 200 , 0 /* CFG_GPMC_A25_OUT */},
1019 {0x1F4, 200 , 0 /* CFG_GPMC_A26_OUT */},
1020 {0x200, 0 , 0 /* CFG_GPMC_A27_OUT */},
1021 {0x368, 240 , 0 /* CFG_GPMC_CS1_OUT */},
1022 {0x190, 695 , 0 /* CFG_GPMC_A19_OEN */},
1023 {0x1A8, 924 , 0 /* CFG_GPMC_A20_OEN */},
1024 {0x1B4, 719 , 0 /* CFG_GPMC_A21_OEN */},
1025 {0x1C0, 824 , 0 /* CFG_GPMC_A22_OEN */},
1026 {0x1D8, 877 , 0 /* CFG_GPMC_A24_OEN */},
1027 {0x1E4, 446 , 0 /* CFG_GPMC_A25_OEN */},
1028 {0x1F0, 847 , 0 /* CFG_GPMC_A26_OEN */},
1029 {0x1FC, 586 , 0 /* CFG_GPMC_A27_OEN */},
1030 {0x364, 1039 , 0 /* CFG_GPMC_CS1_OEN */},
1031};
1032
1033#define dimof(t) (sizeof(t) / sizeof(t[0]))
1034static struct omap_hsmmc_pinctrl_state hsmmc1_default = {
1035 .padconf = hsmmc1_default_padconf,
1036 .npads = dimof(hsmmc1_default_padconf),
1037 .iodelay = NULL,
1038 .niodelays = 0,
1039};
1040
1041static struct omap_hsmmc_pinctrl_state hsmmc2_default_hs = {
1042 .padconf = mmc2_pins_default_hs,
1043 .npads = dimof(mmc2_pins_default_hs),
1044 .iodelay = NULL,
1045 .niodelays = 0,
1046};
1047
1048static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_1v8_rev11 = {
1049 .padconf = mmc2_pins_ddr_hs200_1_8v,
1050 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1051 .iodelay = mmc2_iodelay_ddr_1_8v_rev11_conf,
1052 .niodelays = dimof(mmc2_iodelay_ddr_1_8v_rev11_conf),
1053};
1054
1055static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_1v8_rev20 = {
1056 .padconf = mmc2_pins_ddr_hs200_1_8v,
1057 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1058 .iodelay = mmc2_iodelay_ddr_1_8v_rev20_conf,
1059 .niodelays = dimof(mmc2_iodelay_ddr_1_8v_rev20_conf),
1060};
1061
1062static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_rev11 = {
1063 .padconf = mmc2_pins_ddr_hs200_1_8v,
1064 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1065 .iodelay = mmc2_iodelay_hs200_1_8v_rev11_conf,
1066 .niodelays = dimof(mmc2_iodelay_hs200_1_8v_rev11_conf),
1067};
1068
1069static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_rev20 = {
1070 .padconf = mmc2_pins_ddr_hs200_1_8v,
1071 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1072 .iodelay = mmc2_iodelay_hs200_1_8v_rev20_conf,
1073 .niodelays = dimof(mmc2_iodelay_hs200_1_8v_rev20_conf),
1074};
1075
1076
1077static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_1v8_dra72 = {
1078 .padconf = mmc2_pins_ddr_hs200_1_8v,
1079 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1080 .iodelay = mmc2_iodelay_ddr_1_8v_dra72_conf,
1081 .niodelays = dimof(mmc2_iodelay_ddr_1_8v_dra72_conf),
1082};
1083
1084static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_dra72 = {
1085 .padconf = mmc2_pins_ddr_hs200_1_8v,
1086 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1087 .iodelay = mmc2_iodelay_hs200_1_8v_dra72_conf,
1088 .niodelays = dimof(mmc2_iodelay_hs200_1_8v_dra72_conf),
1089};
1090#endif
1091
831#endif /* _MUX_DATA_DRA7XX_H_ */ 1092#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 0670b16a2e..82a023190b 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -386,7 +386,7 @@ static int mmc_go_idle(struct mmc *mmc)
386 386
387static int mmc_host_uhs(struct mmc *mmc) 387static int mmc_host_uhs(struct mmc *mmc)
388{ 388{
389 return mmc->cfg->host_caps & 389 return mmc->host_ok_caps &
390 (MMC_MODE_UHS_SDR12 | MMC_MODE_UHS_SDR25 | 390 (MMC_MODE_UHS_SDR12 | MMC_MODE_UHS_SDR25 |
391 MMC_MODE_UHS_SDR50 | MMC_MODE_UHS_SDR104 | 391 MMC_MODE_UHS_SDR50 | MMC_MODE_UHS_SDR104 |
392 MMC_MODE_UHS_DDR50); 392 MMC_MODE_UHS_DDR50);
@@ -663,7 +663,7 @@ static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
663 663
664static void mmc_select_card_type(struct mmc *mmc, char card_type) 664static void mmc_select_card_type(struct mmc *mmc, char card_type)
665{ 665{
666 u32 caps = mmc->cfg->host_caps; 666 u32 caps = mmc->host_ok_caps;
667 uint hs_max_dtr = mmc->tran_speed; 667 uint hs_max_dtr = mmc->tran_speed;
668 668
669 if (caps & MMC_MODE_HS && 669 if (caps & MMC_MODE_HS &&
@@ -1094,7 +1094,7 @@ static int mmc_app_set_bus_width(struct mmc *mmc, int width)
1094 1094
1095static void sd_update_bus_speed_mode(struct mmc *mmc) 1095static void sd_update_bus_speed_mode(struct mmc *mmc)
1096{ 1096{
1097 u32 caps = mmc->cfg->host_caps; 1097 u32 caps = mmc->host_ok_caps;
1098 /* 1098 /*
1099 * If the host doesn't support any of the UHS-I modes, fallback on 1099 * If the host doesn't support any of the UHS-I modes, fallback on
1100 * default speed. 1100 * default speed.
@@ -1238,8 +1238,8 @@ static int mmc_sd_switch_hs(struct mmc *mmc)
1238 * This can avoid furthur problem when the card runs in different 1238 * This can avoid furthur problem when the card runs in different
1239 * mode between the host. 1239 * mode between the host.
1240 */ 1240 */
1241 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && 1241 if (!((mmc->host_ok_caps & MMC_MODE_HS_52MHz) &&
1242 (mmc->cfg->host_caps & MMC_MODE_HS))) 1242 (mmc->host_ok_caps & MMC_MODE_HS)))
1243 return -EINVAL; 1243 return -EINVAL;
1244 1244
1245 if (!(mmc->card_caps & MMC_MODE_HS)) 1245 if (!(mmc->card_caps & MMC_MODE_HS))
@@ -1350,7 +1350,7 @@ retry_scr:
1350 mmc->card_caps |= MMC_MODE_HS; 1350 mmc->card_caps |= MMC_MODE_HS;
1351 1351
1352 /* Restrict card's capabilities by what the host can do */ 1352 /* Restrict card's capabilities by what the host can do */
1353 mmc->card_caps &= mmc->cfg->host_caps; 1353 mmc->card_caps &= mmc->host_ok_caps;
1354 1354
1355 if (mmc->ocr & OCR_S18R) { 1355 if (mmc->ocr & OCR_S18R) {
1356 mmc_sd_init_uhs_card(mmc); 1356 mmc_sd_init_uhs_card(mmc);
@@ -1513,16 +1513,15 @@ static int mmc_select_bus_width(struct mmc *mmc)
1513 MMC_BUS_WIDTH_8, 1513 MMC_BUS_WIDTH_8,
1514 MMC_BUS_WIDTH_4, 1514 MMC_BUS_WIDTH_4,
1515 }; 1515 };
1516 const struct mmc_config *cfg = mmc->cfg;
1517 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1516 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1518 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 1517 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1519 unsigned idx = 0, bus_width = 0; 1518 unsigned idx = 0, bus_width = 0;
1520 int err = 0; 1519 int err = 0;
1521 1520
1522 if (!(cfg->host_caps & (MMC_MODE_8BIT | MMC_MODE_4BIT))) 1521 if (!(mmc->host_ok_caps & (MMC_MODE_8BIT | MMC_MODE_4BIT)))
1523 return 0; 1522 return 0;
1524 1523
1525 idx = (cfg->host_caps & MMC_MODE_8BIT) ? 0 : 1; 1524 idx = (mmc->host_ok_caps & MMC_MODE_8BIT) ? 0 : 1;
1526 1525
1527 err = mmc_send_ext_csd(mmc, ext_csd); 1526 err = mmc_send_ext_csd(mmc, ext_csd);
1528 if (err) 1527 if (err)
@@ -1887,16 +1886,22 @@ static int mmc_startup(struct mmc *mmc)
1887 if (mmc->timing == MMC_TIMING_MMC_HS200) { 1886 if (mmc->timing == MMC_TIMING_MMC_HS200) {
1888 err = mmc->cfg->ops->execute_tuning(mmc, 1887 err = mmc->cfg->ops->execute_tuning(mmc,
1889 MMC_SEND_TUNING_BLOCK_HS200); 1888 MMC_SEND_TUNING_BLOCK_HS200);
1890 if (err) 1889 if (err) {
1891 return err; 1890 printf("Tuning failed, dropping HS200 mode.\n");
1891 mmc->host_ok_caps &= ~MMC_MODE_HS200;
1892 return -EAGAIN;
1893 }
1892 } else if (mmc->timing == MMC_TIMING_MMC_HS) { 1894 } else if (mmc->timing == MMC_TIMING_MMC_HS) {
1893 err = mmc_select_bus_width(mmc); 1895 err = mmc_select_bus_width(mmc);
1894 if (err) 1896 if (err)
1895 return err; 1897 return err;
1896 1898
1897 err = mmc_select_hs_ddr(mmc); 1899 err = mmc_select_hs_ddr(mmc);
1898 if (err) 1900 if (err) {
1899 return err; 1901 printf("dropping DDR52 mode.\n");
1902 mmc->host_ok_caps &= ~MMC_MODE_DDR_52MHz;
1903 return -EAGAIN;
1904 }
1900 } 1905 }
1901 } 1906 }
1902 1907
@@ -2161,19 +2166,26 @@ static int mmc_complete_init(struct mmc *mmc)
2161int mmc_init(struct mmc *mmc) 2166int mmc_init(struct mmc *mmc)
2162{ 2167{
2163 int err = 0; 2168 int err = 0;
2164 unsigned start; 2169 int retries = 0;
2170 __maybe_unused unsigned start;
2165 2171
2166 if (mmc->has_init) 2172 if (mmc->has_init)
2167 return 0; 2173 return 0;
2168 2174
2175 mmc->host_ok_caps = mmc->cfg->host_caps;
2169 start = get_timer(0); 2176 start = get_timer(0);
2170 2177
2171 if (!mmc->init_in_progress) 2178 do {
2172 err = mmc_start_init(mmc); 2179 retries++;
2180 if (!mmc->init_in_progress)
2181 err = mmc_start_init(mmc);
2173 2182
2174 if (!err) 2183 if (!err)
2175 err = mmc_complete_init(mmc); 2184 err = mmc_complete_init(mmc);
2176 debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); 2185 } while (err == -EAGAIN);
2186
2187 debug("%s: %d, time %lu (retries %d)\n", __func__, err,
2188 get_timer(start), retries - 1);
2177 return err; 2189 return err;
2178} 2190}
2179 2191
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 4d4962ac8a..0162be44ad 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -59,13 +59,8 @@ DECLARE_GLOBAL_DATA_PTR;
59#define SYSCTL_SRC (1 << 25) 59#define SYSCTL_SRC (1 << 25)
60#define SYSCTL_SRD (1 << 26) 60#define SYSCTL_SRD (1 << 26)
61 61
62#ifdef CONFIG_IODELAY_RECALIBRATION 62#ifndef CONFIG_OMAP34XX
63struct omap_hsmmc_pinctrl_state { 63#define SUPPORTS_ADMA
64 struct pad_conf_entry *padconf;
65 int npads;
66 struct iodelay_cfg_entry *iodelay;
67 int niodelays;
68};
69#endif 64#endif
70 65
71struct omap_hsmmc_data { 66struct omap_hsmmc_data {
@@ -83,17 +78,22 @@ struct omap_hsmmc_data {
83 int wp_gpio; 78 int wp_gpio;
84#endif 79#endif
85#endif 80#endif
86#ifdef CONFIG_DM_MMC 81
87 uint iov; 82#ifdef SUPPORTS_ADMA
88 uint timing;
89 u8 controller_flags; 83 u8 controller_flags;
90 struct omap_hsmmc_adma_desc *adma_desc_table; 84 struct omap_hsmmc_adma_desc *adma_desc_table;
91 uint desc_slot; 85 uint desc_slot;
92 int node; 86#endif
87 ushort last_cmd;
88 uint iov;
89 uint timing;
93 char *version; 90 char *version;
91
92#ifdef CONFIG_DM_MMC
93 int node;
94 struct udevice *vmmc_supply; 94 struct udevice *vmmc_supply;
95 struct udevice *vmmc_aux_supply; 95 struct udevice *vmmc_aux_supply;
96 ushort last_cmd; 96#endif
97#ifdef CONFIG_IODELAY_RECALIBRATION 97#ifdef CONFIG_IODELAY_RECALIBRATION
98 struct omap_hsmmc_pinctrl_state *default_pinctrl_state; 98 struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
99 struct omap_hsmmc_pinctrl_state *hs_pinctrl_state; 99 struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
@@ -105,11 +105,10 @@ struct omap_hsmmc_data {
105 struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state; 105 struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
106 struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state; 106 struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
107#endif 107#endif
108#endif
109 uint signal_voltage; 108 uint signal_voltage;
110}; 109};
111 110
112#ifdef CONFIG_DM_MMC 111#ifdef SUPPORTS_ADMA
113struct omap_hsmmc_adma_desc { 112struct omap_hsmmc_adma_desc {
114 u8 attr; 113 u8 attr;
115 u8 reserved; 114 u8 reserved;
@@ -245,8 +244,51 @@ void mmc_init_stream(struct hsmmc *mmc_base)
245 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); 244 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
246} 245}
247 246
248#ifdef CONFIG_DM_MMC
249#ifdef CONFIG_IODELAY_RECALIBRATION 247#ifdef CONFIG_IODELAY_RECALIBRATION
248#ifdef DEBUG
249static inline void show_mmc_timing(struct mmc *mmc)
250{
251 const char *str;
252 switch (mmc->timing) {
253 case MMC_TIMING_MMC_HS200:
254 str = "HS200";
255 break;
256 case MMC_TIMING_UHS_SDR104:
257 str = "SDR104";
258 break;
259 case MMC_TIMING_UHS_DDR50:
260 str = "DDR50";
261 break;
262 case MMC_TIMING_UHS_SDR50:
263 str = "SDR50";
264 break;
265 case MMC_TIMING_UHS_SDR25:
266 str = "SDR25";
267 break;
268 case MMC_TIMING_UHS_SDR12:
269 str = "SDR12";
270 break;
271 case MMC_TIMING_SD_HS:
272 str = "HS(sd)";
273 break;
274 case MMC_TIMING_MMC_HS:
275 str = "HS(mmc)";
276 break;
277 case MMC_TIMING_MMC_DDR52:
278 str = "DDR52";
279 break;
280 default:
281 str = "std";
282 break;
283 }
284 printf("mmc %d mode %s\n", mmc->block_dev.devnum + 1, str);
285}
286#else
287static inline void show_mmc_timing(struct mmc *mmc)
288{
289}
290#endif
291
250static void omap_hsmmc_set_timing(struct mmc *mmc) 292static void omap_hsmmc_set_timing(struct mmc *mmc)
251{ 293{
252 u32 val; 294 u32 val;
@@ -317,9 +359,9 @@ static void omap_hsmmc_set_timing(struct mmc *mmc)
317 359
318 omap_hsmmc_start_clock(mmc_base); 360 omap_hsmmc_start_clock(mmc_base);
319 priv->timing = mmc->timing; 361 priv->timing = mmc->timing;
362 show_mmc_timing(mmc);
320} 363}
321#endif 364#endif
322#endif
323 365
324static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage) 366static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
325{ 367{
@@ -346,7 +388,6 @@ static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
346 writel(val, &mmc_base->hctl); 388 writel(val, &mmc_base->hctl);
347} 389}
348 390
349#if defined(CONFIG_DM_MMC)
350static int omap_hsmmc_card_busy_low(struct mmc *mmc) 391static int omap_hsmmc_card_busy_low(struct mmc *mmc)
351{ 392{
352 u32 val; 393 u32 val;
@@ -454,7 +495,6 @@ static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int uV)
454 return 0; 495 return 0;
455} 496}
456#endif 497#endif
457#endif
458 498
459static int omap_hsmmc_set_signal_voltage(struct mmc *mmc) 499static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
460{ 500{
@@ -480,7 +520,9 @@ static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
480#if CONFIG_IS_ENABLED(DM_REGULATOR) && defined(CONFIG_DM_MMC) 520#if CONFIG_IS_ENABLED(DM_REGULATOR) && defined(CONFIG_DM_MMC)
481 return omap_hsmmc_set_io_regulator(mmc, 3000000); 521 return omap_hsmmc_set_io_regulator(mmc, 3000000);
482#else 522#else
483 vmmc_pbias_config(LDO_VOLT_3V0); 523 /* PBIAS config needed for MMC1 only */
524 if ((uint32_t) mmc_base == OMAP_HSMMC1_BASE)
525 vmmc_pbias_config(LDO_VOLT_3V0);
484#endif 526#endif
485#endif 527#endif
486 } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 528 } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
@@ -498,7 +540,9 @@ static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
498#if CONFIG_IS_ENABLED(DM_REGULATOR) && defined(CONFIG_DM_MMC) 540#if CONFIG_IS_ENABLED(DM_REGULATOR) && defined(CONFIG_DM_MMC)
499 return omap_hsmmc_set_io_regulator(mmc, 1800000); 541 return omap_hsmmc_set_io_regulator(mmc, 1800000);
500#else 542#else
501 vmmc_pbias_config(LDO_VOLT_1V8); 543 /* PBIAS config needed for MMC1 only */
544 if ((uint32_t) mmc_base == OMAP_HSMMC1_BASE)
545 vmmc_pbias_config(LDO_VOLT_1V8);
502#endif 546#endif
503#endif 547#endif
504 } else { 548 } else {
@@ -537,6 +581,7 @@ static void omap_hsmmc_set_capabilities(struct mmc *mmc)
537 581
538 writel(val, &mmc_base->capa); 582 writel(val, &mmc_base->capa);
539} 583}
584#endif
540 585
541static void omap_hsmmc_disable_tuning(struct mmc *mmc) 586static void omap_hsmmc_disable_tuning(struct mmc *mmc)
542{ 587{
@@ -670,7 +715,6 @@ static int omap_hsmmc_set_vdd(struct mmc *mmc, int enable)
670 return 0; 715 return 0;
671} 716}
672#endif 717#endif
673#endif
674 718
675static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd) 719static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
676{ 720{
@@ -698,11 +742,9 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)
698 unsigned int reg_val; 742 unsigned int reg_val;
699 unsigned int dsor; 743 unsigned int dsor;
700 ulong start; 744 ulong start;
701#ifdef CONFIG_DM_MMC
702 struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv; 745 struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv;
703#endif
704 746
705 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr; 747 mmc_base = priv->base_addr;
706 mmc_board_init(mmc); 748 mmc_board_init(mmc);
707 749
708 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, 750 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
@@ -724,12 +766,15 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)
724 } 766 }
725 } 767 }
726 768
727#ifdef CONFIG_DM_MMC 769#ifdef SUPPORTS_ADMA
728 omap_hsmmc_set_capabilities(mmc);
729 omap_hsmmc_conf_bus_power(mmc, priv->iov);
730 reg_val = readl(&mmc_base->hl_hwinfo); 770 reg_val = readl(&mmc_base->hl_hwinfo);
731 if (reg_val & MADMA_EN) 771 if (reg_val & MADMA_EN)
732 priv->controller_flags |= OMAP_HSMMC_USE_ADMA; 772 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
773#endif
774
775#ifdef CONFIG_DM_MMC
776 omap_hsmmc_set_capabilities(mmc);
777 omap_hsmmc_conf_bus_power(mmc, priv->iov);
733#else 778#else
734 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); 779 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
735 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, 780 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
@@ -814,7 +859,7 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
814 } 859 }
815} 860}
816 861
817#ifdef CONFIG_DM_MMC 862#ifdef SUPPORTS_ADMA
818static int omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end) 863static int omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
819{ 864{
820 struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv; 865 struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv;
@@ -931,7 +976,7 @@ static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
931 struct hsmmc *mmc_base; 976 struct hsmmc *mmc_base;
932 unsigned int flags, mmc_stat; 977 unsigned int flags, mmc_stat;
933 ulong start; 978 ulong start;
934#ifdef CONFIG_DM_MMC 979#ifdef SUPPORTS_ADMA
935 struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv; 980 struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv;
936 priv->last_cmd = cmd->cmdidx; 981 priv->last_cmd = cmd->cmdidx;
937#endif 982#endif
@@ -1010,7 +1055,7 @@ static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1010 else 1055 else
1011 flags |= (DP_DATA | DDIR_WRITE); 1056 flags |= (DP_DATA | DDIR_WRITE);
1012 1057
1013#ifdef CONFIG_DM_MMC 1058#ifdef SUPPORTS_ADMA
1014 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && 1059 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1015 cmd->cmdidx != MMC_SEND_TUNING_BLOCK_HS200) { 1060 cmd->cmdidx != MMC_SEND_TUNING_BLOCK_HS200) {
1016 omap_hsmmc_prepare_data(mmc, data); 1061 omap_hsmmc_prepare_data(mmc, data);
@@ -1055,7 +1100,7 @@ static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1055 } 1100 }
1056 } 1101 }
1057 1102
1058#ifdef CONFIG_DM_MMC 1103#ifdef SUPPORTS_ADMA
1059 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data && 1104 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1060 cmd->cmdidx != MMC_SEND_TUNING_BLOCK_HS200) { 1105 cmd->cmdidx != MMC_SEND_TUNING_BLOCK_HS200) {
1061 if (mmc_stat & IE_ADMAE) { 1106 if (mmc_stat & IE_ADMAE) {
@@ -1290,7 +1335,7 @@ static int omap_hsmmc_set_ios(struct mmc *mmc)
1290 else 1335 else
1291 omap_hsmmc_start_clock(mmc_base); 1336 omap_hsmmc_start_clock(mmc_base);
1292 1337
1293#if defined(CONFIG_DM_MMC) && defined(CONFIG_IODELAY_RECALIBRATION) 1338#if defined(CONFIG_IODELAY_RECALIBRATION)
1294 if (priv_data->timing != mmc->timing) 1339 if (priv_data->timing != mmc->timing)
1295 omap_hsmmc_set_timing(mmc); 1340 omap_hsmmc_set_timing(mmc);
1296#endif 1341#endif
@@ -1367,104 +1412,35 @@ static const struct mmc_ops omap_hsmmc_ops = {
1367 .getcd = omap_hsmmc_getcd, 1412 .getcd = omap_hsmmc_getcd,
1368 .getwp = omap_hsmmc_getwp, 1413 .getwp = omap_hsmmc_getwp,
1369#endif 1414#endif
1370#ifdef CONFIG_DM_MMC
1371 .execute_tuning = omap_hsmmc_execute_tuning, 1415 .execute_tuning = omap_hsmmc_execute_tuning,
1372 .card_busy = omap_hsmmc_card_busy, 1416 .card_busy = omap_hsmmc_card_busy,
1373#if CONFIG_IS_ENABLED(DM_REGULATOR) && defined(CONFIG_DM_MMC) 1417#if CONFIG_IS_ENABLED(DM_REGULATOR) && defined(CONFIG_DM_MMC)
1374 .set_vdd = omap_hsmmc_set_vdd, 1418 .set_vdd = omap_hsmmc_set_vdd,
1375#endif 1419#endif
1376#endif
1377}; 1420};
1378 1421
1379#ifndef CONFIG_DM_MMC 1422#ifdef CONFIG_IODELAY_RECALIBRATION
1380int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, 1423#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC)
1381 int wp_gpio) 1424__weak struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
1425 (struct hsmmc *base, const char *mode)
1382{ 1426{
1383 struct mmc *mmc; 1427 static struct omap_hsmmc_pinctrl_state empty = {
1384 struct omap_hsmmc_data *priv_data; 1428 .padconf = NULL,
1385 struct mmc_config *cfg; 1429 .npads = 0,
1386 uint host_caps_val; 1430 .iodelay = NULL,
1387 1431 .niodelays = 0,
1388 priv_data = malloc(sizeof(*priv_data)); 1432 };
1389 if (priv_data == NULL) 1433 return &empty;
1390 return -1; 1434}
1391
1392 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1393
1394 switch (dev_index) {
1395 case 0:
1396 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1397 break;
1398#ifdef OMAP_HSMMC2_BASE
1399 case 1:
1400 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1401#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1402 defined(CONFIG_DRA7XX) || \
1403 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1404 defined(CONFIG_HSMMC2_8BIT)
1405 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1406 host_caps_val |= MMC_MODE_8BIT;
1407#endif
1408 break;
1409#endif
1410#ifdef OMAP_HSMMC3_BASE
1411 case 2:
1412 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1413#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1414 /* Enable 8-bit interface for eMMC on DRA7XX */
1415 host_caps_val |= MMC_MODE_8BIT;
1416#endif
1417 break;
1418#endif
1419 default:
1420 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1421 return 1;
1422 }
1423#ifdef OMAP_HSMMC_USE_GPIO
1424 /* on error gpio values are set to -1, which is what we want */
1425 priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1426 priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1427#endif
1428
1429 cfg = &priv_data->cfg;
1430
1431 cfg->name = "OMAP SD/MMC";
1432 cfg->ops = &omap_hsmmc_ops;
1433
1434 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1435 cfg->host_caps = host_caps_val & ~host_caps_mask;
1436
1437 cfg->f_min = 400000;
1438
1439 if (f_max != 0)
1440 cfg->f_max = f_max;
1441 else {
1442 if (cfg->host_caps & MMC_MODE_HS) {
1443 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1444 cfg->f_max = 52000000;
1445 else
1446 cfg->f_max = 26000000;
1447 } else
1448 cfg->f_max = 20000000;
1449 }
1450
1451 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1452 1435
1453#if defined(CONFIG_OMAP34XX) 1436static struct omap_hsmmc_pinctrl_state *
1454 /* 1437omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1455 * Silicon revs 2.1 and older do not support multiblock transfers. 1438{
1456 */ 1439 struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv;
1457 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1458 cfg->b_max = 1;
1459#endif
1460 mmc = mmc_create(cfg, priv_data);
1461 if (mmc == NULL)
1462 return -1;
1463 1440
1464 return 0; 1441 return platform_fixup_get_pinctrl_by_mode(priv->base_addr, mode);
1465} 1442}
1466#else 1443#else
1467#ifdef CONFIG_IODELAY_RECALIBRATION
1468static struct pad_conf_entry * 1444static struct pad_conf_entry *
1469omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count) 1445omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1470{ 1446{
@@ -1708,6 +1684,7 @@ err_pinctrl_state:
1708 kfree(pinctrl_state); 1684 kfree(pinctrl_state);
1709 return 0; 1685 return 0;
1710} 1686}
1687#endif
1711 1688
1712#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode) \ 1689#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode) \
1713 do { \ 1690 do { \
@@ -1761,6 +1738,133 @@ static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1761} 1738}
1762#endif 1739#endif
1763 1740
1741__weak int platform_fixup_disable_uhs_mode(void)
1742{
1743 return 0;
1744}
1745
1746static int omap_hsmmc_platform_fixup(struct mmc *mmc)
1747{
1748 struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv;
1749 struct mmc_config *cfg = &priv->cfg;
1750
1751 priv->version = NULL;
1752
1753 if (platform_fixup_disable_uhs_mode()) {
1754 priv->version = "rev11";
1755 cfg->host_caps &= ~(MMC_MODE_HS200 | MMC_MODE_UHS_SDR104
1756 | MMC_MODE_UHS_SDR50);
1757 }
1758
1759 return 0;
1760}
1761
1762#ifndef CONFIG_DM_MMC
1763int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1764 int wp_gpio)
1765{
1766 struct mmc *mmc;
1767 struct omap_hsmmc_data *priv_data;
1768 struct mmc_config *cfg;
1769 uint host_caps_val;
1770#ifdef CONFIG_IODELAY_RECALIBRATION
1771 int ret;
1772#endif
1773
1774 priv_data = malloc(sizeof(*priv_data));
1775 if (priv_data == NULL)
1776 return -1;
1777
1778 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1779#if defined(CONFIG_OMAP54XX)
1780 host_caps_val |= MMC_MODE_DDR_52MHz | MMC_MODE_HS200;
1781 priv_data->controller_flags |= OMAP_HSMMC_REQUIRE_IODELAY;
1782#endif
1783 switch (dev_index) {
1784 case 0:
1785 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1786 break;
1787#ifdef OMAP_HSMMC2_BASE
1788 case 1:
1789 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1790#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1791 defined(CONFIG_DRA7XX) || \
1792 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1793 defined(CONFIG_HSMMC2_8BIT)
1794 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1795 host_caps_val |= MMC_MODE_8BIT;
1796#endif
1797 break;
1798#endif
1799#ifdef OMAP_HSMMC3_BASE
1800 case 2:
1801 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1802#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1803 /* Enable 8-bit interface for eMMC on DRA7XX */
1804 host_caps_val |= MMC_MODE_8BIT;
1805#endif
1806 break;
1807#endif
1808 default:
1809 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1810 return 1;
1811 }
1812#ifdef OMAP_HSMMC_USE_GPIO
1813 /* on error gpio values are set to -1, which is what we want */
1814 priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1815 priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1816#endif
1817
1818 cfg = &priv_data->cfg;
1819
1820 cfg->name = "OMAP SD/MMC";
1821 cfg->ops = &omap_hsmmc_ops;
1822
1823 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1824 cfg->host_caps = host_caps_val & ~host_caps_mask;
1825
1826
1827 cfg->f_min = 400000;
1828
1829 if (f_max != 0) {
1830 cfg->f_max = f_max;
1831 } else {
1832 if (cfg->host_caps & MMC_MODE_HS200)
1833 cfg->f_max = 200000000;
1834 else if (cfg->host_caps & MMC_MODE_DDR_52MHz)
1835 cfg->f_max = 52000000;
1836 else if (cfg->host_caps & MMC_MODE_HS_52MHz)
1837 cfg->f_max = 52000000;
1838 else if (cfg->host_caps & MMC_MODE_HS)
1839 cfg->f_max = 26000000;
1840 else
1841 cfg->f_max = 20000000;
1842 }
1843
1844 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1845
1846#if defined(CONFIG_OMAP34XX)
1847 /*
1848 * Silicon revs 2.1 and older do not support multiblock transfers.
1849 */
1850 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1851 cfg->b_max = 1;
1852#endif
1853 mmc = mmc_create(cfg, priv_data);
1854 if (mmc == NULL)
1855 return -1;
1856
1857 omap_hsmmc_platform_fixup(mmc);
1858
1859#ifdef CONFIG_IODELAY_RECALIBRATION
1860 ret = omap_hsmmc_get_pinctrl_state(mmc);
1861 if (ret < 0)
1862 return ret;
1863#endif
1864
1865 return 0;
1866}
1867#else
1764static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) 1868static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1765{ 1869{
1766 struct omap_hsmmc_data *priv = dev_get_priv(dev); 1870 struct omap_hsmmc_data *priv = dev_get_priv(dev);
@@ -1793,27 +1897,6 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1793 return 0; 1897 return 0;
1794} 1898}
1795 1899
1796__weak int platform_fixup_disable_uhs_mode(void)
1797{
1798 return 0;
1799}
1800
1801static int omap_hsmmc_platform_fixup(struct mmc *mmc)
1802{
1803 struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv;
1804 struct mmc_config *cfg = &priv->cfg;
1805
1806 priv->version = NULL;
1807
1808 if (platform_fixup_disable_uhs_mode()) {
1809 priv->version = "rev11";
1810 cfg->host_caps &= ~(MMC_MODE_HS200 | MMC_MODE_UHS_SDR104
1811 | MMC_MODE_UHS_SDR50);
1812 }
1813
1814 return 0;
1815}
1816
1817static int omap_hsmmc_probe(struct udevice *dev) 1900static int omap_hsmmc_probe(struct udevice *dev)
1818{ 1901{
1819 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 1902 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
diff --git a/include/mmc.h b/include/mmc.h
index 8cdad5a800..c7aeb74b49 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -450,6 +450,7 @@ struct mmc {
450 struct blk_desc block_dev; 450 struct blk_desc block_dev;
451 char op_cond_pending; /* 1 if we are waiting on an op_cond command */ 451 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
452 char init_in_progress; /* 1 if we have done mmc_start_init() */ 452 char init_in_progress; /* 1 if we have done mmc_start_init() */
453 uint host_ok_caps; /* host caps that are not yet proven wrong */
453 char preinit; /* start init as early as possible */ 454 char preinit; /* start init as early as possible */
454 int ddr_mode; 455 int ddr_mode;
455 unsigned int sd_bus_speed; 456 unsigned int sd_bus_speed;