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authorPraneeth Bajjuri2017-08-28 18:05:10 -0500
committerPraneeth Bajjuri2017-08-28 18:05:10 -0500
commit897c50416cb47553fd149ae95ede41149ae8fbaa (patch)
tree862d462158291cbd41102d541554304ed42a4eaa
parent28c2b55c045daa86413fe9fa73299b1d47564615 (diff)
parent50becb1a9d088359a55d6068a47ed3fc8605253c (diff)
downloadu-boot-6AM.1.3-rvc-video-j6e-aug.tar.gz
u-boot-6AM.1.3-rvc-video-j6e-aug.tar.xz
u-boot-6AM.1.3-rvc-video-j6e-aug.zip
Merge branch 'p-ti-u-boot-2016.05' of git://git.omapzoom.org/repo/u-boot into 6AM.1.3-rvc-video6AM.1.3-rvc-video-j6e-aug6AM.1.3-rvc-video
* 'p-ti-u-boot-2016.05' of git://git.omapzoom.org/repo/u-boot: (62 commits) am57x: android: add vendor partition arm: omap: enable high speed mode support in SPL for the eMMC on DRA76x ARM: dts: dra76-evm: add higher speed MMC/SD modes ARM: dts: dra76-evm: shift to using common IOdelay data ARM: dts: dra76x: create a common file with MMC/SD IOdelay data ARM: DRA72x: Add support for detection of DRA71x SR 2.1 dra7xx: android: add vendor partition fastboot: sparse: remove session-id logic ARM: dts: dra76-evm: Add initial support ARM: dts: dra7-evm: sync DT with Linux configs: ti_omap5_common: Select dtb name for dra76 board: ti: dra76-evm: Add support for powering on mmc ldo board: ti: dra76-evm: Add the pinmux data board: ti: dra76-evm: Add DDR data board: ti: dra76-evm: Add the pmic data board: ti: dra76-evm: Add epprom support arm: dra76: Add support for ES1.0 detection configs: dra7xx: Enable LP87565 related configs power: regulator: palmas: Add smps12 dual regulator for tps65917 power: regulator: lp87565: add regulator support ... Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c2
-rw-r--r--arch/arm/cpu/armv7/omap-common/boot-common.c16
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c105
-rw-r--r--arch/arm/cpu/armv7/omap5/hwinit.c22
-rw-r--r--arch/arm/cpu/armv7/omap5/sdram.c4
-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/dra7-evm-common.dtsi190
-rw-r--r--arch/arm/dts/dra7-evm.dts473
-rw-r--r--arch/arm/dts/dra7.dtsi2
-rw-r--r--arch/arm/dts/dra76-evm.dts388
-rw-r--r--arch/arm/dts/dra76x-mmc-iodelay.dtsi244
-rw-r--r--arch/arm/dts/dra76x.dtsi27
-rw-r--r--arch/arm/include/asm/arch-am33xx/mmc_host_def.h4
-rw-r--r--arch/arm/include/asm/arch-omap4/mmc_host_def.h6
-rw-r--r--arch/arm/include/asm/arch-omap5/clock.h9
-rw-r--r--arch/arm/include/asm/arch-omap5/mmc_host_def.h6
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h2
-rw-r--r--arch/arm/include/asm/arch-omap5/sys_proto.h7
-rw-r--r--arch/arm/include/asm/omap_common.h10
-rw-r--r--arch/arm/include/asm/omap_mmc.h6
-rw-r--r--arch/arm/mach-keystone/include/mach/mmc_host_def.h4
-rw-r--r--board/BuR/common/common.c2
-rw-r--r--board/amazon/kc1/kc1.c2
-rw-r--r--board/compulab/cm_t35/cm_t35.c2
-rw-r--r--board/compulab/cm_t3517/cm_t3517.c2
-rw-r--r--board/compulab/cm_t54/cm_t54.c2
-rw-r--r--board/corscience/tricorder/tricorder.c2
-rw-r--r--board/gumstix/duovero/duovero.c4
-rw-r--r--board/htkw/mcx/mcx.c2
-rw-r--r--board/isee/igep00x0/igep00x0.c2
-rw-r--r--board/lg/sniper/sniper.c2
-rw-r--r--board/logicpd/am3517evm/am3517evm.c2
-rw-r--r--board/logicpd/omap3som/omap3logic.c2
-rw-r--r--board/quipos/cairo/cairo.c2
-rw-r--r--board/technexion/tao3530/tao3530.c2
-rw-r--r--board/technexion/twister/twister.c3
-rw-r--r--board/teejet/mt_ventoux/mt_ventoux.c3
-rw-r--r--board/ti/am3517crane/am3517crane.c2
-rw-r--r--board/ti/am57xx/board.c63
-rw-r--r--board/ti/am57xx/mux_data.h132
-rw-r--r--board/ti/beagle/beagle.c2
-rw-r--r--board/ti/dra7xx/evm.c263
-rw-r--r--board/ti/dra7xx/lateattach.c5
-rw-r--r--board/ti/dra7xx/mux_data.h604
-rw-r--r--board/ti/evm/evm.c2
-rw-r--r--board/ti/ks2_evm/board_k2g.c2
-rw-r--r--board/ti/omap5_uevm/evm.c2
-rw-r--r--board/ti/panda/panda.c4
-rw-r--r--board/ti/sdp4430/sdp.c4
-rw-r--r--board/ti/ti814x/evm.c2
-rw-r--r--board/timll/devkit8000/devkit8000.c2
-rw-r--r--common/env_ext4.c4
-rw-r--r--common/env_fat.c4
-rw-r--r--common/env_mmc.c20
-rw-r--r--common/env_sf.c8
-rw-r--r--common/fb_mmc.c16
-rw-r--r--common/fb_nand.c4
-rw-r--r--common/image-sparse.c21
-rwxr-xr-xcommon/spl/spl.c2
-rw-r--r--configs/dra7xx_evm_defconfig6
-rw-r--r--configs/dra7xx_hs_evm_defconfig6
-rw-r--r--drivers/mmc/mmc.c50
-rw-r--r--drivers/mmc/omap_hsmmc.c436
-rw-r--r--drivers/power/palmas.c6
-rw-r--r--drivers/power/pmic/Kconfig7
-rw-r--r--drivers/power/pmic/Makefile1
-rw-r--r--drivers/power/pmic/lp87565.c89
-rw-r--r--drivers/power/regulator/Kconfig10
-rw-r--r--drivers/power/regulator/Makefile1
-rw-r--r--drivers/power/regulator/lp87565_regulator.c199
-rw-r--r--drivers/power/regulator/palmas_regulator.c6
-rw-r--r--drivers/spi/ti_qspi.c16
-rw-r--r--drivers/usb/gadget/f_fastboot.c16
-rw-r--r--fs/fat/fat.c2
-rw-r--r--fs/fat/fat_write.c2
-rw-r--r--include/configs/am335x_evm.h31
-rw-r--r--include/configs/am43xx_evm.h35
-rw-r--r--include/configs/am57xx_evm.h52
-rw-r--r--include/configs/dra7xx_evm.h59
-rw-r--r--include/configs/omap5_uevm.h39
-rw-r--r--include/configs/ti_armv7_common.h11
-rw-r--r--include/configs/ti_omap5_common.h2
-rw-r--r--include/environment/ti/dfu.h77
-rw-r--r--include/fb_mmc.h5
-rw-r--r--include/fb_nand.h5
-rw-r--r--include/image-sparse.h2
-rw-r--r--include/libfdt.h21
-rw-r--r--include/mmc.h1
-rw-r--r--include/palmas.h6
-rw-r--r--include/power/lp87565.h12
-rw-r--r--lib/libfdt/fdt_addresses.c21
91 files changed, 2981 insertions, 984 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 4618470bad..8cc4e65809 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -105,7 +105,7 @@ static const struct gpio_bank gpio_bank_am33xx[] = {
105const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; 105const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
106#endif 106#endif
107 107
108#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) 108#if defined(CONFIG_OMAP_HSMMC)
109int cpu_mmc_init(bd_t *bis) 109int cpu_mmc_init(bd_t *bis)
110{ 110{
111 int ret; 111 int ret;
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 4e50a68b58..b308859104 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -209,22 +209,6 @@ void spl_board_init(void)
209#endif 209#endif
210} 210}
211 211
212int board_mmc_init(bd_t *bis)
213{
214 switch (spl_boot_device()) {
215 case BOOT_DEVICE_MMC1:
216 omap_mmc_init(0, 0, 0, -1, -1);
217 break;
218 case BOOT_DEVICE_MMC2:
219 case BOOT_DEVICE_MMC2_2:
220 case BOOT_DEVICE_SPI:
221 omap_mmc_init(0, 0, 0, -1, -1);
222 omap_mmc_init(1, 0, 0, -1, -1);
223 break;
224 }
225 return 0;
226}
227
228void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) 212void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
229{ 213{
230 typedef void __noreturn (*image_entry_noargs_t)(u32 *); 214 typedef void __noreturn (*image_entry_noargs_t)(u32 *);
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 0716f51931..06b0414469 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -28,17 +28,6 @@ struct vcores_data const **omap_vcores =
28struct omap_sys_ctrl_regs const **ctrl = 28struct omap_sys_ctrl_regs const **ctrl =
29 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; 29 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
30 30
31/* OPP HIGH FREQUENCY for ES2.0 */
32static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
33 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
34 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
35 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
36 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
37 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
38 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
39 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
40};
41
42/* OPP NOM FREQUENCY for ES1.0 */ 31/* OPP NOM FREQUENCY for ES1.0 */
43static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { 32static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
44 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 33 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
@@ -50,28 +39,6 @@ static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
50 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 39 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
51}; 40};
52 41
53/* OPP LOW FREQUENCY for ES1.0 */
54static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
55 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
56 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
57 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
58 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
59 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
60 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
61 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
62};
63
64/* OPP LOW FREQUENCY for ES2.0 */
65static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
66 {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
67 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
68 {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
69 {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
70 {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
71 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
72 {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
73};
74
75/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ 42/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
76static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { 43static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
77 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 44 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
@@ -116,28 +83,6 @@ static const struct dpll_params
116 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */ 83 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
117}; 84};
118 85
119static const struct dpll_params
120 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
121 {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
123 {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
124 {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
125 {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
126 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
127 {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
128};
129
130static const struct dpll_params
131 core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
132 {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
133 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
134 {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
135 {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
136 {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
137 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
138 {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
139};
140
141static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { 86static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
142 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ 87 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
143 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 88 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
@@ -168,6 +113,16 @@ static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
168 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ 113 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
169}; 114};
170 115
116static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = {
117 {32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 12 MHz */
118 {96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 20 MHz */
119 {160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 16.8 MHz */
120 {20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 19.2 MHz */
121 {192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 26 MHz */
122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
123 {10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 38.4 MHz */
124};
125
171static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { 126static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
172 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 127 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
173 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 128 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
@@ -188,6 +143,7 @@ static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
188 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 143 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
189}; 144};
190 145
146#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
191/* ABE M & N values with sys_clk as source */ 147/* ABE M & N values with sys_clk as source */
192static const struct dpll_params 148static const struct dpll_params
193 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { 149 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
@@ -199,11 +155,14 @@ static const struct dpll_params
199 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 155 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
200 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 156 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
201}; 157};
158#endif
202 159
160#ifndef CONFIG_SYS_OMAP_ABE_SYSCK
203/* ABE M & N values with 32K clock as source */ 161/* ABE M & N values with 32K clock as source */
204static const struct dpll_params abe_dpll_params_32k_196608khz = { 162static const struct dpll_params abe_dpll_params_32k_196608khz = {
205 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 163 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
206}; 164};
165#endif
207 166
208/* ABE M & N values with sysclk2(22.5792 MHz) as input */ 167/* ABE M & N values with sysclk2(22.5792 MHz) as input */
209static const struct dpll_params 168static const struct dpll_params
@@ -285,6 +244,17 @@ struct dplls omap5_dplls_es2 = {
285 .ddr = NULL 244 .ddr = NULL
286}; 245};
287 246
247struct dplls dra76x_dplls = {
248 .mpu = mpu_dpll_params_1ghz,
249 .core = core_dpll_params_2128mhz_dra7xx,
250 .per = per_dpll_params_768mhz_dra76x,
251 .abe = abe_dpll_params_sysclk2_361267khz,
252 .iva = iva_dpll_params_2330mhz_dra7xx,
253 .usb = usb_dpll_params_1920mhz,
254 .ddr = ddr_dpll_params_2664mhz,
255 .gmac = gmac_dpll_params_2000mhz,
256};
257
288struct dplls dra7xx_dplls = { 258struct dplls dra7xx_dplls = {
289 .mpu = mpu_dpll_params_1ghz, 259 .mpu = mpu_dpll_params_1ghz,
290 .core = core_dpll_params_2128mhz_dra7xx, 260 .core = core_dpll_params_2128mhz_dra7xx,
@@ -336,6 +306,22 @@ struct pmic_data tps659038 = {
336 .gpio_en = 0, 306 .gpio_en = 0,
337}; 307};
338 308
309/* The LP87565*/
310struct pmic_data lp87565 = {
311 .base_offset = LP873X_BUCK_BASE_VOLT_UV,
312 .step = 5000, /* 5 mV represented in uV */
313 /*
314 * Offset codes 0 - 0x13 Invalid.
315 * Offset codes 0x14 0x17 give 10mV steps
316 * Offset codes 0x17 through 0x9D give 5mV steps
317 * So let us start with our operating range from .73V
318 */
319 .start_code = 0x17,
320 .i2c_slave_addr = 0x60,
321 .pmic_bus_init = gpi2c_init,
322 .pmic_write = palmas_i2c_write_u8,
323};
324
339/* The LP8732 and LP8733 are software-compatible, use common struct */ 325/* The LP8732 and LP8733 are software-compatible, use common struct */
340struct pmic_data lp8733 = { 326struct pmic_data lp8733 = {
341 .base_offset = LP873X_BUCK_BASE_VOLT_UV, 327 .base_offset = LP873X_BUCK_BASE_VOLT_UV,
@@ -753,6 +739,12 @@ void __weak hw_data_init(void)
753 *ctrl = &omap5_ctrl; 739 *ctrl = &omap5_ctrl;
754 break; 740 break;
755 741
742 case DRA762_ES1_0:
743 *prcm = &dra7xx_prcm;
744 *dplls_data = &dra76x_dplls;
745 *ctrl = &dra7xx_ctrl;
746 break;
747
756 case DRA752_ES1_0: 748 case DRA752_ES1_0:
757 case DRA752_ES1_1: 749 case DRA752_ES1_1:
758 case DRA752_ES2_0: 750 case DRA752_ES2_0:
@@ -763,6 +755,7 @@ void __weak hw_data_init(void)
763 755
764 case DRA722_ES1_0: 756 case DRA722_ES1_0:
765 case DRA722_ES2_0: 757 case DRA722_ES2_0:
758 case DRA722_ES2_1:
766 *prcm = &dra7xx_prcm; 759 *prcm = &dra7xx_prcm;
767 *dplls_data = &dra72x_dplls; 760 *dplls_data = &dra72x_dplls;
768 *ctrl = &dra7xx_ctrl; 761 *ctrl = &dra7xx_ctrl;
@@ -791,12 +784,14 @@ void get_ioregs(const struct ctrl_ioregs **regs)
791 case DRA752_ES1_0: 784 case DRA752_ES1_0:
792 case DRA752_ES1_1: 785 case DRA752_ES1_1:
793 case DRA752_ES2_0: 786 case DRA752_ES2_0:
787 case DRA762_ES1_0:
794 *regs = &ioregs_dra7xx_es1; 788 *regs = &ioregs_dra7xx_es1;
795 break; 789 break;
796 case DRA722_ES1_0: 790 case DRA722_ES1_0:
797 *regs = &ioregs_dra72x_es1; 791 *regs = &ioregs_dra72x_es1;
798 break; 792 break;
799 case DRA722_ES2_0: 793 case DRA722_ES2_0:
794 case DRA722_ES2_1:
800 *regs = &ioregs_dra72x_es2; 795 *regs = &ioregs_dra72x_es2;
801 break; 796 break;
802 797
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 839d79d102..03e50ba891 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -362,6 +362,9 @@ void init_omap_revision(void)
362 case OMAP5432_CONTROL_ID_CODE_ES2_0: 362 case OMAP5432_CONTROL_ID_CODE_ES2_0:
363 *omap_si_rev = OMAP5432_ES2_0; 363 *omap_si_rev = OMAP5432_ES2_0;
364 break; 364 break;
365 case DRA762_CONTROL_ID_CODE_ES1_0:
366 *omap_si_rev = DRA762_ES1_0;
367 break;
365 case DRA752_CONTROL_ID_CODE_ES1_0: 368 case DRA752_CONTROL_ID_CODE_ES1_0:
366 *omap_si_rev = DRA752_ES1_0; 369 *omap_si_rev = DRA752_ES1_0;
367 break; 370 break;
@@ -377,6 +380,9 @@ void init_omap_revision(void)
377 case DRA722_CONTROL_ID_CODE_ES2_0: 380 case DRA722_CONTROL_ID_CODE_ES2_0:
378 *omap_si_rev = DRA722_ES2_0; 381 *omap_si_rev = DRA722_ES2_0;
379 break; 382 break;
383 case DRA722_CONTROL_ID_CODE_ES2_1:
384 *omap_si_rev = DRA722_ES2_1;
385 break;
380 default: 386 default:
381 *omap_si_rev = OMAP5430_SILICON_ID_INVALID; 387 *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
382 } 388 }
@@ -454,10 +460,14 @@ void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
454} 460}
455 461
456#if defined(CONFIG_PALMAS_POWER) 462#if defined(CONFIG_PALMAS_POWER)
463__weak void board_mmc_poweron_ldo(uint voltage)
464{
465 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
466}
467
457void vmmc_pbias_config(uint voltage) 468void vmmc_pbias_config(uint voltage)
458{ 469{
459 u32 value = 0; 470 u32 value = 0;
460 struct vcores_data const *vcores = *omap_vcores;
461 471
462 value = readl((*ctrl)->control_pbias); 472 value = readl((*ctrl)->control_pbias);
463 value &= ~SDCARD_PWRDNZ; 473 value &= ~SDCARD_PWRDNZ;
@@ -466,15 +476,7 @@ void vmmc_pbias_config(uint voltage)
466 value &= ~SDCARD_BIAS_PWRDNZ; 476 value &= ~SDCARD_BIAS_PWRDNZ;
467 writel(value, (*ctrl)->control_pbias); 477 writel(value, (*ctrl)->control_pbias);
468 478
469 if (vcores->core.pmic->i2c_slave_addr == 0x60) { 479 board_mmc_poweron_ldo(voltage);
470 if (voltage == LDO_VOLT_3V0)
471 voltage = 0x19;
472 else if (voltage == LDO_VOLT_1V8)
473 voltage = 0xa;
474 lp873x_mmc1_poweron_ldo(voltage);
475 } else {
476 palmas_mmc1_poweron_ldo(voltage);
477 }
478 480
479 value = readl((*ctrl)->control_pbias); 481 value = readl((*ctrl)->control_pbias);
480 value |= SDCARD_BIAS_PWRDNZ; 482 value |= SDCARD_BIAS_PWRDNZ;
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 7712923d85..8fb962e39d 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -480,7 +480,9 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
480 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz; 480 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
481 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz); 481 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
482 break; 482 break;
483 case DRA762_ES1_0:
483 case DRA722_ES2_0: 484 case DRA722_ES2_0:
485 case DRA722_ES2_1:
484 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; 486 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
485 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); 487 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
486 break; 488 break;
@@ -709,11 +711,13 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
709 *iterations = sizeof(omap5_bug_00339_regs)/ 711 *iterations = sizeof(omap5_bug_00339_regs)/
710 sizeof(omap5_bug_00339_regs[0]); 712 sizeof(omap5_bug_00339_regs[0]);
711 break; 713 break;
714 case DRA762_ES1_0:
712 case DRA752_ES1_0: 715 case DRA752_ES1_0:
713 case DRA752_ES1_1: 716 case DRA752_ES1_1:
714 case DRA752_ES2_0: 717 case DRA752_ES2_0:
715 case DRA722_ES1_0: 718 case DRA722_ES1_0:
716 case DRA722_ES2_0: 719 case DRA722_ES2_0:
720 case DRA722_ES2_1:
717 bug_00339_regs_ptr = dra_bug_00339_regs; 721 bug_00339_regs_ptr = dra_bug_00339_regs;
718 *iterations = sizeof(dra_bug_00339_regs)/ 722 *iterations = sizeof(dra_bug_00339_regs)/
719 sizeof(dra_bug_00339_regs[0]); 723 sizeof(dra_bug_00339_regs[0]);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0c87fa4492..fa81de1152 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -108,7 +108,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
108 socfpga_cyclone5_sr1500.dtb 108 socfpga_cyclone5_sr1500.dtb
109 109
110dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ 110dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
111 dra72-evm-revc.dtb dra71-evm.dtb 111 dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
112dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ 112dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
113 am572x-idk.dtb \ 113 am572x-idk.dtb \
114 am571x-idk.dtb 114 am571x-idk.dtb
diff --git a/arch/arm/dts/dra7-evm-common.dtsi b/arch/arm/dts/dra7-evm-common.dtsi
new file mode 100644
index 0000000000..78ffafd143
--- /dev/null
+++ b/arch/arm/dts/dra7-evm-common.dtsi
@@ -0,0 +1,190 @@
1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11
12/ {
13 chosen {
14 stdout-path = &uart1;
15 tick-timer = &timer2;
16 };
17
18 extcon_usb1: extcon_usb1 {
19 compatible = "linux,extcon-usb-gpio";
20 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
21 };
22
23 extcon_usb2: extcon_usb2 {
24 compatible = "linux,extcon-usb-gpio";
25 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
26 };
27
28 leds {
29 compatible = "gpio-leds";
30 led@0 {
31 label = "dra7:usr1";
32 gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
33 default-state = "off";
34 };
35
36 led@1 {
37 label = "dra7:usr2";
38 gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
39 default-state = "off";
40 };
41
42 led@2 {
43 label = "dra7:usr3";
44 gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
45 default-state = "off";
46 };
47
48 led@3 {
49 label = "dra7:usr4";
50 gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
51 default-state = "off";
52 };
53 };
54
55 gpio_keys {
56 compatible = "gpio-keys";
57 #address-cells = <1>;
58 #size-cells = <0>;
59 autorepeat;
60
61 USER1 {
62 label = "btnUser1";
63 linux,code = <BTN_0>;
64 gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
65 };
66
67 USER2 {
68 label = "btnUser2";
69 linux,code = <BTN_1>;
70 gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
71 };
72 };
73};
74
75&dra7_pmx_core {
76 dcan1_pins_default: dcan1_pins_default {
77 pinctrl-single,pins = <
78 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
79 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
80 >;
81 };
82
83 dcan1_pins_sleep: dcan1_pins_sleep {
84 pinctrl-single,pins = <
85 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
86 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
87 >;
88 };
89};
90
91&i2c3 {
92 status = "okay";
93 clock-frequency = <400000>;
94};
95
96&mcspi1 {
97 status = "okay";
98};
99
100&mcspi2 {
101 status = "okay";
102};
103
104&uart1 {
105 status = "okay";
106 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
107 <&dra7_pmx_core 0x3e0>;
108};
109
110&uart2 {
111 status = "okay";
112};
113
114&uart3 {
115 status = "okay";
116};
117
118
119&qspi {
120 status = "okay";
121
122 spi-max-frequency = <76800000>;
123 m25p80@0 {
124 compatible = "s25fl256s1";
125 spi-max-frequency = <76800000>;
126 reg = <0>;
127 spi-tx-bus-width = <1>;
128 spi-rx-bus-width = <4>;
129 #address-cells = <1>;
130 #size-cells = <1>;
131
132 /* MTD partition table.
133 * The ROM checks the first four physical blocks
134 * for a valid file to boot and the flash here is
135 * 64KiB block size.
136 */
137 partition@0 {
138 label = "QSPI.SPL";
139 reg = <0x00000000 0x000040000>;
140 };
141 partition@1 {
142 label = "QSPI.u-boot";
143 reg = <0x00040000 0x00100000>;
144 };
145 partition@2 {
146 label = "QSPI.u-boot-spl-os";
147 reg = <0x00140000 0x00080000>;
148 };
149 partition@3 {
150 label = "QSPI.u-boot-env";
151 reg = <0x001c0000 0x00010000>;
152 };
153 partition@4 {
154 label = "QSPI.u-boot-env.backup1";
155 reg = <0x001d0000 0x0010000>;
156 };
157 partition@5 {
158 label = "QSPI.kernel";
159 reg = <0x001e0000 0x0800000>;
160 };
161 partition@6 {
162 label = "QSPI.file-system";
163 reg = <0x009e0000 0x01620000>;
164 };
165 };
166};
167
168&omap_dwc3_1 {
169 extcon = <&extcon_usb1>;
170};
171
172&omap_dwc3_2 {
173 extcon = <&extcon_usb2>;
174};
175
176&usb1 {
177 dr_mode = "peripheral";
178};
179
180&usb2 {
181 dr_mode = "host";
182};
183
184&dcan1 {
185 status = "ok";
186 pinctrl-names = "default", "sleep", "active";
187 pinctrl-0 = <&dcan1_pins_sleep>;
188 pinctrl-1 = <&dcan1_pins_sleep>;
189 pinctrl-2 = <&dcan1_pins_default>;
190};
diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index ecfaf6052d..ceee1a76b5 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -8,17 +8,14 @@
8/dts-v1/; 8/dts-v1/;
9 9
10#include "dra74x.dtsi" 10#include "dra74x.dtsi"
11#include "dra7-evm-common.dtsi"
11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
12 14
13/ { 15/ {
14 model = "TI DRA742"; 16 model = "TI DRA742";
15 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; 17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
16 18
17 chosen {
18 stdout-path = &uart1;
19 tick-timer = &timer2;
20 };
21
22 memory { 19 memory {
23 device_type = "memory"; 20 device_type = "memory";
24 reg = <0x80000000 0x60000000>; /* 1536 MB */ 21 reg = <0x80000000 0x60000000>; /* 1536 MB */
@@ -33,23 +30,34 @@
33 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; 30 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
34 }; 31 };
35 32
36 mmc2_3v3: fixedregulator-mmc2 { 33 evm_3v3_sw: fixedregulator-evm_3v3_sw {
37 compatible = "regulator-fixed"; 34 compatible = "regulator-fixed";
38 regulator-name = "mmc2_3v3"; 35 regulator-name = "evm_3v3_sw";
36 vin-supply = <&sysen1>;
39 regulator-min-microvolt = <3300000>; 37 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>; 38 regulator-max-microvolt = <3300000>;
41 }; 39 };
42 40
43 extcon_usb1: extcon_usb1 { 41 aic_dvdd: fixedregulator-aic_dvdd {
44 compatible = "linux,extcon-usb-gpio"; 42 /* TPS77018DBVT */
45 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; 43 compatible = "regulator-fixed";
44 regulator-name = "aic_dvdd";
45 vin-supply = <&evm_3v3_sw>;
46 regulator-min-microvolt = <1800000>;
47 regulator-max-microvolt = <1800000>;
46 }; 48 };
47 49
48 extcon_usb2: extcon_usb2 { 50 vmmcwl_fixed: fixedregulator-mmcwl {
49 compatible = "linux,extcon-usb-gpio"; 51 compatible = "regulator-fixed";
50 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; 52 regulator-name = "vmmcwl_fixed";
53 regulator-min-microvolt = <1800000>;
54 regulator-max-microvolt = <1800000>;
55 gpio = <&gpio5 8 0>; /* gpio5_8 */
56 startup-delay-us = <70000>;
57 enable-active-high;
51 }; 58 };
52 59
60
53 vtt_fixed: fixedregulator-vtt { 61 vtt_fixed: fixedregulator-vtt {
54 compatible = "regulator-fixed"; 62 compatible = "regulator-fixed";
55 regulator-name = "vtt_fixed"; 63 regulator-name = "vtt_fixed";
@@ -58,234 +66,30 @@
58 regulator-always-on; 66 regulator-always-on;
59 regulator-boot-on; 67 regulator-boot-on;
60 enable-active-high; 68 enable-active-high;
69 vin-supply = <&sysen2>;
61 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; 70 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
62 }; 71 };
63}; 72};
64 73
65&dra7_pmx_core { 74&dra7_pmx_core {
66 pinctrl-names = "default"; 75 hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
67 pinctrl-0 = <&vtt_pin>;
68
69 vtt_pin: pinmux_vtt_pin {
70 pinctrl-single,pins = <
71 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
72 >;
73 };
74
75 i2c1_pins: pinmux_i2c1_pins {
76 pinctrl-single,pins = <
77 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
78 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
79 >;
80 };
81
82 i2c2_pins: pinmux_i2c2_pins {
83 pinctrl-single,pins = <
84 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
85 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
86 >;
87 };
88
89 i2c3_pins: pinmux_i2c3_pins {
90 pinctrl-single,pins = <
91 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
92 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
93 >;
94 };
95
96 mcspi1_pins: pinmux_mcspi1_pins {
97 pinctrl-single,pins = <
98 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
99 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
100 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
101 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
102 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
103 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
104 >;
105 };
106
107 mcspi2_pins: pinmux_mcspi2_pins {
108 pinctrl-single,pins = <
109 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
110 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
111 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
112 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
113 >;
114 };
115
116 uart1_pins: pinmux_uart1_pins {
117 pinctrl-single,pins = <
118 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
119 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
120 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
121 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
122 >;
123 };
124
125 uart2_pins: pinmux_uart2_pins {
126 pinctrl-single,pins = <
127 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
128 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
129 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
130 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
131 >;
132 };
133
134 uart3_pins: pinmux_uart3_pins {
135 pinctrl-single,pins = < 76 pinctrl-single,pins = <
136 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ 77 /* this pin is used as a GPIO via mcasp */
137 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ 78 0x2fc (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
138 >; 79 >;
139 }; 80 };
140 81
141 qspi1_pins: pinmux_qspi1_pins { 82 hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
142 pinctrl-single,pins = < 83 pinctrl-single,pins = <
143 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */ 84 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
144 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */ 85 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
145 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
146 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
147 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
148 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
149 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
150 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
151 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
152 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
153 >; 86 >;
154 }; 87 };
155 88
156 usb1_pins: pinmux_usb1_pins { 89 hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
157 pinctrl-single,pins = <
158 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
159 >;
160 };
161
162 usb2_pins: pinmux_usb2_pins {
163 pinctrl-single,pins = <
164 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
165 >;
166 };
167
168 nand_flash_x16: nand_flash_x16 {
169 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
170 * So NAND flash requires following switch settings:
171 * SW5.9 (GPMC_WPN) = LOW
172 * SW5.1 (NAND_BOOTn) = HIGH */
173 pinctrl-single,pins = < 90 pinctrl-single,pins = <
174 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ 91 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
175 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ 92 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
176 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
177 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
178 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
179 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
180 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
181 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
182 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
183 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
184 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
185 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
186 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
187 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
188 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
189 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
190 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
191 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
192 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
193 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
194 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
195 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
196 >;
197 };
198
199 cpsw_default: cpsw_default {
200 pinctrl-single,pins = <
201 /* Slave 1 */
202 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
203 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
204 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
205 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
206 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
207 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
208 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
209 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
210 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
211 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
212 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
213 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
214
215 /* Slave 2 */
216 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
217 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
218 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
219 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
220 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
221 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
222 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
223 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
224 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
225 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
226 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
227 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
228 >;
229
230 };
231
232 cpsw_sleep: cpsw_sleep {
233 pinctrl-single,pins = <
234 /* Slave 1 */
235 0x250 (MUX_MODE15)
236 0x254 (MUX_MODE15)
237 0x258 (MUX_MODE15)
238 0x25c (MUX_MODE15)
239 0x260 (MUX_MODE15)
240 0x264 (MUX_MODE15)
241 0x268 (MUX_MODE15)
242 0x26c (MUX_MODE15)
243 0x270 (MUX_MODE15)
244 0x274 (MUX_MODE15)
245 0x278 (MUX_MODE15)
246 0x27c (MUX_MODE15)
247
248 /* Slave 2 */
249 0x198 (MUX_MODE15)
250 0x19c (MUX_MODE15)
251 0x1a0 (MUX_MODE15)
252 0x1a4 (MUX_MODE15)
253 0x1a8 (MUX_MODE15)
254 0x1ac (MUX_MODE15)
255 0x1b0 (MUX_MODE15)
256 0x1b4 (MUX_MODE15)
257 0x1b8 (MUX_MODE15)
258 0x1bc (MUX_MODE15)
259 0x1c0 (MUX_MODE15)
260 0x1c4 (MUX_MODE15)
261 >;
262 };
263
264 davinci_mdio_default: davinci_mdio_default {
265 pinctrl-single,pins = <
266 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
267 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
268 >;
269 };
270
271 davinci_mdio_sleep: davinci_mdio_sleep {
272 pinctrl-single,pins = <
273 0x23c (MUX_MODE15)
274 0x240 (MUX_MODE15)
275 >;
276 };
277
278 dcan1_pins_default: dcan1_pins_default {
279 pinctrl-single,pins = <
280 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
281 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
282 >;
283 };
284
285 dcan1_pins_sleep: dcan1_pins_sleep {
286 pinctrl-single,pins = <
287 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
288 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
289 >; 93 >;
290 }; 94 };
291 95
@@ -623,8 +427,6 @@
623 427
624&i2c1 { 428&i2c1 {
625 status = "okay"; 429 status = "okay";
626 pinctrl-names = "default";
627 pinctrl-0 = <&i2c1_pins>;
628 clock-frequency = <400000>; 430 clock-frequency = <400000>;
629 431
630 tps659038: tps659038@58 { 432 tps659038: tps659038@58 {
@@ -648,7 +450,7 @@
648 /* VDD_DSPEVE */ 450 /* VDD_DSPEVE */
649 regulator-name = "smps45"; 451 regulator-name = "smps45";
650 regulator-min-microvolt = < 850000>; 452 regulator-min-microvolt = < 850000>;
651 regulator-max-microvolt = <1150000>; 453 regulator-max-microvolt = <1250000>;
652 regulator-always-on; 454 regulator-always-on;
653 regulator-boot-on; 455 regulator-boot-on;
654 }; 456 };
@@ -666,7 +468,7 @@
666 /* CORE_VDD */ 468 /* CORE_VDD */
667 regulator-name = "smps7"; 469 regulator-name = "smps7";
668 regulator-min-microvolt = <850000>; 470 regulator-min-microvolt = <850000>;
669 regulator-max-microvolt = <1060000>; 471 regulator-max-microvolt = <1150000>;
670 regulator-always-on; 472 regulator-always-on;
671 regulator-boot-on; 473 regulator-boot-on;
672 }; 474 };
@@ -694,6 +496,7 @@
694 regulator-name = "ldo1"; 496 regulator-name = "ldo1";
695 regulator-min-microvolt = <1800000>; 497 regulator-min-microvolt = <1800000>;
696 regulator-max-microvolt = <3300000>; 498 regulator-max-microvolt = <3300000>;
499 regulator-always-on;
697 regulator-boot-on; 500 regulator-boot-on;
698 }; 501 };
699 502
@@ -723,6 +526,7 @@
723 regulator-max-microvolt = <1050000>; 526 regulator-max-microvolt = <1050000>;
724 regulator-always-on; 527 regulator-always-on;
725 regulator-boot-on; 528 regulator-boot-on;
529 regulator-allow-bypass;
726 }; 530 };
727 531
728 ldoln_reg: ldoln { 532 ldoln_reg: ldoln {
@@ -741,10 +545,46 @@
741 regulator-max-microvolt = <3300000>; 545 regulator-max-microvolt = <3300000>;
742 regulator-boot-on; 546 regulator-boot-on;
743 }; 547 };
548
549 /* REGEN1 is unused */
550
551 regen2: regen2 {
552 /* Needed for PMIC internal resources */
553 regulator-name = "regen2";
554 regulator-boot-on;
555 regulator-always-on;
556 };
557
558 /* REGEN3 is unused */
559
560 sysen1: sysen1 {
561 /* PMIC_REGEN_3V3 */
562 regulator-name = "sysen1";
563 regulator-boot-on;
564 regulator-always-on;
565 };
566
567 sysen2: sysen2 {
568 /* PMIC_REGEN_DDR */
569 regulator-name = "sysen2";
570 regulator-boot-on;
571 regulator-always-on;
572 };
744 }; 573 };
745 }; 574 };
746 }; 575 };
747 576
577 pcf_lcd: gpio@20 {
578 compatible = "nxp,pcf8575";
579 reg = <0x20>;
580 gpio-controller;
581 #gpio-cells = <2>;
582 interrupt-parent = <&gpio6>;
583 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
586 };
587
748 pcf_gpio_21: gpio@21 { 588 pcf_gpio_21: gpio@21 {
749 compatible = "ti,pcf8575"; 589 compatible = "ti,pcf8575";
750 reg = <0x21>; 590 reg = <0x21>;
@@ -757,52 +597,39 @@
757 #interrupt-cells = <2>; 597 #interrupt-cells = <2>;
758 }; 598 };
759 599
760}; 600 tlv320aic3106: tlv320aic3106@19 {
601 #sound-dai-cells = <0>;
602 compatible = "ti,tlv320aic3106";
603 reg = <0x19>;
604 adc-settle-ms = <40>;
605 ai3x-micbias-vg = <1>; /* 2.0V */
606 status = "okay";
761 607
762&i2c2 { 608 /* Regulators */
763 status = "okay"; 609 AVDD-supply = <&evm_3v3_sw>;
764 pinctrl-names = "default"; 610 IOVDD-supply = <&evm_3v3_sw>;
765 pinctrl-0 = <&i2c2_pins>; 611 DRVDD-supply = <&evm_3v3_sw>;
766 clock-frequency = <400000>; 612 DVDD-supply = <&aic_dvdd>;
613 };
767}; 614};
768 615
769&i2c3 { 616&i2c2 {
770 status = "okay"; 617 status = "okay";
771 pinctrl-names = "default";
772 pinctrl-0 = <&i2c3_pins>;
773 clock-frequency = <400000>; 618 clock-frequency = <400000>;
774};
775
776&mcspi1 {
777 status = "okay";
778 pinctrl-names = "default";
779 pinctrl-0 = <&mcspi1_pins>;
780};
781
782&mcspi2 {
783 status = "okay";
784 pinctrl-names = "default";
785 pinctrl-0 = <&mcspi2_pins>;
786};
787
788&uart1 {
789 status = "okay";
790 pinctrl-names = "default";
791 pinctrl-0 = <&uart1_pins>;
792 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
793 <&dra7_pmx_core 0x3e0>;
794};
795 619
796&uart2 { 620 pcf_hdmi: gpio@26 {
797 status = "okay"; 621 compatible = "nxp,pcf8575";
798 pinctrl-names = "default"; 622 reg = <0x26>;
799 pinctrl-0 = <&uart2_pins>; 623 gpio-controller;
800}; 624 #gpio-cells = <2>;
801 625 p1 {
802&uart3 { 626 /* vin6_sel_s0: high: VIN6, low: audio */
803 status = "okay"; 627 gpio-hog;
804 pinctrl-names = "default"; 628 gpios = <1 GPIO_ACTIVE_HIGH>;
805 pinctrl-0 = <&uart3_pins>; 629 output-low;
630 line-name = "vin6_sel_s0";
631 };
632 };
806}; 633};
807 634
808&mmc1 { 635&mmc1 {
@@ -830,7 +657,7 @@
830 657
831&mmc2 { 658&mmc2 {
832 status = "okay"; 659 status = "okay";
833 vmmc-supply = <&mmc2_3v3>; 660 vmmc-supply = <&evm_3v3_sw>;
834 bus-width = <8>; 661 bus-width = <8>;
835 max-frequency = <192000000>; 662 max-frequency = <192000000>;
836 pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; 663 pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
@@ -846,97 +673,12 @@
846 cpu0-supply = <&smps123_reg>; 673 cpu0-supply = <&smps123_reg>;
847}; 674};
848 675
849&qspi {
850 status = "okay";
851 pinctrl-names = "default";
852 pinctrl-0 = <&qspi1_pins>;
853
854 spi-max-frequency = <64000000>;
855 m25p80@0 {
856 compatible = "s25fl256s1","spi-flash";
857 spi-max-frequency = <76800000>;
858 reg = <0>;
859 spi-tx-bus-width = <1>;
860 spi-rx-bus-width = <4>;
861 #address-cells = <1>;
862 #size-cells = <1>;
863
864 /* MTD partition table.
865 * The ROM checks the first four physical blocks
866 * for a valid file to boot and the flash here is
867 * 64KiB block size.
868 */
869 partition@0 {
870 label = "QSPI.SPL";
871 reg = <0x00000000 0x000010000>;
872 };
873 partition@1 {
874 label = "QSPI.SPL.backup1";
875 reg = <0x00010000 0x00010000>;
876 };
877 partition@2 {
878 label = "QSPI.SPL.backup2";
879 reg = <0x00020000 0x00010000>;
880 };
881 partition@3 {
882 label = "QSPI.SPL.backup3";
883 reg = <0x00030000 0x00010000>;
884 };
885 partition@4 {
886 label = "QSPI.u-boot";
887 reg = <0x00040000 0x00100000>;
888 };
889 partition@5 {
890 label = "QSPI.u-boot-spl-os";
891 reg = <0x00140000 0x00080000>;
892 };
893 partition@6 {
894 label = "QSPI.u-boot-env";
895 reg = <0x001c0000 0x00010000>;
896 };
897 partition@7 {
898 label = "QSPI.u-boot-env.backup1";
899 reg = <0x001d0000 0x0010000>;
900 };
901 partition@8 {
902 label = "QSPI.kernel";
903 reg = <0x001e0000 0x0800000>;
904 };
905 partition@9 {
906 label = "QSPI.file-system";
907 reg = <0x009e0000 0x01620000>;
908 };
909 };
910};
911
912&omap_dwc3_1 {
913 extcon = <&extcon_usb1>;
914};
915
916&omap_dwc3_2 {
917 extcon = <&extcon_usb2>;
918};
919
920&usb1 {
921 dr_mode = "peripheral";
922 pinctrl-names = "default";
923 pinctrl-0 = <&usb1_pins>;
924};
925
926&usb2 {
927 dr_mode = "host";
928 pinctrl-names = "default";
929 pinctrl-0 = <&usb2_pins>;
930};
931
932&elm { 676&elm {
933 status = "okay"; 677 status = "okay";
934}; 678};
935 679
936&gpmc { 680&gpmc {
937 status = "okay"; 681 status = "okay";
938 pinctrl-names = "default";
939 pinctrl-0 = <&nand_flash_x16>;
940 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ 682 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
941 nand@0,0 { 683 nand@0,0 {
942 reg = <0 0 4>; /* device IO registers */ 684 reg = <0 0 4>; /* device IO registers */
@@ -1028,9 +770,6 @@
1028 770
1029&mac { 771&mac {
1030 status = "okay"; 772 status = "okay";
1031 pinctrl-names = "default", "sleep";
1032 pinctrl-0 = <&cpsw_default>;
1033 pinctrl-1 = <&cpsw_sleep>;
1034 dual_emac; 773 dual_emac;
1035}; 774};
1036 775
@@ -1045,17 +784,3 @@
1045 phy-mode = "rgmii"; 784 phy-mode = "rgmii";
1046 dual_emac_res_vlan = <2>; 785 dual_emac_res_vlan = <2>;
1047}; 786};
1048
1049&davinci_mdio {
1050 pinctrl-names = "default", "sleep";
1051 pinctrl-0 = <&davinci_mdio_default>;
1052 pinctrl-1 = <&davinci_mdio_sleep>;
1053};
1054
1055&dcan1 {
1056 status = "ok";
1057 pinctrl-names = "default", "sleep", "active";
1058 pinctrl-0 = <&dcan1_pins_sleep>;
1059 pinctrl-1 = <&dcan1_pins_sleep>;
1060 pinctrl-2 = <&dcan1_pins_default>;
1061};
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index ec8de7a116..e9eb8f0986 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -146,6 +146,7 @@
146 #address-cells = <1>; 146 #address-cells = <1>;
147 #size-cells = <0>; 147 #size-cells = <0>;
148 #interrupt-cells = <1>; 148 #interrupt-cells = <1>;
149 #pinctrl-cells = <1>;
149 interrupt-controller; 150 interrupt-controller;
150 pinctrl-single,register-width = <32>; 151 pinctrl-single,register-width = <32>;
151 pinctrl-single,function-mask = <0x3fffffff>; 152 pinctrl-single,function-mask = <0x3fffffff>;
@@ -302,6 +303,7 @@
302 reg = <0x4844a000 0x0d1c>; 303 reg = <0x4844a000 0x0d1c>;
303 #address-cells = <1>; 304 #address-cells = <1>;
304 #size-cells = <0>; 305 #size-cells = <0>;
306 #pinctrl-cells = <1>;
305 }; 307 };
306 308
307 sdma: dma-controller@4a056000 { 309 sdma: dma-controller@4a056000 {
diff --git a/arch/arm/dts/dra76-evm.dts b/arch/arm/dts/dra76-evm.dts
new file mode 100644
index 0000000000..1a149fa5fe
--- /dev/null
+++ b/arch/arm/dts/dra76-evm.dts
@@ -0,0 +1,388 @@
1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra76x.dtsi"
11#include "dra7-evm-common.dtsi"
12#include "dra76x-mmc-iodelay.dtsi"
13#include <dt-bindings/net/ti-dp83867.h>
14
15/ {
16 model = "TI DRA762 EVM";
17 compatible = "ti,dra76-evm", "ti,dra76", "ti,dra7";
18
19 memory@0 {
20 device_type = "memory";
21 reg = <0x0 0x80000000 0x0 0x80000000>;
22 };
23
24 vsys_12v0: fixedregulator-vsys12v0 {
25 /* main supply */
26 compatible = "regulator-fixed";
27 regulator-name = "vsys_12v0";
28 regulator-min-microvolt = <12000000>;
29 regulator-max-microvolt = <12000000>;
30 regulator-always-on;
31 regulator-boot-on;
32 };
33
34 vsys_5v0: fixedregulator-vsys5v0 {
35 /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */
36 compatible = "regulator-fixed";
37 regulator-name = "vsys_5v0";
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
40 vin-supply = <&vsys_12v0>;
41 regulator-always-on;
42 regulator-boot-on;
43 };
44
45 vsys_3v3: fixedregulator-vsys3v3 {
46 /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */
47 compatible = "regulator-fixed";
48 regulator-name = "vsys_3v3";
49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
51 vin-supply = <&vsys_12v0>;
52 regulator-always-on;
53 regulator-boot-on;
54 };
55
56 vio_3v3: fixedregulator-vio_3v3 {
57 compatible = "regulator-fixed";
58 regulator-name = "vio_3v3";
59 regulator-min-microvolt = <3300000>;
60 regulator-max-microvolt = <3300000>;
61 vin-supply = <&vsys_3v3>;
62 regulator-always-on;
63 regulator-boot-on;
64 };
65
66 vio_3v3_sd: fixedregulator-sd {
67 compatible = "regulator-fixed";
68 regulator-name = "vio_3v3_sd";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 vin-supply = <&vio_3v3>;
72 enable-active-high;
73 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
74 };
75
76 vio_1v8: fixedregulator-vio_1v8 {
77 compatible = "regulator-fixed";
78 regulator-name = "vio_1v8";
79 regulator-min-microvolt = <1800000>;
80 regulator-max-microvolt = <1800000>;
81 vin-supply = <&smps5_reg>;
82 };
83
84 vtt_fixed: fixedregulator-vtt {
85 compatible = "regulator-fixed";
86 regulator-name = "vtt_fixed";
87 regulator-min-microvolt = <1350000>;
88 regulator-max-microvolt = <1350000>;
89 vin-supply = <&vsys_3v3>;
90 regulator-always-on;
91 regulator-boot-on;
92 };
93
94 aic_dvdd: fixedregulator-aic_dvdd {
95 /* TPS77018DBVT */
96 compatible = "regulator-fixed";
97 regulator-name = "aic_dvdd";
98 vin-supply = <&vio_3v3>;
99 regulator-min-microvolt = <1800000>;
100 regulator-max-microvolt = <1800000>;
101 };
102};
103
104&i2c1 {
105 status = "okay";
106 clock-frequency = <400000>;
107
108 tps65917: tps65917@58 {
109 compatible = "ti,tps65917";
110 reg = <0x58>;
111 ti,system-power-controller;
112 interrupt-controller;
113 #interrupt-cells = <2>;
114
115 tps65917_pmic {
116 compatible = "ti,tps65917-pmic";
117
118 smps12-in-supply = <&vsys_3v3>;
119 smps3-in-supply = <&vsys_3v3>;
120 smps4-in-supply = <&vsys_3v3>;
121 smps5-in-supply = <&vsys_3v3>;
122 ldo1-in-supply = <&vsys_3v3>;
123 ldo2-in-supply = <&vsys_3v3>;
124 ldo3-in-supply = <&vsys_5v0>;
125 ldo4-in-supply = <&vsys_5v0>;
126 ldo5-in-supply = <&vsys_3v3>;
127
128 tps65917_regulators: regulators {
129 smps12_reg: smps12 {
130 /* VDD_DSPEVE */
131 regulator-name = "smps12";
132 regulator-min-microvolt = <850000>;
133 regulator-max-microvolt = <1250000>;
134 regulator-always-on;
135 regulator-boot-on;
136 };
137
138 smps3_reg: smps3 {
139 /* VDD_CORE */
140 regulator-name = "smps3";
141 regulator-min-microvolt = <850000>;
142 regulator-max-microvolt = <1250000>;
143 regulator-boot-on;
144 regulator-always-on;
145 };
146
147 smps4_reg: smps4 {
148 /* VDD_IVA */
149 regulator-name = "smps4";
150 regulator-min-microvolt = <850000>;
151 regulator-max-microvolt = <1250000>;
152 regulator-always-on;
153 regulator-boot-on;
154 };
155
156 smps5_reg: smps5 {
157 /* VDDS1V8 */
158 regulator-name = "smps5";
159 regulator-min-microvolt = <1800000>;
160 regulator-max-microvolt = <1800000>;
161 regulator-boot-on;
162 regulator-always-on;
163 };
164
165 ldo1_reg: ldo1 {
166 /* LDO1_OUT --> VDA_PHY1_1V8 */
167 regulator-name = "ldo1";
168 regulator-min-microvolt = <1800000>;
169 regulator-max-microvolt = <1800000>;
170 regulator-always-on;
171 regulator-boot-on;
172 regulator-allow-bypass;
173 };
174
175 ldo2_reg: ldo2 {
176 /* LDO2_OUT --> VDA_PHY2_1V8 */
177 regulator-name = "ldo2";
178 regulator-min-microvolt = <1800000>;
179 regulator-max-microvolt = <1800000>;
180 regulator-allow-bypass;
181 regulator-always-on;
182 };
183
184 ldo3_reg: ldo3 {
185 /* VDA_USB_3V3 */
186 regulator-name = "ldo3";
187 regulator-min-microvolt = <3300000>;
188 regulator-max-microvolt = <3300000>;
189 regulator-boot-on;
190 regulator-always-on;
191 };
192
193 ldo5_reg: ldo5 {
194 /* VDDA_1V8_PLL */
195 regulator-name = "ldo5";
196 regulator-min-microvolt = <1800000>;
197 regulator-max-microvolt = <1800000>;
198 regulator-always-on;
199 regulator-boot-on;
200 };
201
202 ldo4_reg: ldo4 {
203 /* VDD_SDIO_DV */
204 regulator-name = "ldo4";
205 regulator-min-microvolt = <1800000>;
206 regulator-max-microvolt = <3300000>;
207 regulator-boot-on;
208 regulator-always-on;
209 };
210 };
211 };
212
213 tps65917_power_button {
214 compatible = "ti,palmas-pwrbutton";
215 interrupt-parent = <&tps65917>;
216 interrupts = <1 IRQ_TYPE_NONE>;
217 wakeup-source;
218 ti,palmas-long-press-seconds = <6>;
219 };
220 };
221
222 lp87565: lp87565@60 {
223 compatible = "ti,lp87565-q1";
224 reg = <0x60>;
225
226 buck10-in-supply =<&vsys_3v3>;
227 buck23-in-supply =<&vsys_3v3>;
228
229 regulators: regulators {
230 buck10_reg: buck10 {
231 /*VDD_MPU*/
232 regulator-name = "buck10";
233 regulator-min-microvolt = <850000>;
234 regulator-max-microvolt = <1250000>;
235 regulator-always-on;
236 regulator-boot-on;
237 };
238
239 buck23_reg: buck23 {
240 /* VDD_GPU*/
241 regulator-name = "buck23";
242 regulator-min-microvolt = <850000>;
243 regulator-max-microvolt = <1250000>;
244 regulator-boot-on;
245 regulator-always-on;
246 };
247 };
248 };
249
250 pcf_lcd: pcf8757@20 {
251 compatible = "ti,pcf8575", "nxp,pcf8575";
252 reg = <0x20>;
253 gpio-controller;
254 #gpio-cells = <2>;
255 interrupt-controller;
256 #interrupt-cells = <2>;
257 interrupt-parent = <&gpio1>;
258 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
259 };
260
261 pcf_gpio_21: pcf8757@21 {
262 compatible = "ti,pcf8575", "nxp,pcf8575";
263 reg = <0x21>;
264 gpio-controller;
265 #gpio-cells = <2>;
266 interrupt-parent = <&gpio1>;
267 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
268 interrupt-controller;
269 #interrupt-cells = <2>;
270 };
271
272 pcf_hdmi: pcf8575@26 {
273 compatible = "ti,pcf8575", "nxp,pcf8575";
274 reg = <0x26>;
275 gpio-controller;
276 #gpio-cells = <2>;
277 p1 {
278 /* vin6_sel_s0: high: VIN6, low: audio */
279 gpio-hog;
280 gpios = <1 GPIO_ACTIVE_HIGH>;
281 output-low;
282 line-name = "vin6_sel_s0";
283 };
284 };
285
286 tlv320aic3106: tlv320aic3106@19 {
287 #sound-dai-cells = <0>;
288 compatible = "ti,tlv320aic3106";
289 reg = <0x19>;
290 adc-settle-ms = <40>;
291 ai3x-micbias-vg = <1>; /* 2.0V */
292 status = "okay";
293
294 /* Regulators */
295 AVDD-supply = <&vio_3v3>;
296 IOVDD-supply = <&vio_3v3>;
297 DRVDD-supply = <&vio_3v3>;
298 DVDD-supply = <&aic_dvdd>;
299 };
300};
301
302&cpu0 {
303 vdd-supply = <&buck10_reg>;
304};
305
306&mmc1 {
307 status = "okay";
308 vmmc-supply = <&vio_3v3_sd>;
309 vmmc_aux-supply = <&ldo4_reg>;
310 bus-width = <4>;
311 /*
312 * SDCD signal is not being used here - using the fact that GPIO mode
313 * is always hardwired.
314 */
315 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
316 max-frequency = <192000000>;
317 pinctrl-names = "default", "hs";
318 pinctrl-0 = <&mmc1_pins_default>;
319 pinctrl-1 = <&mmc1_pins_hs>;
320};
321
322&mmc2 {
323 status = "okay";
324 vmmc-supply = <&vio_1v8>;
325 bus-width = <8>;
326 max-frequency = <192000000>;
327 pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
328 pinctrl-0 = <&mmc2_pins_default>;
329 pinctrl-1 = <&mmc2_pins_hs>;
330 pinctrl-2 = <&mmc2_pins_ddr>;
331 pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
332};
333
334/* No RTC on this device */
335&rtc {
336 status = "disabled";
337};
338
339&mac {
340 status = "okay";
341
342 dual_emac;
343};
344
345&cpsw_emac0 {
346 phy-handle = <&dp83867_0>;
347 phy-mode = "rgmii-id";
348 dual_emac_res_vlan = <1>;
349};
350
351&cpsw_emac1 {
352 phy-handle = <&dp83867_1>;
353 phy-mode = "rgmii-id";
354 dual_emac_res_vlan = <2>;
355};
356
357&davinci_mdio {
358 dp83867_0: ethernet-phy@2 {
359 reg = <2>;
360 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
361 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
362 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
363 ti,min-output-impedance;
364 };
365
366 dp83867_1: ethernet-phy@3 {
367 reg = <3>;
368 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
369 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
370 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
371 ti,min-output-impedance;
372 };
373};
374
375&usb2_phy1 {
376 phy-supply = <&ldo3_reg>;
377};
378
379&usb2_phy2 {
380 phy-supply = <&ldo3_reg>;
381};
382
383&qspi {
384 spi-max-frequency = <96000000>;
385 m25p80@0 {
386 spi-max-frequency = <96000000>;
387 };
388};
diff --git a/arch/arm/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/dts/dra76x-mmc-iodelay.dtsi
new file mode 100644
index 0000000000..ff578843eb
--- /dev/null
+++ b/arch/arm/dts/dra76x-mmc-iodelay.dtsi
@@ -0,0 +1,244 @@
1/*
2 * MMC IOdelay values for TI's DRA76x and AM576x SoCs.
3 *
4 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/*
17 * Rules for modifying this file:
18 * a) Update of this file should typically correspond to a datamanual revision.
19 * Datamanual revision that was used should be updated in comment below.
20 * If there is no update to datamanual, do not update the values. If you
21 * need to use values different from that recommended by the datamanual
22 * for your design, then you should consider adding values to the device-
23 * -tree file for your board directly.
24 * b) We keep the mode names as close to the datamanual as possible. So
25 * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
26 * we follow that in code too.
27 * c) If the values change between multiple revisions of silicon, we add
28 * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
29 * 'rev20' for PG 2.0 and so on.
30 * d) The node name and node label should be the exact same string. This is
31 * to curb naming creativity and achieve consistency.
32 *
33 * Datamanual Revisions:
34 *
35 * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017
36 *
37 */
38
39&dra7_pmx_core {
40 mmc1_pins_default: mmc1_pins_default {
41 pinctrl-single,pins = <
42 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
43 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
44 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
45 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
46 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
47 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
48 >;
49 };
50
51 mmc1_pins_sdr12: mmc1_pins_sdr12 {
52 pinctrl-single,pins = <
53 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
54 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
55 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
56 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
57 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
58 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
59 >;
60 };
61
62 mmc1_pins_hs: mmc1_pins_hs {
63 pinctrl-single,pins = <
64 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
65 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
66 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
67 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
68 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
69 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
70 >;
71 };
72
73 mmc1_pins_sdr25: mmc1_pins_sdr25 {
74 pinctrl-single,pins = <
75 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
76 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
77 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
78 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
79 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
80 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
81 >;
82 };
83
84 mmc1_pins_sdr50: mmc1_pins_sdr50 {
85 pinctrl-single,pins = <
86 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */
87 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */
88 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */
89 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */
90 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */
91 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */
92 >;
93 };
94
95 mmc1_pins_ddr50: mmc1_pins_ddr50 {
96 pinctrl-single,pins = <
97 0x354 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
98 0x358 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
99 0x35c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
100 0x360 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
101 0x364 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
102 0x368 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
103 >;
104 };
105
106 mmc1_pins_sdr104: mmc1_pins_sdr104 {
107 pinctrl-single,pins = <
108 0x354 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
109 0x358 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
110 0x35c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
111 0x360 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
112 0x364 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
113 0x368 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
114 >;
115 };
116
117 mmc2_pins_default: mmc2_pins_default {
118 pinctrl-single,pins = <
119 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
120 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
121 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
122 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
123 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
124 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
125 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
126 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
127 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
128 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
129 >;
130 };
131
132 mmc2_pins_hs: mmc2_pins_hs {
133 pinctrl-single,pins = <
134 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
135 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
136 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
137 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
138 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
139 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
140 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
141 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
142 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
143 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
144 >;
145 };
146
147 mmc2_pins_ddr: mmc2_pins_ddr {
148 pinctrl-single,pins = <
149 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
150 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
151 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
152 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
153 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
154 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
155 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
156 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
157 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
158 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
159 >;
160 };
161
162 mmc2_pins_hs200: mmc2_pins_hs200 {
163 pinctrl-single,pins = <
164 0x9c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
165 0xb0 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
166 0xa0 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
167 0xa4 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
168 0xa8 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
169 0xac (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
170 0x8c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
171 0x90 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
172 0x94 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
173 0x98 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
174 >;
175 };
176};
177
178&dra7_iodelay_core {
179
180 /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
181 mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf {
182 pinctrl-single,pins = <
183 0x618 (A_DELAY(489) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */
184 0x624 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_IN */
185 0x630 (A_DELAY(374) | G_DELAY(0)) /* CFG_MMC1_DAT0_IN */
186 0x63c (A_DELAY(31) | G_DELAY(0)) /* CFG_MMC1_DAT1_IN */
187 0x648 (A_DELAY(56) | G_DELAY(0)) /* CFG_MMC1_DAT2_IN */
188 0x654 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */
189 0x620 (A_DELAY(1355) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */
190 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
191 0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
192 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
193 0x638 (A_DELAY(0) | G_DELAY(4)) /* CFG_MMC1_DAT0_OUT */
194 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
195 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
196 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
197 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
198 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
199 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
200 >;
201 };
202
203 /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
204 mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
205 pinctrl-single,pins = <
206 0x620 (A_DELAY(892) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */
207 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
208 0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
209 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
210 0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
211 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
212 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
213 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
214 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
215 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
216 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
217 >;
218 };
219
220 /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
221 mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf {
222 pinctrl-single,pins = <
223 0x190 (A_DELAY(384) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
224 0x194 (A_DELAY(0) | G_DELAY(174)) /* CFG_GPMC_A19_OUT */
225 0x1a8 (A_DELAY(410) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
226 0x1ac (A_DELAY(85) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
227 0x1b4 (A_DELAY(468) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
228 0x1b8 (A_DELAY(139) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
229 0x1c0 (A_DELAY(676) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
230 0x1c4 (A_DELAY(69) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
231 0x1d0 (A_DELAY(1062) | G_DELAY(154)) /* CFG_GPMC_A23_OUT */
232 0x1d8 (A_DELAY(640) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
233 0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
234 0x1e4 (A_DELAY(356) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
235 0x1e8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
236 0x1f0 (A_DELAY(579) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
237 0x1f4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
238 0x1fc (A_DELAY(435) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
239 0x200 (A_DELAY(36) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
240 0x364 (A_DELAY(759) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
241 0x368 (A_DELAY(72) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
242 >;
243 };
244};
diff --git a/arch/arm/dts/dra76x.dtsi b/arch/arm/dts/dra76x.dtsi
new file mode 100644
index 0000000000..0176ce4da9
--- /dev/null
+++ b/arch/arm/dts/dra76x.dtsi
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "dra74x.dtsi"
10
11/ {
12 compatible = "ti,dra76", "ti,dra7";
13};
14
15&abb_mpu {
16 ti,abb_info = <
17 /*uV ABB efuse rbb_m fbb_m vset_m*/
18 1060000 0 0x0 0 0x02000000 0x01F00000
19 1160000 0 0x4 0 0x02000000 0x01F00000
20 1210000 0 0x8 0 0x02000000 0x01F00000
21 1250000 0 0xC 0 0x02000000 0x01F00000
22 >;
23};
24
25&mmc3 {
26 max-frequency = <96000000>;
27};
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index 724e252946..5a2ea8faef 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -21,8 +21,8 @@
21/* 21/*
22 * OMAP HSMMC register definitions 22 * OMAP HSMMC register definitions
23 */ 23 */
24#define OMAP_HSMMC1_BASE 0x48060100 24#define OMAP_HSMMC1_BASE 0x48060000
25#define OMAP_HSMMC2_BASE 0x481D8100 25#define OMAP_HSMMC2_BASE 0x481D8000
26 26
27#if defined(CONFIG_TI814X) 27#if defined(CONFIG_TI814X)
28#undef MMC_CLOCK_REFERENCE 28#undef MMC_CLOCK_REFERENCE
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
index 9c8ccb6c83..d06779956f 100644
--- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -31,8 +31,8 @@
31 * OMAP HSMMC register definitions 31 * OMAP HSMMC register definitions
32 */ 32 */
33 33
34#define OMAP_HSMMC1_BASE 0x4809C100 34#define OMAP_HSMMC1_BASE 0x4809C000
35#define OMAP_HSMMC2_BASE 0x480B4100 35#define OMAP_HSMMC2_BASE 0x480B4000
36#define OMAP_HSMMC3_BASE 0x480AD100 36#define OMAP_HSMMC3_BASE 0x480AD000
37 37
38#endif /* MMC_HOST_DEF_H */ 38#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 4c0e890194..489815e644 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -341,6 +341,9 @@
341/* Offset is 0.73V for LP873x */ 341/* Offset is 0.73V for LP873x */
342#define LP873X_BUCK_BASE_VOLT_UV 730000 342#define LP873X_BUCK_BASE_VOLT_UV 730000
343 343
344/* Offset is 0.73V for LP87565 */
345#define LP87565_BUCK_BASE_VOLT_UV 730000
346
344/* TPS659038 */ 347/* TPS659038 */
345#define TPS659038_I2C_SLAVE_ADDR 0x58 348#define TPS659038_I2C_SLAVE_ADDR 0x58
346#define TPS659038_REG_ADDR_SMPS12 0x23 349#define TPS659038_REG_ADDR_SMPS12 0x23
@@ -354,6 +357,7 @@
354#define TPS65917_REG_ADDR_SMPS1 0x23 357#define TPS65917_REG_ADDR_SMPS1 0x23
355#define TPS65917_REG_ADDR_SMPS2 0x27 358#define TPS65917_REG_ADDR_SMPS2 0x27
356#define TPS65917_REG_ADDR_SMPS3 0x2F 359#define TPS65917_REG_ADDR_SMPS3 0x2F
360#define TPS65917_REG_ADDR_SMPS4 0x33
357 361
358/* LP873X */ 362/* LP873X */
359#define LP873X_I2C_SLAVE_ADDR 0x60 363#define LP873X_I2C_SLAVE_ADDR 0x60
@@ -361,6 +365,11 @@
361#define LP873X_REG_ADDR_BUCK1 0x7 365#define LP873X_REG_ADDR_BUCK1 0x7
362#define LP873X_REG_ADDR_LDO1 0xA 366#define LP873X_REG_ADDR_LDO1 0xA
363 367
368/* LP87565 */
369#define LP87565_I2C_SLAVE_ADDR 0x61
370#define LP87565_REG_ADDR_BUCK01 0xA
371#define LP87565_REG_ADDR_BUCK23 0xE
372
364/* TPS */ 373/* TPS */
365#define TPS62361_I2C_SLAVE_ADDR 0x60 374#define TPS62361_I2C_SLAVE_ADDR 0x60
366#define TPS62361_REG_ADDR_SET0 0x0 375#define TPS62361_REG_ADDR_SET0 0x0
diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
index 9c8ccb6c83..d06779956f 100644
--- a/arch/arm/include/asm/arch-omap5/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
@@ -31,8 +31,8 @@
31 * OMAP HSMMC register definitions 31 * OMAP HSMMC register definitions
32 */ 32 */
33 33
34#define OMAP_HSMMC1_BASE 0x4809C100 34#define OMAP_HSMMC1_BASE 0x4809C000
35#define OMAP_HSMMC2_BASE 0x480B4100 35#define OMAP_HSMMC2_BASE 0x480B4000
36#define OMAP_HSMMC3_BASE 0x480AD100 36#define OMAP_HSMMC3_BASE 0x480AD000
37 37
38#endif /* MMC_HOST_DEF_H */ 38#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index b5e5519fbd..0fd3d85d29 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -58,11 +58,13 @@
58#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F 58#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
59#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F 59#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
60#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F 60#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
61#define DRA762_CONTROL_ID_CODE_ES1_0 0x0BB5002F
61#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F 62#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
62#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F 63#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F
63#define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F 64#define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F
64#define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F 65#define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F
65#define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F 66#define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F
67#define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F
66 68
67/* UART */ 69/* UART */
68#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) 70#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index c870a72980..fb563ee542 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -35,6 +35,13 @@ struct pad_conf_entry {
35 u32 val; 35 u32 val;
36}; 36};
37 37
38struct omap_hsmmc_pinctrl_state {
39 struct pad_conf_entry *padconf;
40 int npads;
41 struct iodelay_cfg_entry *iodelay;
42 int niodelays;
43};
44
38struct omap_sysinfo { 45struct omap_sysinfo {
39 char *board_string; 46 char *board_string;
40}; 47};
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 3e178be954..951a407515 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -602,6 +602,7 @@ extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
602 602
603extern struct pmic_data tps659038; 603extern struct pmic_data tps659038;
604extern struct pmic_data lp8733; 604extern struct pmic_data lp8733;
605extern struct pmic_data lp87565;
605 606
606void hw_data_init(void); 607void hw_data_init(void);
607 608
@@ -702,6 +703,7 @@ static inline u8 is_omap54xx(void)
702 703
703#define DRA7XX 0x07000000 704#define DRA7XX 0x07000000
704#define DRA72X 0x07200000 705#define DRA72X 0x07200000
706#define DRA76X 0x07600000
705 707
706static inline u8 is_dra7xx(void) 708static inline u8 is_dra7xx(void)
707{ 709{
@@ -714,6 +716,12 @@ static inline u8 is_dra72x(void)
714 extern u32 *const omap_si_rev; 716 extern u32 *const omap_si_rev;
715 return (*omap_si_rev & 0xFFF00000) == DRA72X; 717 return (*omap_si_rev & 0xFFF00000) == DRA72X;
716} 718}
719
720static inline u8 is_dra76x(void)
721{
722 extern u32 *const omap_si_rev;
723 return (*omap_si_rev & 0xFFF00000) == DRA76X;
724}
717#endif 725#endif
718 726
719/* 727/*
@@ -741,11 +749,13 @@ static inline u8 is_dra72x(void)
741#define OMAP5432_ES2_0 0x54320200 749#define OMAP5432_ES2_0 0x54320200
742 750
743/* DRA7XX */ 751/* DRA7XX */
752#define DRA762_ES1_0 0x07620100
744#define DRA752_ES1_0 0x07520100 753#define DRA752_ES1_0 0x07520100
745#define DRA752_ES1_1 0x07520110 754#define DRA752_ES1_1 0x07520110
746#define DRA752_ES2_0 0x07520200 755#define DRA752_ES2_0 0x07520200
747#define DRA722_ES1_0 0x07220100 756#define DRA722_ES1_0 0x07220100
748#define DRA722_ES2_0 0x07220200 757#define DRA722_ES2_0 0x07220200
758#define DRA722_ES2_1 0x07220210
749 759
750/* 760/*
751 * SRAM scratch space entries 761 * SRAM scratch space entries
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 767f8ec50a..abfdc2ef4f 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -26,7 +26,7 @@
26#define OMAP_MMC_H_ 26#define OMAP_MMC_H_
27 27
28struct hsmmc { 28struct hsmmc {
29#ifdef CONFIG_DM_MMC 29#ifndef CONFIG_OMAP34XX
30 unsigned int hl_rev; 30 unsigned int hl_rev;
31 unsigned int hl_hwinfo; 31 unsigned int hl_hwinfo;
32 unsigned int hl_sysconfig; 32 unsigned int hl_sysconfig;
@@ -225,7 +225,9 @@ struct hsmmc {
225 225
226int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, 226int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
227 int wp_gpio); 227 int wp_gpio);
228
229int platform_fixup_disable_uhs_mode(void); 228int platform_fixup_disable_uhs_mode(void);
229struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
230 (struct hsmmc *base, const char *mode);
230void vmmc_pbias_config(uint voltage); 231void vmmc_pbias_config(uint voltage);
232void board_mmc_poweron_ldo(uint voltage);
231#endif /* OMAP_MMC_H_ */ 233#endif /* OMAP_MMC_H_ */
diff --git a/arch/arm/mach-keystone/include/mach/mmc_host_def.h b/arch/arm/mach-keystone/include/mach/mmc_host_def.h
index a5050ac0f1..b8eed7d29b 100644
--- a/arch/arm/mach-keystone/include/mach/mmc_host_def.h
+++ b/arch/arm/mach-keystone/include/mach/mmc_host_def.h
@@ -16,7 +16,7 @@
16 * OMAP HSMMC register definitions 16 * OMAP HSMMC register definitions
17 */ 17 */
18 18
19#define OMAP_HSMMC1_BASE 0x23000100 19#define OMAP_HSMMC1_BASE 0x23000000
20#define OMAP_HSMMC2_BASE 0x23100100 20#define OMAP_HSMMC2_BASE 0x23100000
21 21
22#endif /* K2G_MMC_HOST_DEF_H */ 22#endif /* K2G_MMC_HOST_DEF_H */
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index ce4acc13e0..677e043797 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -684,7 +684,7 @@ int board_eth_init(bd_t *bis)
684 return rv; 684 return rv;
685} 685}
686#endif /* defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) */ 686#endif /* defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) */
687#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 687#if defined(CONFIG_GENERIC_MMC)
688int board_mmc_init(bd_t *bis) 688int board_mmc_init(bd_t *bis)
689{ 689{
690 return omap_mmc_init(1, 0, 0, -1, -1); 690 return omap_mmc_init(1, 0, 0, -1, -1);
diff --git a/board/amazon/kc1/kc1.c b/board/amazon/kc1/kc1.c
index 469a83eeef..b3fa7896c5 100644
--- a/board/amazon/kc1/kc1.c
+++ b/board/amazon/kc1/kc1.c
@@ -166,12 +166,10 @@ int fb_set_reboot_flag(void)
166 return omap_reboot_mode_store("b"); 166 return omap_reboot_mode_store("b");
167} 167}
168 168
169#ifndef CONFIG_SPL_BUILD
170int board_mmc_init(bd_t *bis) 169int board_mmc_init(bd_t *bis)
171{ 170{
172 return omap_mmc_init(1, 0, 0, -1, -1); 171 return omap_mmc_init(1, 0, 0, -1, -1);
173} 172}
174#endif
175 173
176void board_mmc_power_init(void) 174void board_mmc_power_init(void)
177{ 175{
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index 189d903b6e..d3f11a7376 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -372,7 +372,7 @@ void set_muxconf_regs(void)
372 cm_t3730_set_muxconf(); 372 cm_t3730_set_muxconf();
373} 373}
374 374
375#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 375#if defined(CONFIG_GENERIC_MMC)
376#define SB_T35_WP_GPIO 59 376#define SB_T35_WP_GPIO 59
377 377
378int board_mmc_getcd(struct mmc *mmc) 378int board_mmc_getcd(struct mmc *mmc)
diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c
index 8aae248042..d9da6d00d6 100644
--- a/board/compulab/cm_t3517/cm_t3517.c
+++ b/board/compulab/cm_t3517/cm_t3517.c
@@ -115,7 +115,7 @@ int misc_init_r(void)
115 return 0; 115 return 0;
116} 116}
117 117
118#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 118#if defined(CONFIG_GENERIC_MMC)
119#define SB_T35_CD_GPIO 144 119#define SB_T35_CD_GPIO 144
120#define SB_T35_WP_GPIO 59 120#define SB_T35_WP_GPIO 59
121 121
diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c
index b4f5d40654..7b58fcd21f 100644
--- a/board/compulab/cm_t54/cm_t54.c
+++ b/board/compulab/cm_t54/cm_t54.c
@@ -96,7 +96,7 @@ uint mmc_get_env_part(struct mmc *mmc)
96} 96}
97#endif 97#endif
98 98
99#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 99#if defined(CONFIG_GENERIC_MMC)
100#define SB_T54_CD_GPIO 228 100#define SB_T54_CD_GPIO 228
101#define SB_T54_WP_GPIO 229 101#define SB_T54_WP_GPIO 229
102 102
diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c
index 0009452651..029f20b86c 100644
--- a/board/corscience/tricorder/tricorder.c
+++ b/board/corscience/tricorder/tricorder.c
@@ -140,7 +140,7 @@ void set_muxconf_regs(void)
140 MUX_TRICORDER(); 140 MUX_TRICORDER();
141} 141}
142 142
143#if defined(CONFIG_GENERIC_MMC) && !(defined(CONFIG_SPL_BUILD)) 143#if defined(CONFIG_GENERIC_MMC)
144int board_mmc_init(bd_t *bis) 144int board_mmc_init(bd_t *bis)
145{ 145{
146 return omap_mmc_init(0, 0, 0, -1, -1); 146 return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c
index 9671c5aa54..f35c77ba5a 100644
--- a/board/gumstix/duovero/duovero.c
+++ b/board/gumstix/duovero/duovero.c
@@ -110,17 +110,19 @@ void set_muxconf_regs(void)
110 sizeof(struct pad_conf_entry)); 110 sizeof(struct pad_conf_entry));
111} 111}
112 112
113#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 113#if defined(CONFIG_GENERIC_MMC)
114int board_mmc_init(bd_t *bis) 114int board_mmc_init(bd_t *bis)
115{ 115{
116 return omap_mmc_init(0, 0, 0, -1, -1); 116 return omap_mmc_init(0, 0, 0, -1, -1);
117} 117}
118 118
119#if !defined(CONFIG_SPL_BUILD)
119void board_mmc_power_init(void) 120void board_mmc_power_init(void)
120{ 121{
121 twl6030_power_mmc_init(0); 122 twl6030_power_mmc_init(0);
122} 123}
123#endif 124#endif
125#endif
124 126
125#if defined(CONFIG_CMD_NET) 127#if defined(CONFIG_CMD_NET)
126 128
diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c
index 4330cf0ddb..06510b2008 100644
--- a/board/htkw/mcx/mcx.c
+++ b/board/htkw/mcx/mcx.c
@@ -100,7 +100,7 @@ void set_muxconf_regs(void)
100 MUX_MCX(); 100 MUX_MCX();
101} 101}
102 102
103#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) 103#if defined(CONFIG_OMAP_HSMMC)
104int board_mmc_init(bd_t *bis) 104int board_mmc_init(bd_t *bis)
105{ 105{
106 return omap_mmc_init(0, 0, 0, -1, -1); 106 return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index d1a6a6f56f..ec340e038f 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -140,7 +140,7 @@ static void setup_net_chip(void)
140static inline void setup_net_chip(void) {} 140static inline void setup_net_chip(void) {}
141#endif 141#endif
142 142
143#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 143#if defined(CONFIG_GENERIC_MMC)
144int board_mmc_init(bd_t *bis) 144int board_mmc_init(bd_t *bis)
145{ 145{
146 return omap_mmc_init(0, 0, 0, -1, -1); 146 return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c
index 0662449c38..3c0a6db81a 100644
--- a/board/lg/sniper/sniper.c
+++ b/board/lg/sniper/sniper.c
@@ -178,12 +178,10 @@ int fb_set_reboot_flag(void)
178 return omap_reboot_mode_store("b"); 178 return omap_reboot_mode_store("b");
179} 179}
180 180
181#ifndef CONFIG_SPL_BUILD
182int board_mmc_init(bd_t *bis) 181int board_mmc_init(bd_t *bis)
183{ 182{
184 return omap_mmc_init(1, 0, 0, -1, -1); 183 return omap_mmc_init(1, 0, 0, -1, -1);
185} 184}
186#endif
187 185
188void board_mmc_power_init(void) 186void board_mmc_power_init(void)
189{ 187{
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
index 1f1e5aedb0..5819aa582f 100644
--- a/board/logicpd/am3517evm/am3517evm.c
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -152,7 +152,7 @@ void set_muxconf_regs(void)
152 MUX_AM3517EVM(); 152 MUX_AM3517EVM();
153} 153}
154 154
155#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 155#if defined(CONFIG_GENERIC_MMC)
156int board_mmc_init(bd_t *bis) 156int board_mmc_init(bd_t *bis)
157{ 157{
158 return omap_mmc_init(0, 0, 0, -1, -1); 158 return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
index 51d2987566..adba90dbb1 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -252,7 +252,7 @@ int board_late_init(void)
252} 252}
253#endif 253#endif
254 254
255#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 255#if defined(CONFIG_GENERIC_MMC)
256int board_mmc_init(bd_t *bis) 256int board_mmc_init(bd_t *bis)
257{ 257{
258 return omap_mmc_init(0, 0, 0, -1, -1); 258 return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c
index 77e4482906..555f5c0e01 100644
--- a/board/quipos/cairo/cairo.c
+++ b/board/quipos/cairo/cairo.c
@@ -62,7 +62,7 @@ void set_muxconf_regs(void)
62 MUX_CAIRO(); 62 MUX_CAIRO();
63} 63}
64 64
65#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 65#if defined(CONFIG_GENERIC_MMC)
66int board_mmc_init(bd_t *bis) 66int board_mmc_init(bd_t *bis)
67{ 67{
68 return omap_mmc_init(0, 0, 0, -1, -1); 68 return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c
index d51b5d940c..cba48d48fc 100644
--- a/board/technexion/tao3530/tao3530.c
+++ b/board/technexion/tao3530/tao3530.c
@@ -179,7 +179,7 @@ void set_muxconf_regs(void)
179#endif 179#endif
180} 180}
181 181
182#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 182#if defined(CONFIG_GENERIC_MMC)
183int board_mmc_init(bd_t *bis) 183int board_mmc_init(bd_t *bis)
184{ 184{
185 omap_mmc_init(0, 0, 0, -1, -1); 185 omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c
index 48d207fbd4..70c4ce5b8d 100644
--- a/board/technexion/twister/twister.c
+++ b/board/technexion/twister/twister.c
@@ -130,8 +130,7 @@ int board_eth_init(bd_t *bis)
130 return 0; 130 return 0;
131} 131}
132 132
133#if defined(CONFIG_OMAP_HSMMC) && \ 133#if defined(CONFIG_OMAP_HSMMC)
134 !defined(CONFIG_SPL_BUILD)
135int board_mmc_init(bd_t *bis) 134int board_mmc_init(bd_t *bis)
136{ 135{
137 return omap_mmc_init(0, 0, 0, -1, -1); 136 return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c
index c2de1fec62..9307258cba 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -291,8 +291,7 @@ int board_eth_init(bd_t *bis)
291 return 0; 291 return 0;
292} 292}
293 293
294#if defined(CONFIG_OMAP_HSMMC) && \ 294#if defined(CONFIG_OMAP_HSMMC)
295 !defined(CONFIG_SPL_BUILD)
296int board_mmc_init(bd_t *bis) 295int board_mmc_init(bd_t *bis)
297{ 296{
298 return omap_mmc_init(0, 0, 0, -1, -1); 297 return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c
index 8d1c390e5d..faa95d7da8 100644
--- a/board/ti/am3517crane/am3517crane.c
+++ b/board/ti/am3517crane/am3517crane.c
@@ -63,7 +63,7 @@ void set_muxconf_regs(void)
63 MUX_AM3517CRANE(); 63 MUX_AM3517CRANE();
64} 64}
65 65
66#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 66#if defined(CONFIG_GENERIC_MMC)
67int board_mmc_init(bd_t *bis) 67int board_mmc_init(bd_t *bis)
68{ 68{
69 return omap_mmc_init(0, 0, 0, -1, -1); 69 return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 00f05986b4..72c4312837 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -712,7 +712,7 @@ err:
712} 712}
713#endif 713#endif
714 714
715#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 715#if defined(CONFIG_GENERIC_MMC)
716int board_mmc_init(bd_t *bis) 716int board_mmc_init(bd_t *bis)
717{ 717{
718 omap_mmc_init(0, 0, 0, -1, -1); 718 omap_mmc_init(0, 0, 0, -1, -1);
@@ -721,6 +721,67 @@ int board_mmc_init(bd_t *bis)
721} 721}
722#endif 722#endif
723 723
724#if defined(CONFIG_IODELAY_RECALIBRATION) && \
725 (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC))
726
727struct pinctrl_desc {
728 const char *name;
729 struct omap_hsmmc_pinctrl_state *pinctrl;
730};
731
732static struct pinctrl_desc pinctrl_descs_hsmmc1[] = {
733 {"default", &hsmmc1_default},
734 {"hs", &hsmmc1_default},
735 {NULL}
736};
737
738static struct pinctrl_desc pinctrl_descs_hsmmc2_am572[] = {
739 {"default", &hsmmc2_default_hs},
740 {"hs", &hsmmc2_default_hs},
741 {"ddr_1_8v", &hsmmc2_ddr_am572},
742 {NULL}
743};
744
745static struct pinctrl_desc pinctrl_descs_hsmmc2_am571[] = {
746 {"default", &hsmmc2_default_hs},
747 {"hs", &hsmmc2_default_hs},
748 {"ddr_1_8v", &hsmmc2_ddr_am571},
749 {NULL}
750};
751
752struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
753 (struct hsmmc *base, const char *mode)
754{
755 struct pinctrl_desc *p = NULL;
756
757 switch ((uint32_t)base) {
758 case OMAP_HSMMC1_BASE:
759 p = pinctrl_descs_hsmmc1;
760 break;
761 case OMAP_HSMMC2_BASE:
762 if (is_dra72x())
763 p = pinctrl_descs_hsmmc2_am571;
764 else
765 p = pinctrl_descs_hsmmc2_am572;
766 break;
767 default:
768 break;
769 }
770
771 if (!p) {
772 printf("%s no pinctrl defined for MMC@%p\n", __func__,
773 base);
774 return NULL;
775 }
776 while (p->name) {
777 if (strcmp(mode, p->name) == 0)
778 return p->pinctrl;
779 p++;
780 }
781 return NULL;
782}
783#endif
784
724#ifdef CONFIG_OMAP_HSMMC 785#ifdef CONFIG_OMAP_HSMMC
725int platform_fixup_disable_uhs_mode(void) 786int platform_fixup_disable_uhs_mode(void)
726{ 787{
diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h
index aff274c74f..3c99905dd2 100644
--- a/board/ti/am57xx/mux_data.h
+++ b/board/ti/am57xx/mux_data.h
@@ -985,4 +985,136 @@ const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] = {
985}; 985};
986 986
987#endif 987#endif
988
989#if defined(CONFIG_IODELAY_RECALIBRATION) && \
990 (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC))
991
992static struct iodelay_cfg_entry mmc2_iodelay_ddr_am572[] = {
993 {0x18c, 270, 0 /* CFG_GPMC_A19_IN */},
994 {0x1a4, 0, 0 /* CFG_GPMC_A20_IN */},
995 {0x1b0, 170, 0 /* CFG_GPMC_A21_IN */},
996 {0x1bc, 758, 0 /* CFG_GPMC_A22_IN */},
997 {0x1c8, 0, 0 /* CFG_GPMC_A23_IN */},
998 {0x1d4, 81, 0 /* CFG_GPMC_A24_IN */},
999 {0x1e0, 286, 0 /* CFG_GPMC_A25_IN */},
1000 {0x1ec, 0, 0 /* CFG_GPMC_A26_IN */},
1001 {0x1f8, 123, 0 /* CFG_GPMC_A27_IN */},
1002 {0x360, 346, 0 /* CFG_GPMC_CS1_IN */},
1003 {0x190, 0, 0 /* CFG_GPMC_A19_OEN */},
1004 {0x194, 55, 0 /* CFG_GPMC_A19_OUT */},
1005 {0x1a8, 0, 0 /* CFG_GPMC_A20_OEN */},
1006 {0x1ac, 422, 0 /* CFG_GPMC_A20_OUT */},
1007 {0x1b4, 642, 0 /* CFG_GPMC_A21_OEN */},
1008 {0x1b8, 0, 0 /* CFG_GPMC_A21_OUT */},
1009 {0x1c0, 0, 0 /* CFG_GPMC_A22_OEN */},
1010 {0x1c4, 128, 0 /* CFG_GPMC_A22_OUT */},
1011 {0x1d0, 0, 0 /* CFG_GPMC_A23_OUT */},
1012 {0x1d8, 0, 0 /* CFG_GPMC_A24_OEN */},
1013 {0x1dc, 395, 0 /* CFG_GPMC_A24_OUT */},
1014 {0x1e4, 0, 0 /* CFG_GPMC_A25_OEN */},
1015 {0x1e8, 0, 0 /* CFG_GPMC_A25_OUT */},
1016 {0x1f0, 623, 0 /* CFG_GPMC_A26_OEN */},
1017 {0x1f4, 0, 0 /* CFG_GPMC_A26_OUT */},
1018 {0x1fc, 54, 0 /* CFG_GPMC_A27_OEN */},
1019 {0x200, 0, 0 /* CFG_GPMC_A27_OUT */},
1020 {0x364, 0, 0 /* CFG_GPMC_CS1_OEN */},
1021 {0x368, 0, 0 /* CFG_GPMC_CS1_OUT */},
1022};
1023
1024static struct iodelay_cfg_entry mmc2_iodelay_ddr_am571[] = {
1025 {0x18c, 0, 0, /* CFG_GPMC_A19_IN */},
1026 {0x1a4, 121, 0, /* CFG_GPMC_A20_IN */},
1027 {0x1b0, 0, 0, /* CFG_GPMC_A21_IN */},
1028 {0x1bc, 20, 0, /* CFG_GPMC_A22_IN */},
1029 {0x1c8, 108, 0, /* CFG_GPMC_A23_IN */},
1030 {0x1d4, 31, 0, /* CFG_GPMC_A24_IN */},
1031 {0x1e0, 0, 0, /* CFG_GPMC_A25_IN */},
1032 {0x1ec, 24, 0, /* CFG_GPMC_A26_IN */},
1033 {0x1f8, 0, 0, /* CFG_GPMC_A27_IN */},
1034 {0x360, 0, 0, /* CFG_GPMC_CS1_IN */},
1035 {0x194, 152, 0, /* CFG_GPMC_A19_OUT */},
1036 {0x1ac, 206, 0, /* CFG_GPMC_A20_OUT */},
1037 {0x1b8, 78, 0, /* CFG_GPMC_A21_OUT */},
1038 {0x1c4, 2, 0, /* CFG_GPMC_A22_OUT */},
1039 {0x1d0, 266, 0, /* CFG_GPMC_A23_OUT */},
1040 {0x1dc, 0, 0, /* CFG_GPMC_A24_OUT */},
1041 {0x1e8, 0, 0, /* CFG_GPMC_A25_OUT */},
1042 {0x1f4, 43, 0, /* CFG_GPMC_A26_OUT */},
1043 {0x200, 0, 0, /* CFG_GPMC_A27_OUT */},
1044 {0x368, 0, 0, /* CFG_GPMC_CS1_OUT */},
1045 {0x190, 0, 0, /* CFG_GPMC_A19_OEN */},
1046 {0x1a8, 0, 0, /* CFG_GPMC_A20_OEN */},
1047 {0x1b4, 0, 0, /* CFG_GPMC_A21_OEN */},
1048 {0x1c0, 0, 0, /* CFG_GPMC_A22_OEN */},
1049 {0x1d8, 0, 0, /* CFG_GPMC_A24_OEN */},
1050 {0x1e4, 0, 0, /* CFG_GPMC_A25_OEN */},
1051 {0x1f0, 0, 0, /* CFG_GPMC_A26_OEN */},
1052 {0x1fc, 0, 0, /* CFG_GPMC_A27_OEN */},
1053 {0x364, 0, 0, /* CFG_GPMC_CS1_OEN */},
1054};
1055
1056static struct pad_conf_entry hsmmc1_default_padconf[] = {
1057 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP) /* mmc1_clk.clk */},
1058 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP) /* mmc1_cmd.cmd */},
1059 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat0.dat0 */},
1060 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat1.dat1 */},
1061 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat2.dat2 */},
1062 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat3.dat3 */},
1063};
1064
1065static struct pad_conf_entry mmc2_pins_ddr[] = {
1066 {GPMC_A23, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a23.mmc2_clk */},
1067 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_cs1.mmc2_cmd */},
1068 {GPMC_A24, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a24.mmc2_dat0 */},
1069 {GPMC_A25, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a25.mmc2_dat1 */},
1070 {GPMC_A26, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a26.mmc2_dat2 */},
1071 {GPMC_A27, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a27.mmc2_dat3 */},
1072 {GPMC_A19, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a19.mmc2_dat4 */},
1073 {GPMC_A20, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a20.mmc2_dat5 */},
1074 {GPMC_A21, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a21.mmc2_dat6 */},
1075 {GPMC_A22, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a22.mmc2_dat7 */},
1076};
1077
1078static struct pad_conf_entry mmc2_pins_default_hs[] = {
1079 {GPMC_A23, (M1 | PIN_INPUT_PULLUP) /* g pmc_a23.mmc2_clk */},
1080 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP) /* gpmc_cs1.mmc2_cmd */},
1081 {GPMC_A24, (M1 | PIN_INPUT_PULLUP) /* gpmc_a24.mmc2_dat0 */},
1082 {GPMC_A25, (M1 | PIN_INPUT_PULLUP) /* gpmc_a25.mmc2_dat1 */},
1083 {GPMC_A26, (M1 | PIN_INPUT_PULLUP) /* gpmc_a26.mmc2_dat2 */},
1084 {GPMC_A27, (M1 | PIN_INPUT_PULLUP) /* gpmc_a27.mmc2_dat3 */},
1085 {GPMC_A19, (M1 | PIN_INPUT_PULLUP) /* gpmc_a19.mmc2_dat4 */},
1086 {GPMC_A20, (M1 | PIN_INPUT_PULLUP) /* gpmc_a20.mmc2_dat5 */},
1087 {GPMC_A21, (M1 | PIN_INPUT_PULLUP) /* gpmc_a21.mmc2_dat6 */},
1088 {GPMC_A22, (M1 | PIN_INPUT_PULLUP) /* gpmc_a22.mmc2_dat7 */},
1089};
1090
1091static struct omap_hsmmc_pinctrl_state hsmmc1_default = {
1092 .padconf = hsmmc1_default_padconf,
1093 .npads = ARRAY_SIZE(hsmmc1_default_padconf),
1094 .iodelay = NULL,
1095 .niodelays = 0,
1096};
1097
1098static struct omap_hsmmc_pinctrl_state hsmmc2_default_hs = {
1099 .padconf = mmc2_pins_default_hs,
1100 .npads = ARRAY_SIZE(mmc2_pins_default_hs),
1101 .iodelay = NULL,
1102 .niodelays = 0,
1103};
1104
1105static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_am572 = {
1106 .padconf = mmc2_pins_ddr,
1107 .npads = ARRAY_SIZE(mmc2_pins_ddr),
1108 .iodelay = mmc2_iodelay_ddr_am572,
1109 .niodelays = ARRAY_SIZE(mmc2_iodelay_ddr_am572),
1110};
1111
1112static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_am571 = {
1113 .padconf = mmc2_pins_ddr,
1114 .npads = ARRAY_SIZE(mmc2_pins_ddr),
1115 .iodelay = mmc2_iodelay_ddr_am571,
1116 .niodelays = ARRAY_SIZE(mmc2_iodelay_ddr_am571),
1117};
1118
1119#endif
988#endif /* _MUX_DATA_BEAGLE_X15_H_ */ 1120#endif /* _MUX_DATA_BEAGLE_X15_H_ */
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 0ed4f52771..ddcfe7d46d 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -523,7 +523,7 @@ void set_muxconf_regs(void)
523 MUX_BEAGLE(); 523 MUX_BEAGLE();
524} 524}
525 525
526#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 526#if defined(CONFIG_GENERIC_MMC)
527int board_mmc_init(bd_t *bis) 527int board_mmc_init(bd_t *bis)
528{ 528{
529 return omap_mmc_init(0, 0, 0, -1, -1); 529 return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 1b8c898c19..145f044f88 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -35,6 +35,7 @@
35#include "mux_data.h" 35#include "mux_data.h"
36#include "../common/board_detect.h" 36#include "../common/board_detect.h"
37 37
38#define board_is_dra76x_evm() board_ti_is("DRA76/7x")
38#define board_is_dra74x_evm() board_ti_is("5777xCPU") 39#define board_is_dra74x_evm() board_ti_is("5777xCPU")
39#define board_is_dra72x_evm() board_ti_is("DRA72x-T") 40#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
40#define board_is_dra71x_evm() board_ti_is("DRA79x,D") 41#define board_is_dra71x_evm() board_ti_is("DRA79x,D")
@@ -210,6 +211,56 @@ const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
210 .emif_rd_wr_exec_thresh = 0x00000305 211 .emif_rd_wr_exec_thresh = 0x00000305
211}; 212};
212 213
214const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
215 .sdram_config_init = 0x61862B32,
216 .sdram_config = 0x61862B32,
217 .sdram_config2 = 0x00000000,
218 .ref_ctrl = 0x0000514C,
219 .ref_ctrl_final = 0x0000144A,
220 .sdram_tim1 = 0xD113783C,
221 .sdram_tim2 = 0x30B47FE3,
222 .sdram_tim3 = 0x409F8AD8,
223 .read_idle_ctrl = 0x00050000,
224 .zq_config = 0x5007190B,
225 .temp_alert_config = 0x00000000,
226 .emif_ddr_phy_ctlr_1_init = 0x0824400D,
227 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
228 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
229 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
230 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
231 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
232 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
233 .emif_rd_wr_lvl_rmp_win = 0x00000000,
234 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
235 .emif_rd_wr_lvl_ctl = 0x00000000,
236 .emif_rd_wr_exec_thresh = 0x00000305
237};
238
239const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
240 .sdram_config_init = 0x61862B32,
241 .sdram_config = 0x61862B32,
242 .sdram_config2 = 0x00000000,
243 .ref_ctrl = 0x0000514C,
244 .ref_ctrl_final = 0x0000144A,
245 .sdram_tim1 = 0xD113781C,
246 .sdram_tim2 = 0x30B47FE3,
247 .sdram_tim3 = 0x409F8AD8,
248 .read_idle_ctrl = 0x00050000,
249 .zq_config = 0x5007190B,
250 .temp_alert_config = 0x00000000,
251 .emif_ddr_phy_ctlr_1_init = 0x0824400D,
252 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
253 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
254 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
255 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
256 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
257 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
258 .emif_rd_wr_lvl_rmp_win = 0x00000000,
259 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
260 .emif_rd_wr_lvl_ctl = 0x00000000,
261 .emif_rd_wr_exec_thresh = 0x00000305
262};
263
213void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 264void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
214{ 265{
215 u64 ram_size; 266 u64 ram_size;
@@ -235,8 +286,15 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
235 break; 286 break;
236 } 287 }
237 break; 288 break;
289 case DRA762_ES1_0:
290 if (emif_nr == 1)
291 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
292 else
293 *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
294 break;
238 case DRA722_ES1_0: 295 case DRA722_ES1_0:
239 case DRA722_ES2_0: 296 case DRA722_ES2_0:
297 case DRA722_ES2_1:
240 if (ram_size < CONFIG_MAX_MEM_MAPPED) 298 if (ram_size < CONFIG_MAX_MEM_MAPPED)
241 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; 299 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
242 else 300 else
@@ -290,6 +348,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
290 ram_size = board_ti_get_emif_size(); 348 ram_size = board_ti_get_emif_size();
291 349
292 switch (omap_revision()) { 350 switch (omap_revision()) {
351 case DRA762_ES1_0:
293 case DRA752_ES1_0: 352 case DRA752_ES1_0:
294 case DRA752_ES1_1: 353 case DRA752_ES1_1:
295 case DRA752_ES2_0: 354 case DRA752_ES2_0:
@@ -300,6 +359,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
300 break; 359 break;
301 case DRA722_ES1_0: 360 case DRA722_ES1_0:
302 case DRA722_ES2_0: 361 case DRA722_ES2_0:
362 case DRA722_ES2_1:
303 default: 363 default:
304 if (ram_size < CONFIG_MAX_MEM_MAPPED) 364 if (ram_size < CONFIG_MAX_MEM_MAPPED)
305 *dmm_lisa_regs = &lisa_map_2G_x_2; 365 *dmm_lisa_regs = &lisa_map_2G_x_2;
@@ -357,6 +417,54 @@ struct vcores_data dra752_volts = {
357 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 417 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
358}; 418};
359 419
420struct vcores_data dra76x_volts = {
421 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
422 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
423 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
424 .mpu.addr = LP87565_REG_ADDR_BUCK01,
425 .mpu.pmic = &lp87565,
426 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
427
428 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
429 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
430 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
431 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
432 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
433 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
434 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
435 .eve.addr = TPS65917_REG_ADDR_SMPS1,
436 .eve.pmic = &tps659038,
437 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
438
439 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
440 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
441 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
442 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
443 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
444 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
445 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
446 .gpu.addr = LP87565_REG_ADDR_BUCK23,
447 .gpu.pmic = &lp87565,
448 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
449
450 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
451 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
452 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
453 .core.addr = TPS65917_REG_ADDR_SMPS3,
454 .core.pmic = &tps659038,
455
456 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
457 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
458 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
459 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
460 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
461 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
462 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
463 .iva.addr = TPS65917_REG_ADDR_SMPS4,
464 .iva.pmic = &tps659038,
465 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
466};
467
360struct vcores_data dra722_volts = { 468struct vcores_data dra722_volts = {
361 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 469 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
362 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 470 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
@@ -439,14 +547,18 @@ struct vcores_data dra718_volts = {
439 * and are powered by BUCK1 of LP873X PMIC 547 * and are powered by BUCK1 of LP873X PMIC
440 */ 548 */
441 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 549 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
550 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
442 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 551 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
552 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
443 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 553 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
444 .eve.addr = LP873X_REG_ADDR_BUCK1, 554 .eve.addr = LP873X_REG_ADDR_BUCK1,
445 .eve.pmic = &lp8733, 555 .eve.pmic = &lp8733,
446 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 556 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
447 557
448 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 558 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
559 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
449 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 560 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
561 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
450 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 562 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
451 .iva.addr = LP873X_REG_ADDR_BUCK1, 563 .iva.addr = LP873X_REG_ADDR_BUCK1,
452 .iva.pmic = &lp8733, 564 .iva.pmic = &lp8733,
@@ -457,27 +569,44 @@ int get_voltrail_opp(int rail_offset)
457{ 569{
458 int opp; 570 int opp;
459 571
460 /*
461 * DRA71x supports only OPP_NOM.
462 */
463 if (board_is_dra71x_evm())
464 return OPP_NOM;
465
466 switch (rail_offset) { 572 switch (rail_offset) {
467 case VOLT_MPU: 573 case VOLT_MPU:
468 opp = DRA7_MPU_OPP; 574 opp = DRA7_MPU_OPP;
575 /* DRA71x supports only OPP_NOM for MPU */
576 if (board_is_dra71x_evm())
577 opp = OPP_NOM;
469 break; 578 break;
470 case VOLT_CORE: 579 case VOLT_CORE:
471 opp = DRA7_CORE_OPP; 580 opp = DRA7_CORE_OPP;
581 /* DRA71x supports only OPP_NOM for CORE */
582 if (board_is_dra71x_evm())
583 opp = OPP_NOM;
472 break; 584 break;
473 case VOLT_GPU: 585 case VOLT_GPU:
474 opp = DRA7_GPU_OPP; 586 opp = DRA7_GPU_OPP;
587 /* DRA71x supports only OPP_NOM for GPU */
588 if (board_is_dra71x_evm())
589 opp = OPP_NOM;
475 break; 590 break;
476 case VOLT_EVE: 591 case VOLT_EVE:
477 opp = DRA7_DSPEVE_OPP; 592 opp = DRA7_DSPEVE_OPP;
593 /*
594 * DRA71x does not support OPP_OD for EVE.
595 * If OPP_OD is selected by menuconfig, fallback
596 * to OPP_NOM.
597 */
598 if (board_is_dra71x_evm() && opp == OPP_OD)
599 opp = OPP_NOM;
478 break; 600 break;
479 case VOLT_IVA: 601 case VOLT_IVA:
480 opp = DRA7_IVA_OPP; 602 opp = DRA7_IVA_OPP;
603 /*
604 * DRA71x does not support OPP_OD for IVA.
605 * If OPP_OD is selected by menuconfig, fallback
606 * to OPP_NOM.
607 */
608 if (board_is_dra71x_evm() && opp == OPP_OD)
609 opp = OPP_NOM;
481 break; 610 break;
482 default: 611 default:
483 opp = OPP_NOM; 612 opp = OPP_NOM;
@@ -538,6 +667,8 @@ int board_late_init(void)
538 name = "dra71x"; 667 name = "dra71x";
539 else 668 else
540 name = "dra72x"; 669 name = "dra72x";
670 } else if (is_dra76x()) {
671 name = "dra76x";
541 } else { 672 } else {
542 name = "dra7xx"; 673 name = "dra7xx";
543 } 674 }
@@ -586,6 +717,8 @@ void do_board_detect(void)
586 bname = "DRA72x EVM"; 717 bname = "DRA72x EVM";
587 } else if (board_is_dra71x_evm()) { 718 } else if (board_is_dra71x_evm()) {
588 bname = "DRA71x EVM"; 719 bname = "DRA71x EVM";
720 } else if (board_is_dra76x_evm()) {
721 bname = "DRA76x EVM";
589 } else { 722 } else {
590 /* If EEPROM is not populated */ 723 /* If EEPROM is not populated */
591 if (is_dra72x()) 724 if (is_dra72x())
@@ -608,6 +741,8 @@ void vcores_update(void)
608 *omap_vcores = &dra722_volts; 741 *omap_vcores = &dra722_volts;
609 } else if (board_is_dra71x_evm()) { 742 } else if (board_is_dra71x_evm()) {
610 *omap_vcores = &dra718_volts; 743 *omap_vcores = &dra718_volts;
744 } else if (board_is_dra76x_evm()) {
745 *omap_vcores = &dra76x_volts;
611 } else { 746 } else {
612 /* If EEPROM is not populated */ 747 /* If EEPROM is not populated */
613 if (is_dra72x()) 748 if (is_dra72x())
@@ -634,6 +769,7 @@ void recalibrate_iodelay(void)
634 switch (omap_revision()) { 769 switch (omap_revision()) {
635 case DRA722_ES1_0: 770 case DRA722_ES1_0:
636 case DRA722_ES2_0: 771 case DRA722_ES2_0:
772 case DRA722_ES2_1:
637 pads = dra72x_core_padconf_array_common; 773 pads = dra72x_core_padconf_array_common;
638 npads = ARRAY_SIZE(dra72x_core_padconf_array_common); 774 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
639 if (board_is_dra71x_evm()) { 775 if (board_is_dra71x_evm()) {
@@ -662,6 +798,12 @@ void recalibrate_iodelay(void)
662 iodelay = dra742_es1_1_iodelay_cfg_array; 798 iodelay = dra742_es1_1_iodelay_cfg_array;
663 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); 799 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
664 break; 800 break;
801 case DRA762_ES1_0:
802 pads = dra76x_core_padconf_array;
803 npads = ARRAY_SIZE(dra76x_core_padconf_array);
804 iodelay = dra76x_es1_0_iodelay_cfg_array;
805 niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
806 break;
665 default: 807 default:
666 case DRA752_ES2_0: 808 case DRA752_ES2_0:
667 pads = dra74x_core_padconf_array; 809 pads = dra74x_core_padconf_array;
@@ -694,16 +836,115 @@ err:
694} 836}
695#endif 837#endif
696 838
697#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 839#if defined(CONFIG_GENERIC_MMC)
698int board_mmc_init(bd_t *bis) 840int board_mmc_init(bd_t *bis)
699{ 841{
700 omap_mmc_init(0, 0, 0, -1, -1); 842 omap_mmc_init(0, 0, 0, -1, -1);
701 omap_mmc_init(1, 0, 0, -1, -1); 843 omap_mmc_init(1, 0, 0, -1, -1);
702 return 0; 844 return 0;
703} 845}
846
847void board_mmc_poweron_ldo(uint voltage)
848{
849 if (board_is_dra71x_evm()) {
850 if (voltage == LDO_VOLT_3V0)
851 voltage = 0x19;
852 else if (voltage == LDO_VOLT_1V8)
853 voltage = 0xa;
854 lp873x_mmc1_poweron_ldo(voltage);
855 } else if (board_is_dra76x_evm()) {
856 palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
857 } else {
858 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
859 }
860}
704#endif 861#endif
705 862
706#ifdef CONFIG_OMAP_HSMMC 863#ifdef CONFIG_OMAP_HSMMC
864#if defined(CONFIG_IODELAY_RECALIBRATION) && \
865 (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC))
866
867struct pinctrl_desc {
868 const char *name;
869 struct omap_hsmmc_pinctrl_state *pinctrl;
870};
871
872static struct pinctrl_desc pinctrl_descs_hsmmc1[] = {
873 {"default", &hsmmc1_default},
874 {"hs", &hsmmc1_default},
875 {NULL}
876};
877
878static struct pinctrl_desc pinctrl_descs_hsmmc2_rev20[] = {
879 {"default", &hsmmc2_default_hs},
880 {"hs", &hsmmc2_default_hs},
881 {"ddr_1_8v", &hsmmc2_ddr_1v8_rev20},
882 {"hs200_1_8v", &hsmmc2_hs200_1v8_rev20},
883 {NULL}
884};
885
886static struct pinctrl_desc pinctrl_descs_hsmmc2_rev11[] = {
887 {"default", &hsmmc2_default_hs},
888 {"hs", &hsmmc2_default_hs},
889 {"ddr_1_8v", &hsmmc2_ddr_1v8_rev11},
890 {"hs200_1_8v", &hsmmc2_hs200_1v8_rev11},
891 {NULL}
892};
893
894static struct pinctrl_desc pinctrl_descs_hsmmc2_dra72x[] = {
895 {"default", &hsmmc2_default_hs},
896 {"hs", &hsmmc2_default_hs},
897 {"ddr_1_8v", &hsmmc2_ddr_1v8_dra72},
898 {"hs200_1_8v", &hsmmc2_hs200_1v8_dra72},
899 {NULL}
900};
901
902static struct pinctrl_desc pinctrl_descs_hsmmc2_dra76x[] = {
903 {"default", &hsmmc2_default_hs},
904 {"hs", &hsmmc2_default_hs},
905 {"ddr_1_8v", &hsmmc2_default_hs},
906 {"hs200_1_8v", &hsmmc2_hs200_1v8_dra76},
907 {NULL}
908};
909
910struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
911 (struct hsmmc *base, const char *mode)
912{
913 struct pinctrl_desc *p = NULL;
914
915 switch ((uint32_t)base) {
916 case OMAP_HSMMC1_BASE:
917 p = pinctrl_descs_hsmmc1;
918 break;
919 case OMAP_HSMMC2_BASE:
920 if ((omap_revision() == DRA752_ES1_0) ||
921 (omap_revision() == DRA752_ES1_1))
922 p = pinctrl_descs_hsmmc2_rev11;
923 else if (is_dra72x())
924 p = pinctrl_descs_hsmmc2_dra72x;
925 else if (is_dra76x())
926 p = pinctrl_descs_hsmmc2_dra76x;
927 else if (is_dra7xx())
928 p = pinctrl_descs_hsmmc2_rev20;
929 break;
930 default:
931 break;
932 }
933
934 if (!p) {
935 printf("%s no pinctrl defined for MMC@%p\n", __func__,
936 base);
937 return NULL;
938 }
939 while (p->name) {
940 if (strcmp(mode, p->name) == 0)
941 return p->pinctrl;
942 p++;
943 }
944 return NULL;
945}
946#endif
947
707int platform_fixup_disable_uhs_mode(void) 948int platform_fixup_disable_uhs_mode(void)
708{ 949{
709 return omap_revision() == DRA752_ES1_1; 950 return omap_revision() == DRA752_ES1_1;
@@ -942,8 +1183,8 @@ static inline void vtt_regulator_enable(void)
942 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 1183 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
943 return; 1184 return;
944 1185
945 /* Do not enable VTT for DRA722 */ 1186 /* Do not enable VTT for DRA722 or DRA76x */
946 if (is_dra72x()) 1187 if (is_dra72x() || is_dra76x())
947 return; 1188 return;
948 1189
949 /* 1190 /*
@@ -974,7 +1215,9 @@ int board_fit_config_name_match(const char *name)
974 } else if (!strcmp(name, "dra72-evm")) { 1215 } else if (!strcmp(name, "dra72-evm")) {
975 return 0; 1216 return 0;
976 } 1217 }
977 } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) { 1218 } else if (is_dra76x() && !strcmp(name, "dra76-evm")) {
1219 return 0;
1220 } else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) {
978 return 0; 1221 return 0;
979 } 1222 }
980 1223
diff --git a/board/ti/dra7xx/lateattach.c b/board/ti/dra7xx/lateattach.c
index f294806fd3..14e152e8d1 100644
--- a/board/ti/dra7xx/lateattach.c
+++ b/board/ti/dra7xx/lateattach.c
@@ -171,6 +171,11 @@
171#define DRA7_PGTBL_BASE_DSP1 0xbfc10000 171#define DRA7_PGTBL_BASE_DSP1 0xbfc10000
172#define DRA7_PGTBL_BASE_DSP2 0xbfc18000 172#define DRA7_PGTBL_BASE_DSP2 0xbfc18000
173 173
174#define DRA7_PGTBL_BASE_IPU1 0xbfc00000
175#define DRA7_PGTBL_BASE_IPU2 0xbfc08000
176#define DRA7_PGTBL_BASE_DSP1 0xbfc10000
177#define DRA7_PGTBL_BASE_DSP2 0xbfc18000
178
174/* 179/*
175 * The page table (32 KB) is placed at the end of the CMA reserved area. 180 * The page table (32 KB) is placed at the end of the CMA reserved area.
176 * It's possible that this location is needed by the firmware (in which 181 * It's possible that this location is needed by the firmware (in which
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 731c5521af..3fe52b19b2 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -448,6 +448,26 @@ const struct pad_conf_entry dra71x_core_padconf_array[] = {
448 {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */ 448 {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
449 {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */ 449 {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
450 {WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */ 450 {WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */
451#ifdef CONFIG_DRA7XX_JAMR3
452 {XREF_CLK1, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.atl_clk1 */
453 {XREF_CLK3, (M14 | PIN_INPUT)}, /* xref_clk3.gpio6_20 */
454 {MCASP1_AXR8, (M1 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp1_axr8.mcasp6_axr0 */
455 {MCASP1_AXR9, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.mcasp6_axr1 */
456 {MCASP1_AXR10, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.mcasp6_aclkx */
457 {MCASP1_AXR11, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr11.mcasp6_fsx */
458 {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* mcasp2_aclkx.mcasp2_aclkx */
459 {MCASP2_FSX, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE9)}, /* mcasp2_fsx.mcasp2_fsx */
460 {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr0.mcasp2_axr0 */
461 {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr1.mcasp2_axr1 */
462 {MCASP2_AXR2, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE9)}, /* mcasp2_axr2.mcasp2_axr2 */
463 {MCASP2_AXR3, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE9)}, /* mcasp2_axr3.mcasp2_axr3 */
464 {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr4.mcasp2_axr4 */
465 {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr5.mcasp2_axr5 */
466 {MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr6.mcasp2_axr6 */
467 {MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr7.mcasp2_axr7 */
468 {MCASP4_ACLKX, (M4 | PIN_INPUT_PULLUP)},/* mcasp4_aclkx.i2c4_sda */
469 {MCASP4_FSX, (M4 | PIN_INPUT_PULLUP)}, /* mcasp4_fsx.i2c4_scl */
470#endif
451}; 471};
452 472
453const struct pad_conf_entry early_padconf[] = { 473const struct pad_conf_entry early_padconf[] = {
@@ -846,6 +866,194 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = {
846 866
847}; 867};
848 868
869const struct pad_conf_entry dra76x_core_padconf_array[] = {
870 {GPMC_AD0, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad0.vout3_d0 */
871 {GPMC_AD1, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad1.vout3_d1 */
872 {GPMC_AD2, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad2.vout3_d2 */
873 {GPMC_AD3, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad3.vout3_d3 */
874 {GPMC_AD4, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad4.vout3_d4 */
875 {GPMC_AD5, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad5.vout3_d5 */
876 {GPMC_AD6, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad6.vout3_d6 */
877 {GPMC_AD7, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad7.vout3_d7 */
878 {GPMC_AD8, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad8.vout3_d8 */
879 {GPMC_AD9, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad9.vout3_d9 */
880 {GPMC_AD10, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad10.vout3_d10 */
881 {GPMC_AD11, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad11.vout3_d11 */
882 {GPMC_AD12, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad12.vout3_d12 */
883 {GPMC_AD13, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad13.vout3_d13 */
884 {GPMC_AD14, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad14.vout3_d14 */
885 {GPMC_AD15, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad15.vout3_d15 */
886 {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vout3_d16 */
887 {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vout3_d17 */
888 {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vout3_d18 */
889 {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vout3_d19 */
890 {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vout3_d20 */
891 {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vout3_d21 */
892 {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vout3_d22 */
893 {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vout3_d23 */
894 {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vout3_hsync */
895 {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vout3_vsync */
896 {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vout3_de */
897 {GPMC_A11, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a11.gpio2_1 */
898 {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */
899 {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
900 {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
901 {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
902 {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
903 {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
904 {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
905 {GPMC_A19, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a19.mmc2_dat4 */
906 {GPMC_A20, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a20.mmc2_dat5 */
907 {GPMC_A21, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a21.mmc2_dat6 */
908 {GPMC_A22, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a22.mmc2_dat7 */
909 {GPMC_A23, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a23.mmc2_clk */
910 {GPMC_A24, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a24.mmc2_dat0 */
911 {GPMC_A25, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a25.mmc2_dat1 */
912 {GPMC_A26, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a26.mmc2_dat2 */
913 {GPMC_A27, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a27.mmc2_dat3 */
914 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
915 {GPMC_CS0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_cs0.gpmc_cs0 */
916 {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
917 {GPMC_CS3, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs3.vout3_clk */
918 {GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpmc_advn_ale */
919 {GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpmc_oen_ren */
920 {GPMC_WEN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpmc_wen */
921 {GPMC_BEN0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_ben0.gpmc_ben0 */
922 {GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpmc_wait0 */
923 {VIN1A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin1a_fld0.gpio3_1 */
924 {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_clk0.vin2a_clk0 */
925 {VIN2A_DE0, (M15 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_de0.Driveroff */
926 {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */
927 {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_hsync0.vin2a_hsync0 */
928 {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_vsync0.vin2a_vsync0 */
929 {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d0.vin2a_d0 */
930 {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d1.vin2a_d1 */
931 {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d2.vin2a_d2 */
932 {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d3.vin2a_d3 */
933 {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d4.vin2a_d4 */
934 {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.vin2a_d5 */
935 {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d6.vin2a_d6 */
936 {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d7.vin2a_d7 */
937 {VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d8.vin2a_d8 */
938 {VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d9.vin2a_d9 */
939 {VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d10.vin2a_d10 */
940 {VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d11.vin2a_d11 */
941 {VIN2A_D12, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
942 {VIN2A_D13, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
943 {VIN2A_D14, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
944 {VIN2A_D15, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
945 {VIN2A_D16, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
946 {VIN2A_D17, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
947 {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
948 {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
949 {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
950 {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
951 {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
952 {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
953 {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
954 {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_de.vout1_de */
955 {VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)}, /* vout1_fld.gpio4_21 */
956 {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
957 {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
958 {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
959 {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
960 {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
961 {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
962 {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
963 {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
964 {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
965 {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
966 {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
967 {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
968 {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
969 {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
970 {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
971 {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
972 {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
973 {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
974 {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
975 {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
976 {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
977 {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
978 {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
979 {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
980 {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
981 {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
982 {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
983 {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
984 {RGMII0_TXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
985 {RGMII0_TXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
986 {RGMII0_TXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
987 {RGMII0_TXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
988 {RGMII0_TXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
989 {RGMII0_TXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
990 {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
991 {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
992 {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
993 {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
994 {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
995 {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
996 {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
997 {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
998 {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
999 {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
1000 {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
1001 {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
1002 {MCASP1_ACLKX, (M14 | 0x00070000)}, /* mcasp1_aclkx.gpio7_31 */
1003 {MCASP1_FSX, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.gpio7_30 */
1004 {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
1005 {MCASP1_AXR1, (M10 | 0x000f0000)}, /* mcasp1_axr1.i2c5_scl */
1006 {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
1007 {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
1008 {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
1009 {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
1010 {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
1011 {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
1012 {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
1013 {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
1014 {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
1015 {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
1016 {MCASP2_ACLKR, (M15 | PIN_INPUT_PULLUP)}, /* mcasp2_aclkr.Driveroff */
1017 {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
1018 {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
1019 {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
1020 {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
1021 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
1022 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
1023 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
1024 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
1025 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
1026 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
1027 {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */
1028 {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
1029 {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
1030 {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
1031 {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
1032 {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
1033 {SPI1_CS2, (M6 | 0x000f0000)}, /* spi1_cs2.hdmi1_hpd */
1034 {SPI1_CS3, (M6 | 0x000f0000)}, /* spi1_cs3.hdmi1_cec */
1035 {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
1036 {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
1037 {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
1038 {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
1039 {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
1040 {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */
1041 {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
1042 {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
1043 {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
1044 {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
1045 {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */
1046 {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
1047 {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
1048 {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
1049 {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
1050 {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
1051 {WAKEUP0, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_0 */
1052 {WAKEUP1, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_1 */
1053 {WAKEUP2, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq2 */
1054 {WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */
1055};
1056
849#ifdef CONFIG_IODELAY_RECALIBRATION 1057#ifdef CONFIG_IODELAY_RECALIBRATION
850const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = { 1058const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = {
851 {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ 1059 {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
@@ -1057,6 +1265,402 @@ const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = {
1057#endif 1265#endif
1058 1266
1059}; 1267};
1268
1269const struct iodelay_cfg_entry dra76x_es1_0_iodelay_cfg_array[] = {
1270 {0x011C, 787, 0}, /* CFG_GPMC_A0_OUT */
1271 {0x0128, 1181, 0}, /* CFG_GPMC_A10_OUT */
1272 {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
1273 {0x0150, 2149, 1052}, /* CFG_GPMC_A14_IN */
1274 {0x015C, 2121, 997}, /* CFG_GPMC_A15_IN */
1275 {0x0168, 2159, 1134}, /* CFG_GPMC_A16_IN */
1276 {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
1277 {0x0174, 2135, 1085}, /* CFG_GPMC_A17_IN */
1278 {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
1279 {0x01A0, 592, 0}, /* CFG_GPMC_A1_OUT */
1280 {0x020C, 641, 0}, /* CFG_GPMC_A2_OUT */
1281 {0x0218, 1481, 0}, /* CFG_GPMC_A3_OUT */
1282 {0x0224, 1775, 0}, /* CFG_GPMC_A4_OUT */
1283 {0x0230, 785, 0}, /* CFG_GPMC_A5_OUT */
1284 {0x023C, 848, 0}, /* CFG_GPMC_A6_OUT */
1285 {0x0248, 851, 0}, /* CFG_GPMC_A7_OUT */
1286 {0x0254, 1783, 0}, /* CFG_GPMC_A8_OUT */
1287 {0x0260, 951, 0}, /* CFG_GPMC_A9_OUT */
1288 {0x026C, 1091, 0}, /* CFG_GPMC_AD0_OUT */
1289 {0x0278, 1027, 0}, /* CFG_GPMC_AD10_OUT */
1290 {0x0284, 824, 0}, /* CFG_GPMC_AD11_OUT */
1291 {0x0290, 1196, 0}, /* CFG_GPMC_AD12_OUT */
1292 {0x029C, 754, 0}, /* CFG_GPMC_AD13_OUT */
1293 {0x02A8, 665, 0}, /* CFG_GPMC_AD14_OUT */
1294 {0x02B4, 1027, 0}, /* CFG_GPMC_AD15_OUT */
1295 {0x02C0, 937, 0}, /* CFG_GPMC_AD1_OUT */
1296 {0x02CC, 1168, 0}, /* CFG_GPMC_AD2_OUT */
1297 {0x02D8, 872, 0}, /* CFG_GPMC_AD3_OUT */
1298 {0x02E4, 1092, 0}, /* CFG_GPMC_AD4_OUT */
1299 {0x02F0, 576, 0}, /* CFG_GPMC_AD5_OUT */
1300 {0x02FC, 1113, 0}, /* CFG_GPMC_AD6_OUT */
1301 {0x0308, 943, 0}, /* CFG_GPMC_AD7_OUT */
1302 {0x0314, 0, 0}, /* CFG_GPMC_AD8_OUT */
1303 {0x0320, 0, 0}, /* CFG_GPMC_AD9_OUT */
1304 {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
1305 {0x0380, 1801, 948}, /* CFG_GPMC_CS3_OUT */
1306 {0x06F0, 451, 0}, /* CFG_RGMII0_RXC_IN */
1307 {0x06FC, 127, 1571}, /* CFG_RGMII0_RXCTL_IN */
1308 {0x0708, 165, 1178}, /* CFG_RGMII0_RXD0_IN */
1309 {0x0714, 136, 1302}, /* CFG_RGMII0_RXD1_IN */
1310 {0x0720, 0, 1520}, /* CFG_RGMII0_RXD2_IN */
1311 {0x072C, 28, 1690}, /* CFG_RGMII0_RXD3_IN */
1312 {0x0740, 121, 0}, /* CFG_RGMII0_TXC_OUT */
1313 {0x074C, 60, 0}, /* CFG_RGMII0_TXCTL_OUT */
1314 {0x0758, 153, 0}, /* CFG_RGMII0_TXD0_OUT */
1315 {0x0764, 35, 0}, /* CFG_RGMII0_TXD1_OUT */
1316 {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
1317 {0x077C, 172, 0}, /* CFG_RGMII0_TXD3_OUT */
1318 {0x0A38, 0, 0}, /* CFG_VIN2A_CLK0_IN */
1319 {0x0A44, 2180, 0}, /* CFG_VIN2A_D0_IN */
1320 {0x0A50, 2297, 110}, /* CFG_VIN2A_D10_IN */
1321 {0x0A5C, 1938, 0}, /* CFG_VIN2A_D11_IN */
1322 {0x0A70, 147, 0}, /* CFG_VIN2A_D12_OUT */
1323 {0x0A7C, 110, 0}, /* CFG_VIN2A_D13_OUT */
1324 {0x0A88, 18, 0}, /* CFG_VIN2A_D14_OUT */
1325 {0x0A94, 82, 0}, /* CFG_VIN2A_D15_OUT */
1326 {0x0AA0, 33, 0}, /* CFG_VIN2A_D16_OUT */
1327 {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
1328 {0x0AB0, 417, 0}, /* CFG_VIN2A_D18_IN */
1329 {0x0ABC, 156, 843}, /* CFG_VIN2A_D19_IN */
1330 {0x0AC8, 2326, 309}, /* CFG_VIN2A_D1_IN */
1331 {0x0AD4, 223, 1413}, /* CFG_VIN2A_D20_IN */
1332 {0x0AE0, 169, 1415}, /* CFG_VIN2A_D21_IN */
1333 {0x0AEC, 43, 1150}, /* CFG_VIN2A_D22_IN */
1334 {0x0AF8, 0, 1210}, /* CFG_VIN2A_D23_IN */
1335 {0x0B04, 2057, 0}, /* CFG_VIN2A_D2_IN */
1336 {0x0B10, 2440, 257}, /* CFG_VIN2A_D3_IN */
1337 {0x0B1C, 2142, 0}, /* CFG_VIN2A_D4_IN */
1338 {0x0B28, 2455, 252}, /* CFG_VIN2A_D5_IN */
1339 {0x0B34, 1883, 0}, /* CFG_VIN2A_D6_IN */
1340 {0x0B40, 2229, 0}, /* CFG_VIN2A_D7_IN */
1341 {0x0B4C, 2250, 151}, /* CFG_VIN2A_D8_IN */
1342 {0x0B58, 2279, 27}, /* CFG_VIN2A_D9_IN */
1343 {0x0B7C, 2233, 0}, /* CFG_VIN2A_HSYNC0_IN */
1344 {0x0B88, 1936, 0}, /* CFG_VIN2A_VSYNC0_IN */
1345 {0x0B9C, 1281, 497}, /* CFG_VOUT1_CLK_OUT */
1346 {0x0BA8, 379, 0}, /* CFG_VOUT1_D0_OUT */
1347 {0x0BB4, 441, 0}, /* CFG_VOUT1_D10_OUT */
1348 {0x0BC0, 461, 0}, /* CFG_VOUT1_D11_OUT */
1349 {0x0BCC, 1189, 0}, /* CFG_VOUT1_D12_OUT */
1350 {0x0BD8, 312, 0}, /* CFG_VOUT1_D13_OUT */
1351 {0x0BE4, 298, 0}, /* CFG_VOUT1_D14_OUT */
1352 {0x0BF0, 284, 0}, /* CFG_VOUT1_D15_OUT */
1353 {0x0BFC, 152, 0}, /* CFG_VOUT1_D16_OUT */
1354 {0x0C08, 216, 0}, /* CFG_VOUT1_D17_OUT */
1355 {0x0C14, 408, 0}, /* CFG_VOUT1_D18_OUT */
1356 {0x0C20, 519, 0}, /* CFG_VOUT1_D19_OUT */
1357 {0x0C2C, 475, 0}, /* CFG_VOUT1_D1_OUT */
1358 {0x0C38, 316, 0}, /* CFG_VOUT1_D20_OUT */
1359 {0x0C44, 59, 0}, /* CFG_VOUT1_D21_OUT */
1360 {0x0C50, 221, 0}, /* CFG_VOUT1_D22_OUT */
1361 {0x0C5C, 96, 0}, /* CFG_VOUT1_D23_OUT */
1362 {0x0C68, 264, 0}, /* CFG_VOUT1_D2_OUT */
1363 {0x0C74, 421, 0}, /* CFG_VOUT1_D3_OUT */
1364 {0x0C80, 1257, 0}, /* CFG_VOUT1_D4_OUT */
1365 {0x0C8C, 432, 0}, /* CFG_VOUT1_D5_OUT */
1366 {0x0C98, 436, 0}, /* CFG_VOUT1_D6_OUT */
1367 {0x0CA4, 440, 0}, /* CFG_VOUT1_D7_OUT */
1368 {0x0CB0, 81, 100}, /* CFG_VOUT1_D8_OUT */
1369 {0x0CBC, 471, 0}, /* CFG_VOUT1_D9_OUT */
1370 {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */
1371 {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */
1372 {0x0CEC, 815, 0}, /* CFG_VOUT1_VSYNC_OUT */
1373};
1374#endif
1375
1376
1377#if defined(CONFIG_IODELAY_RECALIBRATION) && \
1378 (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC)) && \
1379 defined(CONFIG_OMAP_HSMMC)
1380
1381static struct pad_conf_entry hsmmc1_default_padconf[] = {
1382 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP) /* mmc1_clk.clk */},
1383 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP) /* mmc1_cmd.cmd */},
1384 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat0.dat0 */},
1385 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat1.dat1 */},
1386 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat2.dat2 */},
1387 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat3.dat3 */},
1388};
1389
1390static struct pad_conf_entry mmc2_pins_default_hs[] = {
1391 {GPMC_A23, (M1 | PIN_INPUT_PULLUP) /* g pmc_a23.mmc2_clk */},
1392 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP) /* gpmc_cs1.mmc2_cmd */},
1393 {GPMC_A24, (M1 | PIN_INPUT_PULLUP) /* gpmc_a24.mmc2_dat0 */},
1394 {GPMC_A25, (M1 | PIN_INPUT_PULLUP) /* gpmc_a25.mmc2_dat1 */},
1395 {GPMC_A26, (M1 | PIN_INPUT_PULLUP) /* gpmc_a26.mmc2_dat2 */},
1396 {GPMC_A27, (M1 | PIN_INPUT_PULLUP) /* gpmc_a27.mmc2_dat3 */},
1397 {GPMC_A19, (M1 | PIN_INPUT_PULLUP) /* gpmc_a19.mmc2_dat4 */},
1398 {GPMC_A20, (M1 | PIN_INPUT_PULLUP) /* gpmc_a20.mmc2_dat5 */},
1399 {GPMC_A21, (M1 | PIN_INPUT_PULLUP) /* gpmc_a21.mmc2_dat6 */},
1400 {GPMC_A22, (M1 | PIN_INPUT_PULLUP) /* gpmc_a22.mmc2_dat7 */},
1401};
1402
1403static struct pad_conf_entry mmc2_pins_ddr_hs200_1_8v[] = {
1404 {GPMC_A23, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a23.mmc2_clk */},
1405 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_cs1.mmc2_cmd */},
1406 {GPMC_A24, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a24.mmc2_dat0 */},
1407 {GPMC_A25, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a25.mmc2_dat1 */},
1408 {GPMC_A26, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a26.mmc2_dat2 */},
1409 {GPMC_A27, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a27.mmc2_dat3 */},
1410 {GPMC_A19, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a19.mmc2_dat4 */},
1411 {GPMC_A20, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a20.mmc2_dat5 */},
1412 {GPMC_A21, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a21.mmc2_dat6 */},
1413 {GPMC_A22, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a22.mmc2_dat7 */},
1414};
1415
1416static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_rev11_conf[] = {
1417 {0x190, 621, 600 /* CFG_GPMC_A19_OEN */},
1418 {0x194, 300, 0 /* CFG_GPMC_A19_OUT */},
1419 {0x1a8, 739, 600 /* CFG_GPMC_A20_OEN */},
1420 {0x1ac, 240, 0 /* CFG_GPMC_A20_OUT */},
1421 {0x1b4, 812, 600 /* CFG_GPMC_A21_OEN */},
1422 {0x1b8, 240, 0 /* CFG_GPMC_A21_OUT */},
1423 {0x1c0, 954, 600 /* CFG_GPMC_A22_OEN */},
1424 {0x1c4, 60, 0 /* CFG_GPMC_A22_OUT */},
1425 {0x1d0, 1340, 420 /* CFG_GPMC_A23_OUT */},
1426 {0x1d8, 935, 600 /* CFG_GPMC_A24_OEN */},
1427 {0x1dc, 0, 0 /* CFG_GPMC_A24_OUT */},
1428 {0x1e4, 525, 600 /* CFG_GPMC_A25_OEN */},
1429 {0x1e8, 120, 0 /* CFG_GPMC_A25_OUT */},
1430 {0x1f0, 767, 600 /* CFG_GPMC_A26_OEN */},
1431 {0x1f4, 225, 0 /* CFG_GPMC_A26_OUT */},
1432 {0x1fc, 565, 600 /* CFG_GPMC_A27_OEN */},
1433 {0x200, 60, 0 /* CFG_GPMC_A27_OUT */},
1434 {0x364, 969, 600 /* CFG_GPMC_CS1_OEN */},
1435 {0x368, 180, 0 /* CFG_GPMC_CS1_OUT */},
1436};
1437
1438static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_rev20_conf[] = {
1439 {0x190, 274, 0 /* CFG_GPMC_A19_OEN */},
1440 {0x194, 162, 0 /* CFG_GPMC_A19_OUT */},
1441 {0x1a8, 401, 0 /* CFG_GPMC_A20_OEN */},
1442 {0x1ac, 73, 0 /* CFG_GPMC_A20_OUT */},
1443 {0x1b4, 465, 0 /* CFG_GPMC_A21_OEN */},
1444 {0x1b8, 115, 0 /* CFG_GPMC_A21_OUT */},
1445 {0x1c0, 633, 0 /* CFG_GPMC_A22_OEN */},
1446 {0x1c4, 47, 0 /* CFG_GPMC_A22_OUT */},
1447 {0x1d0, 935, 280 /* CFG_GPMC_A23_OUT */},
1448 {0x1d8, 621, 0 /* CFG_GPMC_A24_OEN */},
1449 {0x1dc, 0, 0 /* CFG_GPMC_A24_OUT */},
1450 {0x1e4, 183, 0 /* CFG_GPMC_A25_OEN */},
1451 {0x1e8, 0, 0 /* CFG_GPMC_A25_OUT */},
1452 {0x1f0, 467, 0 /* CFG_GPMC_A26_OEN */},
1453 {0x1f4, 0, 0 /* CFG_GPMC_A26_OUT */},
1454 {0x1fc, 262, 0 /* CFG_GPMC_A27_OEN */},
1455 {0x200, 46, 0 /* CFG_GPMC_A27_OUT */},
1456 {0x364, 684, 0 /* CFG_GPMC_CS1_OEN */},
1457 {0x368, 76, 0 /* CFG_GPMC_CS1_OUT */},
1458};
1459
1460static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_rev11_conf[] = {
1461 {0x18c, 0, 0 /* CFG_GPMC_A19_IN */},
1462 {0x1a4, 274, 240 /* CFG_GPMC_A20_IN */},
1463 {0x1b0, 0, 60 /* CFG_GPMC_A21_IN */},
1464 {0x1bc, 0, 60 /* CFG_GPMC_A22_IN */},
1465 {0x1c8, 514, 360 /* CFG_GPMC_A23_IN */},
1466 {0x1d4, 187, 120 /* CFG_GPMC_A24_IN */},
1467 {0x1e0, 0, 0 /* CFG_GPMC_A25_IN */},
1468 {0x1ec, 0, 60 /* CFG_GPMC_A26_IN */},
1469 {0x1f8, 121, 60 /* CFG_GPMC_A27_IN */},
1470 {0x360, 0, 0 /* CFG_GPMC_CS1_IN */},
1471 {0x190, 0, 0 /* CFG_GPMC_A19_OEN */},
1472 {0x194, 174, 0 /* CFG_GPMC_A19_OUT */},
1473 {0x1a8, 0, 0 /* CFG_GPMC_A20_OEN */},
1474 {0x1ac, 168, 0 /* CFG_GPMC_A20_OUT */},
1475 {0x1b4, 0, 0 /* CFG_GPMC_A21_OEN */},
1476 {0x1b8, 136, 0 /* CFG_GPMC_A21_OUT */},
1477 {0x1c0, 0, 0 /* CFG_GPMC_A22_OEN */},
1478 {0x1c4, 0, 0 /* CFG_GPMC_A22_OUT */},
1479 {0x1d0, 879, 0 /* CFG_GPMC_A23_OUT */},
1480 {0x1d8, 0, 0 /* CFG_GPMC_A24_OEN */},
1481 {0x1dc, 0, 0 /* CFG_GPMC_A24_OUT */},
1482 {0x1e4, 0, 0 /* CFG_GPMC_A25_OEN */},
1483 {0x1e8, 34, 0 /* CFG_GPMC_A25_OUT */},
1484 {0x1f0, 0, 0 /* CFG_GPMC_A26_OEN */},
1485 {0x1f4, 120, 0 /* CFG_GPMC_A26_OUT */},
1486 {0x1fc, 0, 0 /* CFG_GPMC_A27_OEN */},
1487 {0x200, 0, 0 /* CFG_GPMC_A27_OUT */},
1488 {0x364, 0, 0 /* CFG_GPMC_CS1_OEN */},
1489 {0x368, 11, 0 /* CFG_GPMC_CS1_OUT */},
1490};
1491
1492static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_rev20_conf[] = {
1493 {0x18c, 270, 0 /* CFG_GPMC_A19_IN */},
1494 {0x1a4, 0, 0 /* CFG_GPMC_A20_IN */},
1495 {0x1b0, 170, 0 /* CFG_GPMC_A21_IN */},
1496 {0x1bc, 758, 0 /* CFG_GPMC_A22_IN */},
1497 {0x1c8, 0, 0 /* CFG_GPMC_A23_IN */},
1498 {0x1d4, 81, 0 /* CFG_GPMC_A24_IN */},
1499 {0x1e0, 286, 0 /* CFG_GPMC_A25_IN */},
1500 {0x1ec, 0, 0 /* CFG_GPMC_A26_IN */},
1501 {0x1f8, 123, 0 /* CFG_GPMC_A27_IN */},
1502 {0x360, 346, 0 /* CFG_GPMC_CS1_IN */},
1503 {0x190, 0, 0 /* CFG_GPMC_A19_OEN */},
1504 {0x194, 55, 0 /* CFG_GPMC_A19_OUT */},
1505 {0x1a8, 0, 0 /* CFG_GPMC_A20_OEN */},
1506 {0x1ac, 422, 0 /* CFG_GPMC_A20_OUT */},
1507 {0x1b4, 642, 0 /* CFG_GPMC_A21_OEN */},
1508 {0x1b8, 0, 0 /* CFG_GPMC_A21_OUT */},
1509 {0x1c0, 0, 0 /* CFG_GPMC_A22_OEN */},
1510 {0x1c4, 128, 0 /* CFG_GPMC_A22_OUT */},
1511 {0x1d0, 0, 0 /* CFG_GPMC_A23_OUT */},
1512 {0x1d8, 0, 0 /* CFG_GPMC_A24_OEN */},
1513 {0x1dc, 395, 0 /* CFG_GPMC_A24_OUT */},
1514 {0x1e4, 0, 0 /* CFG_GPMC_A25_OEN */},
1515 {0x1e8, 0, 0 /* CFG_GPMC_A25_OUT */},
1516 {0x1f0, 623, 0 /* CFG_GPMC_A26_OEN */},
1517 {0x1f4, 0, 0 /* CFG_GPMC_A26_OUT */},
1518 {0x1fc, 54, 0 /* CFG_GPMC_A27_OEN */},
1519 {0x200, 0, 0 /* CFG_GPMC_A27_OUT */},
1520 {0x364, 0, 0 /* CFG_GPMC_CS1_OEN */},
1521 {0x368, 0, 0 /* CFG_GPMC_CS1_OUT */},
1522};
1523
1524static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_dra72_conf[] = {
1525 {0x18c, 0, 0, /* CFG_GPMC_A19_IN */},
1526 {0x1a4, 121, 0, /* CFG_GPMC_A20_IN */},
1527 {0x1b0, 0, 0, /* CFG_GPMC_A21_IN */},
1528 {0x1bc, 20, 0, /* CFG_GPMC_A22_IN */},
1529 {0x1c8, 108, 0, /* CFG_GPMC_A23_IN */},
1530 {0x1d4, 31, 0, /* CFG_GPMC_A24_IN */},
1531 {0x1e0, 0, 0, /* CFG_GPMC_A25_IN */},
1532 {0x1ec, 24, 0, /* CFG_GPMC_A26_IN */},
1533 {0x1f8, 0, 0,