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authorPraneeth Bajjuri2017-08-07 10:28:23 -0500
committerPraneeth Bajjuri2017-08-07 10:28:23 -0500
commit0b457c33bd99c22c0d0f0f0b84e9b6c320e42e68 (patch)
tree0b029cb50b90cc2c9f74cfb8b17d80ec5ac96126
parent368d75e93684af0c36ec538324dfd6f064d1be5a (diff)
parentb1b0b0b49407b073ed0e1865c58a3dfa9dc80452 (diff)
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Merge branch 'ti-u-boot-2016.05' of git://git.ti.com/ti-u-boot/ti-u-boot into p-ti-u-boot-2016.05
* 'ti-u-boot-2016.05' of git://git.ti.com/ti-u-boot/ti-u-boot: ARM: dts: dra76-evm: Add initial support ARM: dts: dra7-evm: sync DT with Linux configs: ti_omap5_common: Select dtb name for dra76 board: ti: dra76-evm: Add support for powering on mmc ldo board: ti: dra76-evm: Add the pinmux data board: ti: dra76-evm: Add DDR data board: ti: dra76-evm: Add the pmic data board: ti: dra76-evm: Add epprom support arm: dra76: Add support for ES1.0 detection configs: dra7xx: Enable LP87565 related configs power: regulator: palmas: Add smps12 dual regulator for tps65917 power: regulator: lp87565: add regulator support power: pmic: lp87565: Add the basic pmic support palmas: Add support for powering different ldos arm: omap5+: Add board specific ldo powering spi: ti_qspi: Fix baudrate divider calculation Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Conflicts: configs/dra7xx_evm_defconfig Change-Id: I05447e3e5dab5bcad0dd0469579d95f293563c97
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c44
-rw-r--r--arch/arm/cpu/armv7/omap5/hwinit.c19
-rw-r--r--arch/arm/cpu/armv7/omap5/sdram.c2
-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/dra7-evm-common.dtsi190
-rw-r--r--arch/arm/dts/dra7-evm.dts473
-rw-r--r--arch/arm/dts/dra76-evm.dts421
-rw-r--r--arch/arm/dts/dra76x.dtsi27
-rw-r--r--arch/arm/include/asm/arch-omap5/clock.h9
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h1
-rw-r--r--arch/arm/include/asm/omap_common.h9
-rw-r--r--arch/arm/include/asm/omap_mmc.h1
-rw-r--r--board/ti/dra7xx/evm.c141
-rw-r--r--board/ti/dra7xx/mux_data.h294
-rw-r--r--configs/dra7xx_evm_defconfig6
-rw-r--r--configs/dra7xx_hs_evm_defconfig4
-rw-r--r--drivers/power/palmas.c6
-rw-r--r--drivers/power/pmic/Kconfig7
-rw-r--r--drivers/power/pmic/Makefile1
-rw-r--r--drivers/power/pmic/lp87565.c89
-rw-r--r--drivers/power/regulator/Kconfig10
-rw-r--r--drivers/power/regulator/Makefile1
-rw-r--r--drivers/power/regulator/lp87565_regulator.c199
-rw-r--r--drivers/power/regulator/palmas_regulator.c6
-rw-r--r--drivers/spi/ti_qspi.c16
-rw-r--r--include/configs/ti_omap5_common.h2
-rw-r--r--include/palmas.h6
-rw-r--r--include/power/lp87565.h12
28 files changed, 1593 insertions, 405 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 2f9f5ad161..ed016cb7de 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -113,6 +113,16 @@ static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
113 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ 113 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
114}; 114};
115 115
116static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = {
117 {32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 12 MHz */
118 {96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 20 MHz */
119 {160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 16.8 MHz */
120 {20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 19.2 MHz */
121 {192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 26 MHz */
122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
123 {10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 38.4 MHz */
124};
125
116static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { 126static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
117 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 127 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
118 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 128 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
@@ -234,6 +244,17 @@ struct dplls omap5_dplls_es2 = {
234 .ddr = NULL 244 .ddr = NULL
235}; 245};
236 246
247struct dplls dra76x_dplls = {
248 .mpu = mpu_dpll_params_1ghz,
249 .core = core_dpll_params_2128mhz_dra7xx,
250 .per = per_dpll_params_768mhz_dra76x,
251 .abe = abe_dpll_params_sysclk2_361267khz,
252 .iva = iva_dpll_params_2330mhz_dra7xx,
253 .usb = usb_dpll_params_1920mhz,
254 .ddr = ddr_dpll_params_2664mhz,
255 .gmac = gmac_dpll_params_2000mhz,
256};
257
237struct dplls dra7xx_dplls = { 258struct dplls dra7xx_dplls = {
238 .mpu = mpu_dpll_params_1ghz, 259 .mpu = mpu_dpll_params_1ghz,
239 .core = core_dpll_params_2128mhz_dra7xx, 260 .core = core_dpll_params_2128mhz_dra7xx,
@@ -285,6 +306,22 @@ struct pmic_data tps659038 = {
285 .gpio_en = 0, 306 .gpio_en = 0,
286}; 307};
287 308
309/* The LP87565*/
310struct pmic_data lp87565 = {
311 .base_offset = LP873X_BUCK_BASE_VOLT_UV,
312 .step = 5000, /* 5 mV represented in uV */
313 /*
314 * Offset codes 0 - 0x13 Invalid.
315 * Offset codes 0x14 0x17 give 10mV steps
316 * Offset codes 0x17 through 0x9D give 5mV steps
317 * So let us start with our operating range from .73V
318 */
319 .start_code = 0x17,
320 .i2c_slave_addr = 0x60,
321 .pmic_bus_init = gpi2c_init,
322 .pmic_write = palmas_i2c_write_u8,
323};
324
288/* The LP8732 and LP8733 are software-compatible, use common struct */ 325/* The LP8732 and LP8733 are software-compatible, use common struct */
289struct pmic_data lp8733 = { 326struct pmic_data lp8733 = {
290 .base_offset = LP873X_BUCK_BASE_VOLT_UV, 327 .base_offset = LP873X_BUCK_BASE_VOLT_UV,
@@ -700,6 +737,12 @@ void __weak hw_data_init(void)
700 *ctrl = &omap5_ctrl; 737 *ctrl = &omap5_ctrl;
701 break; 738 break;
702 739
740 case DRA762_ES1_0:
741 *prcm = &dra7xx_prcm;
742 *dplls_data = &dra76x_dplls;
743 *ctrl = &dra7xx_ctrl;
744 break;
745
703 case DRA752_ES1_0: 746 case DRA752_ES1_0:
704 case DRA752_ES1_1: 747 case DRA752_ES1_1:
705 case DRA752_ES2_0: 748 case DRA752_ES2_0:
@@ -738,6 +781,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
738 case DRA752_ES1_0: 781 case DRA752_ES1_0:
739 case DRA752_ES1_1: 782 case DRA752_ES1_1:
740 case DRA752_ES2_0: 783 case DRA752_ES2_0:
784 case DRA762_ES1_0:
741 *regs = &ioregs_dra7xx_es1; 785 *regs = &ioregs_dra7xx_es1;
742 break; 786 break;
743 case DRA722_ES1_0: 787 case DRA722_ES1_0:
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 839d79d102..434d304686 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -362,6 +362,9 @@ void init_omap_revision(void)
362 case OMAP5432_CONTROL_ID_CODE_ES2_0: 362 case OMAP5432_CONTROL_ID_CODE_ES2_0:
363 *omap_si_rev = OMAP5432_ES2_0; 363 *omap_si_rev = OMAP5432_ES2_0;
364 break; 364 break;
365 case DRA762_CONTROL_ID_CODE_ES1_0:
366 *omap_si_rev = DRA762_ES1_0;
367 break;
365 case DRA752_CONTROL_ID_CODE_ES1_0: 368 case DRA752_CONTROL_ID_CODE_ES1_0:
366 *omap_si_rev = DRA752_ES1_0; 369 *omap_si_rev = DRA752_ES1_0;
367 break; 370 break;
@@ -454,10 +457,14 @@ void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
454} 457}
455 458
456#if defined(CONFIG_PALMAS_POWER) 459#if defined(CONFIG_PALMAS_POWER)
460__weak void board_mmc_poweron_ldo(uint voltage)
461{
462 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
463}
464
457void vmmc_pbias_config(uint voltage) 465void vmmc_pbias_config(uint voltage)
458{ 466{
459 u32 value = 0; 467 u32 value = 0;
460 struct vcores_data const *vcores = *omap_vcores;
461 468
462 value = readl((*ctrl)->control_pbias); 469 value = readl((*ctrl)->control_pbias);
463 value &= ~SDCARD_PWRDNZ; 470 value &= ~SDCARD_PWRDNZ;
@@ -466,15 +473,7 @@ void vmmc_pbias_config(uint voltage)
466 value &= ~SDCARD_BIAS_PWRDNZ; 473 value &= ~SDCARD_BIAS_PWRDNZ;
467 writel(value, (*ctrl)->control_pbias); 474 writel(value, (*ctrl)->control_pbias);
468 475
469 if (vcores->core.pmic->i2c_slave_addr == 0x60) { 476 board_mmc_poweron_ldo(voltage);
470 if (voltage == LDO_VOLT_3V0)
471 voltage = 0x19;
472 else if (voltage == LDO_VOLT_1V8)
473 voltage = 0xa;
474 lp873x_mmc1_poweron_ldo(voltage);
475 } else {
476 palmas_mmc1_poweron_ldo(voltage);
477 }
478 477
479 value = readl((*ctrl)->control_pbias); 478 value = readl((*ctrl)->control_pbias);
480 value |= SDCARD_BIAS_PWRDNZ; 479 value |= SDCARD_BIAS_PWRDNZ;
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 7712923d85..67ff63b9f6 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -480,6 +480,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
480 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz; 480 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
481 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz); 481 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
482 break; 482 break;
483 case DRA762_ES1_0:
483 case DRA722_ES2_0: 484 case DRA722_ES2_0:
484 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; 485 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
485 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); 486 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
@@ -709,6 +710,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
709 *iterations = sizeof(omap5_bug_00339_regs)/ 710 *iterations = sizeof(omap5_bug_00339_regs)/
710 sizeof(omap5_bug_00339_regs[0]); 711 sizeof(omap5_bug_00339_regs[0]);
711 break; 712 break;
713 case DRA762_ES1_0:
712 case DRA752_ES1_0: 714 case DRA752_ES1_0:
713 case DRA752_ES1_1: 715 case DRA752_ES1_1:
714 case DRA752_ES2_0: 716 case DRA752_ES2_0:
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0c87fa4492..fa81de1152 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -108,7 +108,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
108 socfpga_cyclone5_sr1500.dtb 108 socfpga_cyclone5_sr1500.dtb
109 109
110dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ 110dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
111 dra72-evm-revc.dtb dra71-evm.dtb 111 dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
112dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ 112dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
113 am572x-idk.dtb \ 113 am572x-idk.dtb \
114 am571x-idk.dtb 114 am571x-idk.dtb
diff --git a/arch/arm/dts/dra7-evm-common.dtsi b/arch/arm/dts/dra7-evm-common.dtsi
new file mode 100644
index 0000000000..78ffafd143
--- /dev/null
+++ b/arch/arm/dts/dra7-evm-common.dtsi
@@ -0,0 +1,190 @@
1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11
12/ {
13 chosen {
14 stdout-path = &uart1;
15 tick-timer = &timer2;
16 };
17
18 extcon_usb1: extcon_usb1 {
19 compatible = "linux,extcon-usb-gpio";
20 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
21 };
22
23 extcon_usb2: extcon_usb2 {
24 compatible = "linux,extcon-usb-gpio";
25 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
26 };
27
28 leds {
29 compatible = "gpio-leds";
30 led@0 {
31 label = "dra7:usr1";
32 gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
33 default-state = "off";
34 };
35
36 led@1 {
37 label = "dra7:usr2";
38 gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
39 default-state = "off";
40 };
41
42 led@2 {
43 label = "dra7:usr3";
44 gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
45 default-state = "off";
46 };
47
48 led@3 {
49 label = "dra7:usr4";
50 gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
51 default-state = "off";
52 };
53 };
54
55 gpio_keys {
56 compatible = "gpio-keys";
57 #address-cells = <1>;
58 #size-cells = <0>;
59 autorepeat;
60
61 USER1 {
62 label = "btnUser1";
63 linux,code = <BTN_0>;
64 gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
65 };
66
67 USER2 {
68 label = "btnUser2";
69 linux,code = <BTN_1>;
70 gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
71 };
72 };
73};
74
75&dra7_pmx_core {
76 dcan1_pins_default: dcan1_pins_default {
77 pinctrl-single,pins = <
78 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
79 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
80 >;
81 };
82
83 dcan1_pins_sleep: dcan1_pins_sleep {
84 pinctrl-single,pins = <
85 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
86 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
87 >;
88 };
89};
90
91&i2c3 {
92 status = "okay";
93 clock-frequency = <400000>;
94};
95
96&mcspi1 {
97 status = "okay";
98};
99
100&mcspi2 {
101 status = "okay";
102};
103
104&uart1 {
105 status = "okay";
106 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
107 <&dra7_pmx_core 0x3e0>;
108};
109
110&uart2 {
111 status = "okay";
112};
113
114&uart3 {
115 status = "okay";
116};
117
118
119&qspi {
120 status = "okay";
121
122 spi-max-frequency = <76800000>;
123 m25p80@0 {
124 compatible = "s25fl256s1";
125 spi-max-frequency = <76800000>;
126 reg = <0>;
127 spi-tx-bus-width = <1>;
128 spi-rx-bus-width = <4>;
129 #address-cells = <1>;
130 #size-cells = <1>;
131
132 /* MTD partition table.
133 * The ROM checks the first four physical blocks
134 * for a valid file to boot and the flash here is
135 * 64KiB block size.
136 */
137 partition@0 {
138 label = "QSPI.SPL";
139 reg = <0x00000000 0x000040000>;
140 };
141 partition@1 {
142 label = "QSPI.u-boot";
143 reg = <0x00040000 0x00100000>;
144 };
145 partition@2 {
146 label = "QSPI.u-boot-spl-os";
147 reg = <0x00140000 0x00080000>;
148 };
149 partition@3 {
150 label = "QSPI.u-boot-env";
151 reg = <0x001c0000 0x00010000>;
152 };
153 partition@4 {
154 label = "QSPI.u-boot-env.backup1";
155 reg = <0x001d0000 0x0010000>;
156 };
157 partition@5 {
158 label = "QSPI.kernel";
159 reg = <0x001e0000 0x0800000>;
160 };
161 partition@6 {
162 label = "QSPI.file-system";
163 reg = <0x009e0000 0x01620000>;
164 };
165 };
166};
167
168&omap_dwc3_1 {
169 extcon = <&extcon_usb1>;
170};
171
172&omap_dwc3_2 {
173 extcon = <&extcon_usb2>;
174};
175
176&usb1 {
177 dr_mode = "peripheral";
178};
179
180&usb2 {
181 dr_mode = "host";
182};
183
184&dcan1 {
185 status = "ok";
186 pinctrl-names = "default", "sleep", "active";
187 pinctrl-0 = <&dcan1_pins_sleep>;
188 pinctrl-1 = <&dcan1_pins_sleep>;
189 pinctrl-2 = <&dcan1_pins_default>;
190};
diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index ecfaf6052d..ceee1a76b5 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -8,17 +8,14 @@
8/dts-v1/; 8/dts-v1/;
9 9
10#include "dra74x.dtsi" 10#include "dra74x.dtsi"
11#include "dra7-evm-common.dtsi"
11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
12 14
13/ { 15/ {
14 model = "TI DRA742"; 16 model = "TI DRA742";
15 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; 17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
16 18
17 chosen {
18 stdout-path = &uart1;
19 tick-timer = &timer2;
20 };
21
22 memory { 19 memory {
23 device_type = "memory"; 20 device_type = "memory";
24 reg = <0x80000000 0x60000000>; /* 1536 MB */ 21 reg = <0x80000000 0x60000000>; /* 1536 MB */
@@ -33,23 +30,34 @@
33 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; 30 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
34 }; 31 };
35 32
36 mmc2_3v3: fixedregulator-mmc2 { 33 evm_3v3_sw: fixedregulator-evm_3v3_sw {
37 compatible = "regulator-fixed"; 34 compatible = "regulator-fixed";
38 regulator-name = "mmc2_3v3"; 35 regulator-name = "evm_3v3_sw";
36 vin-supply = <&sysen1>;
39 regulator-min-microvolt = <3300000>; 37 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>; 38 regulator-max-microvolt = <3300000>;
41 }; 39 };
42 40
43 extcon_usb1: extcon_usb1 { 41 aic_dvdd: fixedregulator-aic_dvdd {
44 compatible = "linux,extcon-usb-gpio"; 42 /* TPS77018DBVT */
45 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; 43 compatible = "regulator-fixed";
44 regulator-name = "aic_dvdd";
45 vin-supply = <&evm_3v3_sw>;
46 regulator-min-microvolt = <1800000>;
47 regulator-max-microvolt = <1800000>;
46 }; 48 };
47 49
48 extcon_usb2: extcon_usb2 { 50 vmmcwl_fixed: fixedregulator-mmcwl {
49 compatible = "linux,extcon-usb-gpio"; 51 compatible = "regulator-fixed";
50 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; 52 regulator-name = "vmmcwl_fixed";
53 regulator-min-microvolt = <1800000>;
54 regulator-max-microvolt = <1800000>;
55 gpio = <&gpio5 8 0>; /* gpio5_8 */
56 startup-delay-us = <70000>;
57 enable-active-high;
51 }; 58 };
52 59
60
53 vtt_fixed: fixedregulator-vtt { 61 vtt_fixed: fixedregulator-vtt {
54 compatible = "regulator-fixed"; 62 compatible = "regulator-fixed";
55 regulator-name = "vtt_fixed"; 63 regulator-name = "vtt_fixed";
@@ -58,234 +66,30 @@
58 regulator-always-on; 66 regulator-always-on;
59 regulator-boot-on; 67 regulator-boot-on;
60 enable-active-high; 68 enable-active-high;
69 vin-supply = <&sysen2>;
61 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; 70 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
62 }; 71 };
63}; 72};
64 73
65&dra7_pmx_core { 74&dra7_pmx_core {
66 pinctrl-names = "default"; 75 hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
67 pinctrl-0 = <&vtt_pin>;
68
69 vtt_pin: pinmux_vtt_pin {
70 pinctrl-single,pins = <
71 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
72 >;
73 };
74
75 i2c1_pins: pinmux_i2c1_pins {
76 pinctrl-single,pins = <
77 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
78 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
79 >;
80 };
81
82 i2c2_pins: pinmux_i2c2_pins {
83 pinctrl-single,pins = <
84 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
85 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
86 >;
87 };
88
89 i2c3_pins: pinmux_i2c3_pins {
90 pinctrl-single,pins = <
91 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
92 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
93 >;
94 };
95
96 mcspi1_pins: pinmux_mcspi1_pins {
97 pinctrl-single,pins = <
98 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
99 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
100 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
101 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
102 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
103 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
104 >;
105 };
106
107 mcspi2_pins: pinmux_mcspi2_pins {
108 pinctrl-single,pins = <
109 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
110 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
111 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
112 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
113 >;
114 };
115
116 uart1_pins: pinmux_uart1_pins {
117 pinctrl-single,pins = <
118 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
119 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
120 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
121 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
122 >;
123 };
124
125 uart2_pins: pinmux_uart2_pins {
126 pinctrl-single,pins = <
127 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
128 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
129 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
130 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
131 >;
132 };
133
134 uart3_pins: pinmux_uart3_pins {
135 pinctrl-single,pins = < 76 pinctrl-single,pins = <
136 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ 77 /* this pin is used as a GPIO via mcasp */
137 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ 78 0x2fc (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
138 >; 79 >;
139 }; 80 };
140 81
141 qspi1_pins: pinmux_qspi1_pins { 82 hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
142 pinctrl-single,pins = < 83 pinctrl-single,pins = <
143 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */ 84 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
144 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */ 85 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
145 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
146 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
147 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
148 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
149 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
150 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
151 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
152 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
153 >; 86 >;
154 }; 87 };
155 88
156 usb1_pins: pinmux_usb1_pins { 89 hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
157 pinctrl-single,pins = <
158 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
159 >;
160 };
161
162 usb2_pins: pinmux_usb2_pins {
163 pinctrl-single,pins = <
164 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
165 >;
166 };
167
168 nand_flash_x16: nand_flash_x16 {
169 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
170 * So NAND flash requires following switch settings:
171 * SW5.9 (GPMC_WPN) = LOW
172 * SW5.1 (NAND_BOOTn) = HIGH */
173 pinctrl-single,pins = < 90 pinctrl-single,pins = <
174 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ 91 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
175 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ 92 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
176 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
177 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
178 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
179 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
180 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
181 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
182 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
183 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
184 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
185 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
186 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
187 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
188 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
189 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
190 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
191 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
192 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
193 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
194 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
195 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
196 >;
197 };
198
199 cpsw_default: cpsw_default {
200 pinctrl-single,pins = <
201 /* Slave 1 */
202 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
203 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
204 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
205 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
206 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
207 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
208 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
209 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
210 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
211 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
212 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
213 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
214
215 /* Slave 2 */
216 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
217 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
218 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
219 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
220 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
221 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
222 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
223 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
224 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
225 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
226 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
227 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
228 >;
229
230 };
231
232 cpsw_sleep: cpsw_sleep {
233 pinctrl-single,pins = <
234 /* Slave 1 */
235 0x250 (MUX_MODE15)
236 0x254 (MUX_MODE15)
237 0x258 (MUX_MODE15)
238 0x25c (MUX_MODE15)
239 0x260 (MUX_MODE15)
240 0x264 (MUX_MODE15)
241 0x268 (MUX_MODE15)
242 0x26c (MUX_MODE15)
243 0x270 (MUX_MODE15)
244 0x274 (MUX_MODE15)
245 0x278 (MUX_MODE15)
246 0x27c (MUX_MODE15)
247
248 /* Slave 2 */
249 0x198 (MUX_MODE15)
250 0x19c (MUX_MODE15)
251 0x1a0 (MUX_MODE15)
252 0x1a4 (MUX_MODE15)
253 0x1a8 (MUX_MODE15)
254 0x1ac (MUX_MODE15)
255 0x1b0 (MUX_MODE15)
256 0x1b4 (MUX_MODE15)
257 0x1b8 (MUX_MODE15)
258 0x1bc (MUX_MODE15)
259 0x1c0 (MUX_MODE15)
260 0x1c4 (MUX_MODE15)
261 >;
262 };
263
264 davinci_mdio_default: davinci_mdio_default {
265 pinctrl-single,pins = <
266 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
267 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
268 >;
269 };
270
271 davinci_mdio_sleep: davinci_mdio_sleep {
272 pinctrl-single,pins = <
273 0x23c (MUX_MODE15)
274 0x240 (MUX_MODE15)
275 >;
276 };
277
278 dcan1_pins_default: dcan1_pins_default {
279 pinctrl-single,pins = <
280 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
281 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
282 >;
283 };
284
285 dcan1_pins_sleep: dcan1_pins_sleep {
286 pinctrl-single,pins = <
287 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
288 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
289 >; 93 >;
290 }; 94 };
291 95
@@ -623,8 +427,6 @@
623 427
624&i2c1 { 428&i2c1 {
625 status = "okay"; 429 status = "okay";
626 pinctrl-names = "default";
627 pinctrl-0 = <&i2c1_pins>;
628 clock-frequency = <400000>; 430 clock-frequency = <400000>;
629 431
630 tps659038: tps659038@58 { 432 tps659038: tps659038@58 {
@@ -648,7 +450,7 @@
648 /* VDD_DSPEVE */ 450 /* VDD_DSPEVE */
649 regulator-name = "smps45"; 451 regulator-name = "smps45";
650 regulator-min-microvolt = < 850000>; 452 regulator-min-microvolt = < 850000>;
651 regulator-max-microvolt = <1150000>; 453 regulator-max-microvolt = <1250000>;
652 regulator-always-on; 454 regulator-always-on;
653 regulator-boot-on; 455 regulator-boot-on;
654 }; 456 };
@@ -666,7 +468,7 @@
666 /* CORE_VDD */ 468 /* CORE_VDD */
667 regulator-name = "smps7"; 469 regulator-name = "smps7";
668 regulator-min-microvolt = <850000>; 470 regulator-min-microvolt = <850000>;
669 regulator-max-microvolt = <1060000>; 471 regulator-max-microvolt = <1150000>;
670 regulator-always-on; 472 regulator-always-on;
671 regulator-boot-on; 473 regulator-boot-on;
672 }; 474 };
@@ -694,6 +496,7 @@
694 regulator-name = "ldo1"; 496 regulator-name = "ldo1";
695 regulator-min-microvolt = <1800000>; 497 regulator-min-microvolt = <1800000>;
696 regulator-max-microvolt = <3300000>; 498 regulator-max-microvolt = <3300000>;
499 regulator-always-on;
697 regulator-boot-on; 500 regulator-boot-on;
698 }; 501 };
699 502
@@ -723,6 +526,7 @@
723 regulator-max-microvolt = <1050000>; 526 regulator-max-microvolt = <1050000>;
724 regulator-always-on; 527 regulator-always-on;
725 regulator-boot-on; 528 regulator-boot-on;
529 regulator-allow-bypass;
726 }; 530 };
727 531
728 ldoln_reg: ldoln { 532 ldoln_reg: ldoln {
@@ -741,10 +545,46 @@
741 regulator-max-microvolt = <3300000>; 545 regulator-max-microvolt = <3300000>;
742 regulator-boot-on; 546 regulator-boot-on;
743 }; 547 };
548
549 /* REGEN1 is unused */
550
551 regen2: regen2 {
552 /* Needed for PMIC internal resources */
553 regulator-name = "regen2";
554 regulator-boot-on;
555 regulator-always-on;
556 };
557
558 /* REGEN3 is unused */
559
560 sysen1: sysen1 {
561 /* PMIC_REGEN_3V3 */
562 regulator-name = "sysen1";
563 regulator-boot-on;
564 regulator-always-on;
565 };
566
567 sysen2: sysen2 {
568 /* PMIC_REGEN_DDR */
569 regulator-name = "sysen2";
570 regulator-boot-on;
571 regulator-always-on;
572 };
744 }; 573 };
745 }; 574 };
746 }; 575 };
747 576
577 pcf_lcd: gpio@20 {
578 compatible = "nxp,pcf8575";
579 reg = <0x20>;
580 gpio-controller;
581 #gpio-cells = <2>;
582 interrupt-parent = <&gpio6>;
583 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
586 };
587
748 pcf_gpio_21: gpio@21 { 588 pcf_gpio_21: gpio@21 {
749 compatible = "ti,pcf8575"; 589 compatible = "ti,pcf8575";
750 reg = <0x21>; 590 reg = <0x21>;
@@ -757,52 +597,39 @@
757 #interrupt-cells = <2>; 597 #interrupt-cells = <2>;
758 }; 598 };
759 599
760}; 600 tlv320aic3106: tlv320aic3106@19 {
601 #sound-dai-cells = <0>;
602 compatible = "ti,tlv320aic3106";
603 reg = <0x19>;
604 adc-settle-ms = <40>;
605 ai3x-micbias-vg = <1>; /* 2.0V */
606 status = "okay";
761 607
762&i2c2 { 608 /* Regulators */
763 status = "okay"; 609 AVDD-supply = <&evm_3v3_sw>;
764 pinctrl-names = "default"; 610 IOVDD-supply = <&evm_3v3_sw>;
765 pinctrl-0 = <&i2c2_pins>; 611 DRVDD-supply = <&evm_3v3_sw>;
766 clock-frequency = <400000>; 612 DVDD-supply = <&aic_dvdd>;
613 };
767}; 614};
768 615
769&i2c3 { 616&i2c2 {
770 status = "okay"; 617 status = "okay";
771 pinctrl-names = "default";
772 pinctrl-0 = <&i2c3_pins>;
773 clock-frequency = <400000>; 618 clock-frequency = <400000>;
774};
775
776&mcspi1 {
777 status = "okay";
778 pinctrl-names = "default";
779 pinctrl-0 = <&mcspi1_pins>;
780};
781
782&mcspi2 {
783 status = "okay";
784 pinctrl-names = "default";
785 pinctrl-0 = <&mcspi2_pins>;
786};
787
788&uart1 {
789 status = "okay";
790 pinctrl-names = "default";
791 pinctrl-0 = <&uart1_pins>;
792 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
793 <&dra7_pmx_core 0x3e0>;
794};
795 619
796&uart2 { 620 pcf_hdmi: gpio@26 {
797 status = "okay"; 621 compatible = "nxp,pcf8575";
798 pinctrl-names = "default"; 622 reg = <0x26>;
799 pinctrl-0 = <&uart2_pins>; 623 gpio-controller;
800}; 624 #gpio-cells = <2>;
801 625 p1 {
802&uart3 { 626 /* vin6_sel_s0: high: VIN6, low: audio */
803 status = "okay"; 627 gpio-hog;
804 pinctrl-names = "default"; 628 gpios = <1 GPIO_ACTIVE_HIGH>;
805 pinctrl-0 = <&uart3_pins>; 629 output-low;
630 line-name = "vin6_sel_s0";
631 };
632 };
806}; 633};
807 634
808&mmc1 { 635&mmc1 {
@@ -830,7 +657,7 @@
830 657
831&mmc2 { 658&mmc2 {
832 status = "okay"; 659 status = "okay";
833 vmmc-supply = <&mmc2_3v3>; 660 vmmc-supply = <&evm_3v3_sw>;
834 bus-width = <8>; 661 bus-width = <8>;
835 max-frequency = <192000000>; 662 max-frequency = <192000000>;
836 pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; 663 pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
@@ -846,97 +673,12 @@
846 cpu0-supply = <&smps123_reg>; 673 cpu0-supply = <&smps123_reg>;
847}; 674};
848 675
849&qspi {
850 status = "okay";
851 pinctrl-names = "default";
852 pinctrl-0 = <&qspi1_pins>;
853
854 spi-max-frequency = <64000000>;
855 m25p80@0 {
856 compatible = "s25fl256s1","spi-flash";
857 spi-max-frequency = <76800000>;
858 reg = <0>;
859 spi-tx-bus-width = <1>;
860 spi-rx-bus-width = <4>;
861 #address-cells = <1>;
862 #size-cells = <1>;
863
864 /* MTD partition table.
865 * The ROM checks the first four physical blocks
866 * for a valid file to boot and the flash here is
867 * 64KiB block size.
868 */
869 partition@0 {
870 label = "QSPI.SPL";
871 reg = <0x00000000 0x000010000>;
872 };
873 partition@1 {
874 label = "QSPI.SPL.backup1";
875 reg = <0x00010000 0x00010000>;
876 };
877 partition@2 {
878 label = "QSPI.SPL.backup2";
879 reg = <0x00020000 0x00010000>;
880 };
881 partition@3 {
882 label = "QSPI.SPL.backup3";
883 reg = <0x00030000 0x00010000>;
884 };
885 partition@4 {
886 label = "QSPI.u-boot";
887 reg = <0x00040000 0x00100000>;
888 };
889 partition@5 {
890 label = "QSPI.u-boot-spl-os";
891 reg = <0x00140000 0x00080000>;
892 };
893 partition@6 {
894 label = "QSPI.u-boot-env";
895 reg = <0x001c0000 0x00010000>;
896 };
897 partition@7 {
898 label = "QSPI.u-boot-env.backup1";
899 reg = <0x001d0000 0x0010000>;
900 };
901 partition@8 {
902 label = "QSPI.kernel";
903 reg = <0x001e0000 0x0800000>;
904 };
905 partition@9 {
906 label = "QSPI.file-system";
907 reg = <0x009e0000 0x01620000>;
908 };
909 };
910};
911
912&omap_dwc3_1 {
913 extcon = <&extcon_usb1>;
914};
915
916&omap_dwc3_2 {
917 extcon = <&extcon_usb2>;
918};
919
920&usb1 {
921 dr_mode = "peripheral";
922 pinctrl-names = "default";
923 pinctrl-0 = <&usb1_pins>;
924};
925
926&usb2 {
927 dr_mode = "host";
928 pinctrl-names = "default";
929 pinctrl-0 = <&usb2_pins>;
930};
931
932&elm { 676&elm {
933 status = "okay"; 677 status = "okay";
934}; 678};
935 679
936&gpmc { 680&gpmc {
937 status = "okay"; 681 status = "okay";
938 pinctrl-names = "default";
939 pinctrl-0 = <&nand_flash_x16>;
940 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ 682 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
941 nand@0,0 { 683 nand@0,0 {
942 reg = <0 0 4>; /* device IO registers */ 684 reg = <0 0 4>; /* device IO registers */
@@ -1028,9 +770,6 @@
1028 770
1029&mac { 771&mac {
1030 status = "okay"; 772 status = "okay";
1031 pinctrl-names = "default", "sleep";
1032 pinctrl-0 = <&cpsw_default>;
1033 pinctrl-1 = <&cpsw_sleep>;
1034 dual_emac; 773 dual_emac;
1035}; 774};
1036 775
@@ -1045,17 +784,3 @@
1045 phy-mode = "rgmii"; 784 phy-mode = "rgmii";
1046 dual_emac_res_vlan = <2>; 785 dual_emac_res_vlan = <2>;
1047}; 786};
1048
1049&davinci_mdio {
1050 pinctrl-names = "default", "sleep";
1051 pinctrl-0 = <&davinci_mdio_default>;
1052 pinctrl-1 = <&davinci_mdio_sleep>;
1053};
1054
1055&dcan1 {
1056 status = "ok";
1057 pinctrl-names = "default", "sleep", "active";
1058 pinctrl-0 = <&dcan1_pins_sleep>;
1059 pinctrl-1 = <&dcan1_pins_sleep>;
1060 pinctrl-2 = <&dcan1_pins_default>;
1061};
diff --git a/arch/arm/dts/dra76-evm.dts b/arch/arm/dts/dra76-evm.dts
new file mode 100644
index 0000000000..5b14dbf72a
--- /dev/null
+++ b/arch/arm/dts/dra76-evm.dts
@@ -0,0 +1,421 @@
1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra76x.dtsi"
11#include "dra7-evm-common.dtsi"
12#include <dt-bindings/net/ti-dp83867.h>
13
14/ {
15 model = "TI DRA762 EVM";
16 compatible = "ti,dra76-evm", "ti,dra76", "ti,dra7";
17
18 memory@0 {
19 device_type = "memory";
20 reg = <0x0 0x80000000 0x0 0x80000000>;
21 };
22
23 vsys_12v0: fixedregulator-vsys12v0 {
24 /* main supply */
25 compatible = "regulator-fixed";
26 regulator-name = "vsys_12v0";
27 regulator-min-microvolt = <12000000>;
28 regulator-max-microvolt = <12000000>;
29 regulator-always-on;
30 regulator-boot-on;
31 };
32
33 vsys_5v0: fixedregulator-vsys5v0 {
34 /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */
35 compatible = "regulator-fixed";
36 regulator-name = "vsys_5v0";
37 regulator-min-microvolt = <5000000>;
38 regulator-max-microvolt = <5000000>;
39 vin-supply = <&vsys_12v0>;
40 regulator-always-on;
41 regulator-boot-on;
42 };
43
44 vsys_3v3: fixedregulator-vsys3v3 {
45 /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */
46 compatible = "regulator-fixed";
47 regulator-name = "vsys_3v3";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50 vin-supply = <&vsys_12v0>;
51 regulator-always-on;
52 regulator-boot-on;
53 };
54
55 vio_3v3: fixedregulator-vio_3v3 {
56 compatible = "regulator-fixed";
57 regulator-name = "vio_3v3";
58 regulator-min-microvolt = <3300000>;
59 regulator-max-microvolt = <3300000>;
60 vin-supply = <&vsys_3v3>;
61 regulator-always-on;
62 regulator-boot-on;
63 };
64
65 vio_3v3_sd: fixedregulator-sd {
66 compatible = "regulator-fixed";
67 regulator-name = "vio_3v3_sd";
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
70 vin-supply = <&vio_3v3>;
71 enable-active-high;
72 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
73 };
74
75 vio_1v8: fixedregulator-vio_1v8 {
76 compatible = "regulator-fixed";
77 regulator-name = "vio_1v8";
78 regulator-min-microvolt = <1800000>;
79 regulator-max-microvolt = <1800000>;
80 vin-supply = <&smps5_reg>;
81 };
82
83 vtt_fixed: fixedregulator-vtt {
84 compatible = "regulator-fixed";
85 regulator-name = "vtt_fixed";
86 regulator-min-microvolt = <1350000>;
87 regulator-max-microvolt = <1350000>;
88 vin-supply = <&vsys_3v3>;
89 regulator-always-on;
90 regulator-boot-on;
91 };
92
93 aic_dvdd: fixedregulator-aic_dvdd {
94 /* TPS77018DBVT */
95 compatible = "regulator-fixed";
96 regulator-name = "aic_dvdd";
97 vin-supply = <&vio_3v3>;
98 regulator-min-microvolt = <1800000>;
99 regulator-max-microvolt = <1800000>;
100 };
101};
102
103&dra7_pmx_core {
104 mmc1_pins_default: mmc1_pins_default {
105 pinctrl-single,pins = <
106 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
107 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
108 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
109 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
110 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
111 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
112 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
113 >;
114 };
115
116 mmc2_pins_default: mmc2_pins_default {
117 pinctrl-single,pins = <
118 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
119 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
120 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
121 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
122 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
123 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
124 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
125 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
126 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
127 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
128 >;
129 };
130
131 mmc4_pins_default: mmc4_pins_default {
132 pinctrl-single,pins = <
133 0x3e (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
134 0x3e (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
135 0x3f (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
136 0x3f (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
137 0x3f (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
138 0x3f (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
139 >;
140 };
141};
142
143&i2c1 {
144 status = "okay";
145 clock-frequency = <400000>;
146
147 tps65917: tps65917@58 {
148 compatible = "ti,tps65917";
149 reg = <0x58>;
150 ti,system-power-controller;
151 interrupt-controller;
152 #interrupt-cells = <2>;
153
154 tps65917_pmic {
155 compatible = "ti,tps65917-pmic";
156
157 smps12-in-supply = <&vsys_3v3>;
158 smps3-in-supply = <&vsys_3v3>;
159 smps4-in-supply = <&vsys_3v3>;
160 smps5-in-supply = <&vsys_3v3>;
161 ldo1-in-supply = <&vsys_3v3>;
162 ldo2-in-supply = <&vsys_3v3>;
163 ldo3-in-supply = <&vsys_5v0>;
164 ldo4-in-supply = <&vsys_5v0>;
165 ldo5-in-supply = <&vsys_3v3>;
166
167 tps65917_regulators: regulators {
168 smps12_reg: smps12 {
169 /* VDD_DSPEVE */
170 regulator-name = "smps12";
171 regulator-min-microvolt = <850000>;
172 regulator-max-microvolt = <1250000>;
173 regulator-always-on;
174 regulator-boot-on;
175 };
176
177 smps3_reg: smps3 {
178 /* VDD_CORE */
179 regulator-name = "smps3";
180 regulator-min-microvolt = <850000>;
181 regulator-max-microvolt = <1250000>;
182 regulator-boot-on;
183 regulator-always-on;
184 };
185
186 smps4_reg: smps4 {
187 /* VDD_IVA */
188 regulator-name = "smps4";
189 regulator-min-microvolt = <850000>;
190 regulator-max-microvolt = <1250000>;
191 regulator-always-on;
192 regulator-boot-on;
193 };
194
195 smps5_reg: smps5 {
196 /* VDDS1V8 */
197 regulator-name = "smps5";
198 regulator-min-microvolt = <1800000>;
199 regulator-max-microvolt = <1800000>;
200 regulator-boot-on;
201 regulator-always-on;
202 };
203
204 ldo1_reg: ldo1 {
205 /* LDO1_OUT --> VDA_PHY1_1V8 */
206 regulator-name = "ldo1";
207 regulator-min-microvolt = <1800000>;
208 regulator-max-microvolt = <1800000>;
209 regulator-always-on;
210 regulator-boot-on;
211 regulator-allow-bypass;
212 };
213
214 ldo2_reg: ldo2 {
215 /* LDO2_OUT --> VDA_PHY2_1V8 */
216 regulator-name = "ldo2";
217 regulator-min-microvolt = <1800000>;
218 regulator-max-microvolt = <1800000>;
219 regulator-allow-bypass;
220 regulator-always-on;
221 };
222
223 ldo3_reg: ldo3 {
224 /* VDA_USB_3V3 */
225 regulator-name = "ldo3";
226 regulator-min-microvolt = <3300000>;
227 regulator-max-microvolt = <3300000>;
228 regulator-boot-on;
229 regulator-always-on;
230 };
231
232 ldo5_reg: ldo5 {
233 /* VDDA_1V8_PLL */
234 regulator-name = "ldo5";
235 regulator-min-microvolt = <1800000>;
236 regulator-max-microvolt = <1800000>;
237 regulator-always-on;
238 regulator-boot-on;
239 };
240
241 ldo4_reg: ldo4 {
242 /* VDD_SDIO_DV */
243 regulator-name = "ldo4";
244 regulator-min-microvolt = <1800000>;
245 regulator-max-microvolt = <3300000>;
246 regulator-boot-on;
247 regulator-always-on;
248 };
249 };
250 };
251
252 tps65917_power_button {
253 compatible = "ti,palmas-pwrbutton";
254 interrupt-parent = <&tps65917>;
255 interrupts = <1 IRQ_TYPE_NONE>;
256 wakeup-source;
257 ti,palmas-long-press-seconds = <6>;
258 };
259 };
260
261 lp87565: lp87565@60 {
262 compatible = "ti,lp87565-q1";
263 reg = <0x60>;
264
265 buck10-in-supply =<&vsys_3v3>;
266 buck23-in-supply =<&vsys_3v3>;
267
268 regulators: regulators {
269 buck10_reg: buck10 {
270 /*VDD_MPU*/
271 regulator-name = "buck10";
272 regulator-min-microvolt = <850000>;
273 regulator-max-microvolt = <1250000>;
274 regulator-always-on;
275 regulator-boot-on;
276 };
277
278 buck23_reg: buck23 {
279 /* VDD_GPU*/
280 regulator-name = "buck23";
281 regulator-min-microvolt = <850000>;
282 regulator-max-microvolt = <1250000>;
283 regulator-boot-on;
284 regulator-always-on;
285 };
286 };
287 };
288
289 pcf_lcd: pcf8757@20 {
290 compatible = "ti,pcf8575", "nxp,pcf8575";
291 reg = <0x20>;
292 gpio-controller;
293 #gpio-cells = <2>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 interrupt-parent = <&gpio1>;
297 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
298 };
299
300 pcf_gpio_21: pcf8757@21 {
301 compatible = "ti,pcf8575", "nxp,pcf8575";
302 reg = <0x21>;
303 gpio-controller;
304 #gpio-cells = <2>;
305 interrupt-parent = <&gpio1>;
306 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
307 interrupt-controller;
308 #interrupt-cells = <2>;
309 };
310
311 pcf_hdmi: pcf8575@26 {
312 compatible = "ti,pcf8575", "nxp,pcf8575";
313 reg = <0x26>;
314 gpio-controller;
315 #gpio-cells = <2>;
316 p1 {
317 /* vin6_sel_s0: high: VIN6, low: audio */
318 gpio-hog;
319 gpios = <1 GPIO_ACTIVE_HIGH>;
320 output-low;
321 line-name = "vin6_sel_s0";
322 };
323 };
324
325 tlv320aic3106: tlv320aic3106@19 {
326 #sound-dai-cells = <0>;
327 compatible = "ti,tlv320aic3106";
328 reg = <0x19>;
329 adc-settle-ms = <40>;
330 ai3x-micbias-vg = <1>; /* 2.0V */
331 status = "okay";
332
333 /* Regulators */
334 AVDD-supply = <&vio_3v3>;
335 IOVDD-supply = <&vio_3v3>;
336 DRVDD-supply = <&vio_3v3>;
337 DVDD-supply = <&aic_dvdd>;
338 };
339};
340
341&cpu0 {
342 vdd-supply = <&buck10_reg>;
343};
344
345&mmc1 {
346 status = "okay";
347 vmmc-supply = <&vio_3v3_sd>;
348 vmmc_aux-supply = <&ldo4_reg>;
349 bus-width = <4>;
350 /*
351 * SDCD signal is not being used here - using the fact that GPIO mode
352 * is always hardwired.
353 */
354 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&mmc1_pins_default>;
357};
358
359&mmc2 {
360 status = "okay";
361 vmmc-supply = <&vio_1v8>;
362 bus-width = <8>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&mmc2_pins_default>;
365};
366
367/* No RTC on this device */
368&rtc {
369 status = "disabled";
370};
371
372&mac {
373 status = "okay";
374
375 dual_emac;
376};
377
378&cpsw_emac0 {
379 phy-handle = <&dp83867_0>;
380 phy-mode = "rgmii-id";
381 dual_emac_res_vlan = <1>;
382};
383
384&cpsw_emac1 {
385 phy-handle = <&dp83867_1>;
386 phy-mode = "rgmii-id";
387 dual_emac_res_vlan = <2>;
388};
389
390&davinci_mdio {
391 dp83867_0: ethernet-phy@2 {
392 reg = <2>;
393 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
394 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
395 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
396 ti,min-output-impedance;
397 };
398
399 dp83867_1: ethernet-phy@3 {
400 reg = <3>;
401 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
402 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
403 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
404 ti,min-output-impedance;
405 };
406};
407
408&usb2_phy1 {
409 phy-supply = <&ldo3_reg>;
410};
411
412&usb2_phy2 {
413 phy-supply = <&ldo3_reg>;
414};
415
416&qspi {
417 spi-max-frequency = <96000000>;
418 m25p80@0 {
419 spi-max-frequency = <96000000>;
420 };
421};
diff --git a/arch/arm/dts/dra76x.dtsi b/arch/arm/dts/dra76x.dtsi
new file mode 100644
index 0000000000..0176ce4da9
--- /dev/null
+++ b/arch/arm/dts/dra76x.dtsi
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "dra74x.dtsi"
10
11/ {
12 compatible = "ti,dra76", "ti,dra7";
13};
14
15&abb_mpu {
16 ti,abb_info = <
17 /*uV ABB efuse rbb_m fbb_m vset_m*/
18 1060000 0 0x0 0 0x02000000 0x01F00000
19 1160000 0 0x4 0 0x02000000 0x01F00000
20 1210000 0 0x8 0 0x02000000 0x01F00000
21 1250000 0 0xC 0 0x02000000 0x01F00000
22 >;
23};
24
25&mmc3 {
26 max-frequency = <96000000>;
27};
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 4c0e890194..489815e644 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -341,6 +341,9 @@
341/* Offset is 0.73V for LP873x */ 341/* Offset is 0.73V for LP873x */
342#define LP873X_BUCK_BASE_VOLT_UV 730000 342#define LP873X_BUCK_BASE_VOLT_UV 730000
343 343
344/* Offset is 0.73V for LP87565 */
345#define LP87565_BUCK_BASE_VOLT_UV 730000
346
344/* TPS659038 */ 347/* TPS659038 */
345#define TPS659038_I2C_SLAVE_ADDR 0x58 348#define TPS659038_I2C_SLAVE_ADDR 0x58
346#define TPS659038_REG_ADDR_SMPS12 0x23 349#define TPS659038_REG_ADDR_SMPS12 0x23
@@ -354,6 +357,7 @@
354#define TPS65917_REG_ADDR_SMPS1 0x23 357#define TPS65917_REG_ADDR_SMPS1 0x23
355#define TPS65917_REG_ADDR_SMPS2 0x27 358#define TPS65917_REG_ADDR_SMPS2 0x27
356#define TPS65917_REG_ADDR_SMPS3 0x2F 359#define TPS65917_REG_ADDR_SMPS3 0x2F
360#define TPS65917_REG_ADDR_SMPS4 0x33
357 361
358/* LP873X */ 362/* LP873X */
359#define LP873X_I2C_SLAVE_ADDR 0x60 363#define LP873X_I2C_SLAVE_ADDR 0x60
@@ -361,6 +365,11 @@
361#define LP873X_REG_ADDR_BUCK1 0x7 365#define LP873X_REG_ADDR_BUCK1 0x7
362#define LP873X_REG_ADDR_LDO1 0xA 366#define LP873X_REG_ADDR_LDO1 0xA
363 367
368/* LP87565 */
369#define LP87565_I2C_SLAVE_ADDR 0x61
370#define LP87565_REG_ADDR_BUCK01 0xA
371#define LP87565_REG_ADDR_BUCK23 0xE
372
364/* TPS */ 373/* TPS */
365#define TPS62361_I2C_SLAVE_ADDR 0x60 374#define TPS62361_I2C_SLAVE_ADDR 0x60
366#define TPS62361_REG_ADDR_SET0 0x0 375#define TPS62361_REG_ADDR_SET0 0x0
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index b5e5519fbd..aca5af86fc 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -58,6 +58,7 @@
58#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F 58#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
59#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F 59#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
60#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F 60#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
61#define DRA762_CONTROL_ID_CODE_ES1_0 0x0BB5002F
61#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F 62#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
62#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F 63#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F
63#define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F 64#define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 3e178be954..57f8ad2fd7 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -602,6 +602,7 @@ extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
602 602
603extern struct pmic_data tps659038; 603extern struct pmic_data tps659038;
604extern struct pmic_data lp8733; 604extern struct pmic_data lp8733;
605extern struct pmic_data lp87565;
605 606
606void hw_data_init(void); 607void hw_data_init(void);
607 608
@@ -702,6 +703,7 @@ static inline u8 is_omap54xx(void)
702 703
703#define DRA7XX 0x07000000 704#define DRA7XX 0x07000000
704#define DRA72X 0x07200000 705#define DRA72X 0x07200000
706#define DRA76X 0x07600000
705 707
706static inline u8 is_dra7xx(void) 708static inline u8 is_dra7xx(void)
707{ 709{
@@ -714,6 +716,12 @@ static inline u8 is_dra72x(void)
714 extern u32 *const omap_si_rev; 716 extern u32 *const omap_si_rev;
715 return (*omap_si_rev & 0xFFF00000) == DRA72X; 717 return (*omap_si_rev & 0xFFF00000) == DRA72X;
716} 718}
719
720static inline u8 is_dra76x(void)
721{
722 extern u32 *const omap_si_rev;
723 return (*omap_si_rev & 0xFFF00000) == DRA76X;
724}
717#endif 725#endif
718 726
719/* 727/*
@@ -741,6 +749,7 @@ static inline u8 is_dra72x(void)
741#define OMAP5432_ES2_0 0x54320200 749#define OMAP5432_ES2_0 0x54320200
742 750
743/* DRA7XX */ 751/* DRA7XX */
752#define DRA762_ES1_0 0x07620100
744#define DRA752_ES1_0 0x07520100 753#define DRA752_ES1_0 0x07520100
745#define DRA752_ES1_1 0x07520110 754#define DRA752_ES1_1 0x07520110
746#define DRA752_ES2_0 0x07520200 755#define DRA752_ES2_0 0x07520200
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 406010bbbe..abfdc2ef4f 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -229,4 +229,5 @@ int platform_fixup_disable_uhs_mode(void);
229struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode 229struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
230 (struct hsmmc *base, const char *mode); 230 (struct hsmmc *base, const char *mode);
231void vmmc_pbias_config(uint voltage); 231void vmmc_pbias_config(uint voltage);
232void board_mmc_poweron_ldo(uint voltage);
232#endif /* OMAP_MMC_H_ */ 233#endif /* OMAP_MMC_H_ */
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 8378488cb7..9f0beebcb9 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -35,6 +35,7 @@
35#include "mux_data.h" 35#include "mux_data.h"
36#include "../common/board_detect.h" 36#include "../common/board_detect.h"
37 37
38#define board_is_dra76x_evm() board_ti_is("DRA76/7x")
38#define board_is_dra74x_evm() board_ti_is("5777xCPU") 39#define board_is_dra74x_evm() board_ti_is("5777xCPU")
39#define board_is_dra72x_evm() board_ti_is("DRA72x-T") 40#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
40#define board_is_dra71x_evm() board_ti_is("DRA79x,D") 41#define board_is_dra71x_evm() board_ti_is("DRA79x,D")
@@ -210,6 +211,56 @@ const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
210 .emif_rd_wr_exec_thresh = 0x00000305 211 .emif_rd_wr_exec_thresh = 0x00000305
211}; 212};
212 213
214const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
215 .sdram_config_init = 0x61862B32,
216 .sdram_config = 0x61862B32,
217 .sdram_config2 = 0x00000000,
218 .ref_ctrl = 0x0000514C,
219 .ref_ctrl_final = 0x0000144A,
220 .sdram_tim1 = 0xD113783C,
221 .sdram_tim2 = 0x30B47FE3,
222 .sdram_tim3 = 0x409F8AD8,
223 .read_idle_ctrl = 0x00050000,
224 .zq_config = 0x5007190B,
225 .temp_alert_config = 0x00000000,
226 .emif_ddr_phy_ctlr_1_init = 0x0824400D,
227 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
228 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
229 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
230 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
231 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
232 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
233 .emif_rd_wr_lvl_rmp_win = 0x00000000,
234 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
235 .emif_rd_wr_lvl_ctl = 0x00000000,
236 .emif_rd_wr_exec_thresh = 0x00000305
237};
238
239const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
240 .sdram_config_init = 0x61862B32,
241 .sdram_config = 0x61862B32,
242 .sdram_config2 = 0x00000000,
243 .ref_ctrl = 0x0000514C,
244 .ref_ctrl_final = 0x0000144A,
245 .sdram_tim1 = 0xD113781C,
246 .sdram_tim2 = 0x30B47FE3,
247 .sdram_tim3 = 0x409F8AD8,
248 .read_idle_ctrl = 0x00050000,
249 .zq_config = 0x5007190B,
250 .temp_alert_config = 0x00000000,
251 .emif_ddr_phy_ctlr_1_init = 0x0824400D,
252 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
253 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
254 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
255 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
256 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
257 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
258 .emif_rd_wr_lvl_rmp_win = 0x00000000,
259 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
260 .emif_rd_wr_lvl_ctl = 0x00000000,
261 .emif_rd_wr_exec_thresh = 0x00000305
262};
263
213void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 264void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
214{ 265{
215 u64 ram_size; 266 u64 ram_size;
@@ -235,6 +286,12 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
235 break; 286 break;
236 } 287 }
237 break; 288 break;
289 case DRA762_ES1_0:
290 if (emif_nr == 1)
291 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
292 else
293 *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
294 break;
238 case DRA722_ES1_0: 295 case DRA722_ES1_0:
239 case DRA722_ES2_0: 296 case DRA722_ES2_0:
240 if (ram_size < CONFIG_MAX_MEM_MAPPED) 297 if (ram_size < CONFIG_MAX_MEM_MAPPED)
@@ -290,6 +347,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
290 ram_size = board_ti_get_emif_size(); 347 ram_size = board_ti_get_emif_size();
291 348
292 switch (omap_revision()) { 349 switch (omap_revision()) {
350 case DRA762_ES1_0:
293 case DRA752_ES1_0: 351 case DRA752_ES1_0:
294 case DRA752_ES1_1: 352 case DRA752_ES1_1:
295 case DRA752_ES2_0: 353 case DRA752_ES2_0:
@@ -357,6 +415,54 @@ struct vcores_data dra752_volts = {
357 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 415 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
358}; 416};
359 417
418struct vcores_data dra76x_volts = {
419 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
420 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
421 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
422 .mpu.addr = LP87565_REG_ADDR_BUCK01,
423 .mpu.pmic = &lp87565,
424 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
425
426 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
427 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
428 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
429 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
430 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
431 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
432 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
433 .eve.addr = TPS65917_REG_ADDR_SMPS1,
434 .eve.pmic = &tps659038,
435 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
436
437 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
438 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
439 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
440 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
441 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
442 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
443 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
444 .gpu.addr = LP87565_REG_ADDR_BUCK23,
445 .gpu.pmic = &lp87565,
446 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
447
448 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
449 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
450 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
451 .core.addr = TPS65917_REG_ADDR_SMPS3,
452 .core.pmic = &tps659038,
453
454 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
455 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
456 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
457 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
458 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
459 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
460 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
461 .iva.addr = TPS65917_REG_ADDR_SMPS4,
462 .iva.pmic = &tps659038,
463 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
464};
465
360struct vcores_data dra722_volts = { 466struct vcores_data dra722_volts = {
361 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 467 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
362 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 468 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
@@ -559,6 +665,8 @@ int board_late_init(void)
559 name = "dra71x"; 665 name = "dra71x";
560 else 666 else
561 name = "dra72x"; 667 name = "dra72x";
668 } else if (is_dra76x()) {
669 name = "dra76x";
562 } else { 670 } else {
563 name = "dra7xx"; 671 name = "dra7xx";
564 } 672 }
@@ -607,6 +715,8 @@ void do_board_detect(void)
607 bname = "DRA72x EVM"; 715 bname = "DRA72x EVM";
608 } else if (board_is_dra71x_evm()) { 716 } else if (board_is_dra71x_evm()) {
609 bname = "DRA71x EVM"; 717 bname = "DRA71x EVM";
718 } else if (board_is_dra76x_evm()) {
719 bname = "DRA76x EVM";
610 } else { 720 } else {
611 /* If EEPROM is not populated */ 721 /* If EEPROM is not populated */
612 if (is_dra72x()) 722 if (is_dra72x())
@@ -629,6 +739,8 @@ void vcores_update(void)
629 *omap_vcores = &dra722_volts; 739 *omap_vcores = &dra722_volts;
630 } else if (board_is_dra71x_evm()) { 740 } else if (board_is_dra71x_evm()) {
631 *omap_vcores = &dra718_volts; 741 *omap_vcores = &dra718_volts;
742 } else if (board_is_dra76x_evm()) {
743 *omap_vcores = &dra76x_volts;
632 } else { 744 } else {
633 /* If EEPROM is not populated */ 745 /* If EEPROM is not populated */
634 if (is_dra72x()) 746 if (is_dra72x())
@@ -683,6 +795,12 @@ void recalibrate_iodelay(void)
683 iodelay = dra742_es1_1_iodelay_cfg_array; 795 iodelay = dra742_es1_1_iodelay_cfg_array;
684 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); 796 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
685 break; 797 break;
798 case DRA762_ES1_0:
799 pads = dra76x_core_padconf_array;
800 npads = ARRAY_SIZE(dra76x_core_padconf_array);
801 iodelay = dra76x_es1_0_iodelay_cfg_array;
802 niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
803 break;
686 default: 804 default:
687 case DRA752_ES2_0: 805 case DRA752_ES2_0:
688 pads = dra74x_core_padconf_array; 806 pads = dra74x_core_padconf_array;
@@ -722,6 +840,21 @@ int board_mmc_init(bd_t *bis)
722 omap_mmc_init(1, 0, 0, -1, -1); 840 omap_mmc_init(1, 0, 0, -1, -1);
723 return 0; 841 return 0;
724} 842}
843
844void board_mmc_poweron_ldo(uint voltage)
845{
846 if (board_is_dra71x_evm()) {
847 if (voltage == LDO_VOLT_3V0)
848 voltage = 0x19;
849 else if (voltage == LDO_VOLT_1V8)
850 voltage = 0xa;
851 lp873x_mmc1_poweron_ldo(voltage);
852 } else if (board_is_dra76x_evm()) {
853 palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
854 } else {
855 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
856 }
857}
725#endif 858#endif
726 859
727#ifdef CONFIG_OMAP_HSMMC 860#ifdef CONFIG_OMAP_HSMMC
@@ -1037,8 +1170,8 @@ static inline void vtt_regulator_enable(void)
1037 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 1170 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1038 return; 1171 return;
1039 1172
1040 /* Do not enable VTT for DRA722 */ 1173 /* Do not enable VTT for DRA722 or DRA76x */
1041 if (is_dra72x()) 1174 if (is_dra72x() || is_dra76x())
1042 return; 1175 return;
1043 1176
1044 /* 1177 /*
@@ -1069,7 +1202,9 @@ int board_fit_config_name_match(const char *name)
1069 } else if (!strcmp(name, "dra72-evm")) { 1202 } else if (!strcmp(name, "dra72-evm")) {
1070 return 0; 1203 return 0;
1071 } 1204 }
1072 } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) { 1205 } else if (is_dra76x() && !strcmp(name, "dra76-evm")) {
1206 return 0;
1207 } else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) {
1073 return 0; 1208 return 0;
1074 } 1209 }
1075 1210
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index e70f8e6b8c..535b4f5e1e 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -866,6 +866,194 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = {
866 866
867}; 867};
868 868
869const struct pad_conf_entry dra76x_core_padconf_array[] = {
870 {GPMC_AD0, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad0.vout3_d0 */
871 {GPMC_AD1, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad1.vout3_d1 */
872 {GPMC_AD2, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad2.vout3_d2 */
873 {GPMC_AD3, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad3.vout3_d3 */
874 {GPMC_AD4, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad4.vout3_d4 */
875 {GPMC_AD5, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad5.vout3_d5 */
876 {GPMC_AD6, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad6.vout3_d6 */
877 {GPMC_AD7, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad7.vout3_d7 */
878 {GPMC_AD8, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad8.vout3_d8 */
879 {GPMC_AD9, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad9.vout3_d9 */
880 {GPMC_AD10, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad10.vout3_d10 */
881 {GPMC_AD11, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad11.vout3_d11 */
882 {GPMC_AD12, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad12.vout3_d12 */
883 {GPMC_AD13, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad13.vout3_d13 */
884 {GPMC_AD14, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad14.vout3_d14 */
885 {GPMC_AD15, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad15.vout3_d15 */
886 {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vout3_d16 */
887 {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vout3_d17 */
888 {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vout3_d18 */
889 {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vout3_d19 */
890 {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vout3_d20 */
891 {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vout3_d21 */
892 {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vout3_d22 */
893 {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vout3_d23 */
894 {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vout3_hsync */
895 {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vout3_vsync */
896 {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vout3_de */
897 {GPMC_A11, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a11.gpio2_1 */
898 {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */
899 {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
900 {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
901 {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
902 {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
903 {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
904 {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
905 {GPMC_A19, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a19.mmc2_dat4 */
906 {GPMC_A20, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a20.mmc2_dat5 */
907 {GPMC_A21, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a21.mmc2_dat6 */
908 {GPMC_A22, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a22.mmc2_dat7 */
909 {GPMC_A23, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a23.mmc2_clk */
910 {GPMC_A24, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a24.mmc2_dat0 */
911 {GPMC_A25, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a25.mmc2_dat1 */
912 {GPMC_A26, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a26.mmc2_dat2 */
913 {GPMC_A27, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a27.mmc2_dat3 */
914 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
915 {GPMC_CS0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_cs0.gpmc_cs0 */
916 {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
917 {GPMC_CS3, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs3.vout3_clk */
918 {GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpmc_advn_ale */
919 {GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpmc_oen_ren */
920 {GPMC_WEN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpmc_wen */
921 {GPMC_BEN0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_ben0.gpmc_ben0 */
922 {GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpmc_wait0 */
923 {VIN1A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin1a_fld0.gpio3_1 */
924 {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_clk0.vin2a_clk0 */
925 {VIN2A_DE0, (M15 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_de0.Driveroff */
926 {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */
927 {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_hsync0.vin2a_hsync0 */
928 {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_vsync0.vin2a_vsync0 */
929 {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d0.vin2a_d0 */
930 {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d1.vin2a_d1 */
931 {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d2.vin2a_d2 */
932 {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d3.vin2a_d3 */
933 {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d4.vin2a_d4 */
934 {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.vin2a_d5 */
935 {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d6.vin2a_d6 */
936 {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d7.vin2a_d7 */
937 {VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d8.vin2a_d8 */
938 {VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d9.vin2a_d9 */
939 {VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d10.vin2a_d10 */
940 {VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d11.vin2a_d11 */
941 {VIN2A_D12, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
942 {VIN2A_D13, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
943 {VIN2A_D14, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
944 {VIN2A_D15, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
945 {VIN2A_D16, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
946 {VIN2A_D17, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
947 {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
948 {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
949 {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
950 {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
951 {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
952 {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
953 {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
954 {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_de.vout1_de */
955 {VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)}, /* vout1_fld.gpio4_21 */
956 {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
957 {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
958 {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
959 {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
960 {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
961 {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
962 {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
963 {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
964 {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
965 {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
966 {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
967 {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
968 {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
969 {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
970 {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
971 {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
972 {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
973 {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
974 {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
975 {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
976 {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
977 {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
978 {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
979 {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
980 {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
981 {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
982 {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
983 {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
984 {RGMII0_TXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
985 {RGMII0_TXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
986 {RGMII0_TXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
987 {RGMII0_TXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
988 {RGMII0_TXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
989 {RGMII0_TXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
990 {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
991 {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
992 {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
993 {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
994 {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
995 {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
996 {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
997 {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
998 {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
999 {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
1000 {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
1001 {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
1002 {MCASP1_ACLKX, (M14 | 0x00070000)}, /* mcasp1_aclkx.gpio7_31 */
1003 {MCASP1_FSX, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.gpio7_30 */
1004 {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
1005 {MCASP1_AXR1, (M10 | 0x000f0000)}, /* mcasp1_axr1.i2c5_scl */
1006 {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
1007 {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
1008 {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
1009 {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
1010 {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
1011 {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
1012 {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
1013 {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
1014 {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
1015 {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
1016 {MCASP2_ACLKR, (M15 | PIN_INPUT_PULLUP)}, /* mcasp2_aclkr.Driveroff */
1017 {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
1018 {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
1019 {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
1020 {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
1021 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
1022 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
1023 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
1024 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
1025 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
1026 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
1027 {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */
1028 {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
1029 {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
1030 {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
1031 {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
1032 {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
1033 {SPI1_CS2, (M6 | 0x000f0000)}, /* spi1_cs2.hdmi1_hpd */
1034 {SPI1_CS3, (M6 | 0x000f0000)}, /* spi1_cs3.hdmi1_cec */
1035 {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
1036 {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
1037 {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
1038 {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
1039 {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
1040 {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */
1041 {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
1042 {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
1043 {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
1044 {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
1045 {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */
1046 {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
1047 {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
1048 {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
1049 {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
1050 {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
1051 {WAKEUP0, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_0 */
1052 {WAKEUP1, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_1 */
1053 {WAKEUP2, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq2 */
1054 {WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */
1055};
1056
869#ifdef CONFIG_IODELAY_RECALIBRATION 1057#ifdef CONFIG_IODELAY_RECALIBRATION
870const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = { 1058const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = {
871 {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ 1059 {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
@@ -1077,6 +1265,112 @@ const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = {
1077#endif 1265#endif
1078 1266
1079}; 1267};
1268
1269const struct iodelay_cfg_entry dra76x_es1_0_iodelay_cfg_array[] = {
1270 {0x011C, 787, 0}, /* CFG_GPMC_A0_OUT */
1271 {0x0128, 1181, 0}, /* CFG_GPMC_A10_OUT */
1272 {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
1273 {0x0150, 2149, 1052}, /* CFG_GPMC_A14_IN */
1274 {0x015C, 2121, 997}, /* CFG_GPMC_A15_IN */
1275 {0x0168, 2159, 1134}, /* CFG_GPMC_A16_IN */
1276 {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
1277 {0x0174, 2135, 1085}, /* CFG_GPMC_A17_IN */
1278 {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
1279 {0x01A0, 592, 0}, /* CFG_GPMC_A1_OUT */
1280 {0x020C, 641, 0}, /* CFG_GPMC_A2_OUT */
1281 {0x0218, 1481, 0}, /* CFG_GPMC_A3_OUT */
1282 {0x0224, 1775, 0}, /* CFG_GPMC_A4_OUT */
1283 {0x0230, 785, 0}, /* CFG_GPMC_A5_OUT */
1284 {0x023C, 848, 0}, /* CFG_GPMC_A6_OUT */
1285 {0x0248, 851, 0}, /* CFG_GPMC_A7_OUT */
1286 {0x0254, 1783, 0}, /* CFG_GPMC_A8_OUT */
1287 {0x0260, 951, 0}, /* CFG_GPMC_A9_OUT */
1288 {0x026C, 1091, 0}, /* CFG_GPMC_AD0_OUT */
1289 {0x0278, 1027, 0}, /* CFG_GPMC_AD10_OUT */
1290 {0x0284, 824, 0}, /* CFG_GPMC_AD11_OUT */
1291 {0x0290, 1196, 0}, /* CFG_GPMC_AD12_OUT */
1292 {0x029C, 754, 0}, /* CFG_GPMC_AD13_OUT */
1293 {0x02A8, 665, 0}, /* CFG_GPMC_AD14_OUT */
1294 {0x02B4, 1027, 0}, /* CFG_GPMC_AD15_OUT */
1295 {0x02C0, 937, 0}, /* CFG_GPMC_AD1_OUT */
1296 {0x02CC, 1168, 0}, /* CFG_GPMC_AD2_OUT */
1297 {0x02D8, 872, 0}, /* CFG_GPMC_AD3_OUT */
1298 {0x02E4, 1092, 0}, /* CFG_GPMC_AD4_OUT */
1299 {0x02F0, 576, 0}, /* CFG_GPMC_AD5_OUT */
1300 {0x02FC, 1113, 0}, /* CFG_GPMC_AD6_OUT */
1301 {0x0308, 943, 0}, /* CFG_GPMC_AD7_OUT */
1302 {0x0314, 0, 0}, /* CFG_GPMC_AD8_OUT */
1303 {0x0320, 0, 0}, /* CFG_GPMC_AD9_OUT */
1304 {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
1305 {0x0380, 1801, 948}, /* CFG_GPMC_CS3_OUT */
1306 {0x06F0, 451, 0}, /* CFG_RGMII0_RXC_IN */
1307 {0x06FC, 127, 1571}, /* CFG_RGMII0_RXCTL_IN */
1308 {0x0708, 165, 1178}, /* CFG_RGMII0_RXD0_IN */
1309 {0x0714, 136, 1302}, /* CFG_RGMII0_RXD1_IN */
1310 {0x0720, 0, 1520}, /* CFG_RGMII0_RXD2_IN */
1311 {0x072C, 28, 1690}, /* CFG_RGMII0_RXD3_IN */
1312 {0x0740, 121, 0}, /* CFG_RGMII0_TXC_OUT */
1313 {0x074C, 60, 0}, /* CFG_RGMII0_TXCTL_OUT */
1314 {0x0758, 153, 0}, /* CFG_RGMII0_TXD0_OUT */
1315 {0x0764, 35, 0}, /* CFG_RGMII0_TXD1_OUT */
1316 {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
1317 {0x077C, 172, 0}, /* CFG_RGMII0_TXD3_OUT */
1318 {0x0A38, 0, 0}, /* CFG_VIN2A_CLK0_IN */
1319 {0x0A44, 2180, 0}, /* CFG_VIN2A_D0_IN */
1320 {0x0A50, 2297, 110}, /* CFG_VIN2A_D10_IN */
1321 {0x0A5C, 1938, 0}, /* CFG_VIN2A_D11_IN */
1322 {0x0A70, 147, 0}, /* CFG_VIN2A_D12_OUT */
1323 {0x0A7C, 110, 0}, /* CFG_VIN2A_D13_OUT */
1324 {0x0A88, 18, 0}, /* CFG_VIN2A_D14_OUT */
1325 {0x0A94, 82, 0}, /* CFG_VIN2A_D15_OUT */
1326 {0x0AA0, 33, 0}, /* CFG_VIN2A_D16_OUT */
1327 {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
1328 {0x0AB0, 417, 0}, /* CFG_VIN2A_D18_IN */
1329 {0x0ABC, 156, 843}, /* CFG_VIN2A_D19_IN */
1330 {0x0AC8, 2326, 309}, /* CFG_VIN2A_D1_IN */
1331 {0x0AD4, 223, 1413}, /* CFG_VIN2A_D20_IN */
1332 {0x0AE0, 169, 1415}, /* CFG_VIN2A_D21_IN */
1333 {0x0AEC, 43, 1150}, /* CFG_VIN2A_D22_IN */
1334 {0x0AF8, 0, 1210}, /* CFG_VIN2A_D23_IN */
1335 {0x0B04, 2057, 0}, /* CFG_VIN2A_D2_IN */
1336 {0x0B10, 2440, 257}, /* CFG_VIN2A_D3_IN */
1337 {0x0B1C, 2142, 0}, /* CFG_VIN2A_D4_IN */
1338 {0x0B28, 2455, 252}, /* CFG_VIN2A_D5_IN */
1339 {0x0B34, 1883, 0}, /* CFG_VIN2A_D6_IN */
1340 {0x0B40, 2229, 0}, /* CFG_VIN2A_D7_IN */
1341 {0x0B4C, 2250, 151}, /* CFG_VIN2A_D8_IN */
1342 {0x0B58, 2279, 27}, /* CFG_VIN2A_D9_IN */
1343 {0x0B7C, 2233, 0}, /* CFG_VIN2A_HSYNC0_IN */
1344 {0x0B88, 1936, 0}, /* CFG_VIN2A_VSYNC0_IN */
1345 {0x0B9C, 1281, 497}, /* CFG_VOUT1_CLK_OUT */
1346 {0x0BA8, 379, 0}, /* CFG_VOUT1_D0_OUT */
1347 {0x0BB4, 441, 0}, /* CFG_VOUT1_D10_OUT */
1348 {0x0BC0, 461, 0}, /* CFG_VOUT1_D11_OUT */
1349 {0x0BCC, 1189, 0}, /* CFG_VOUT1_D12_OUT */
1350 {0x0BD8, 312, 0}, /* CFG_VOUT1_D13_OUT */
1351 {0x0BE4, 298, 0}, /* CFG_VOUT1_D14_OUT */
1352 {0x0BF0, 284, 0}, /* CFG_VOUT1_D15_OUT */
1353 {0x0BFC, 152, 0}, /* CFG_VOUT1_D16_OUT */
1354 {0x0C08, 216, 0}, /* CFG_VOUT1_D17_OUT */
1355 {0x0C14, 408, 0}, /* CFG_VOUT1_D18_OUT */
1356 {0x0C20, 519, 0}, /* CFG_VOUT1_D19_OUT */
1357 {0x0C2C, 475, 0}, /* CFG_VOUT1_D1_OUT */
1358 {0x0C38, 316, 0}, /* CFG_VOUT1_D20_OUT */
1359 {0x0C44, 59, 0}, /* CFG_VOUT1_D21_OUT */
1360 {0x0C50, 221, 0}, /* CFG_VOUT1_D22_OUT */
1361 {0x0C5C, 96, 0}, /* CFG_VOUT1_D23_OUT */
1362 {0x0C68, 264, 0}, /* CFG_VOUT1_D2_OUT */
1363 {0x0C74, 421, 0}, /* CFG_VOUT1_D3_OUT */
1364 {0x0C80, 1257, 0}, /* CFG_VOUT1_D4_OUT */
1365 {0x0C8C, 432, 0}, /* CFG_VOUT1_D5_OUT */
1366 {0x0C98, 436, 0}, /* CFG_VOUT1_D6_OUT */
1367 {0x0CA4, 440, 0}, /* CFG_VOUT1_D7_OUT */
1368 {0x0CB0, 81, 100}, /* CFG_VOUT1_D8_OUT */
1369 {0x0CBC, 471, 0}, /* CFG_VOUT1_D9_OUT */
1370 {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */
1371 {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */
1372 {0x0CEC, 815, 0}, /* CFG_VOUT1_VSYNC_OUT */
1373};
1080#endif 1374#endif
1081 1375
1082 1376
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 36a0acaa0b..e125593e41 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -37,6 +37,8 @@ CONFIG_CMD_USB_MASS_STORAGE=y
37CONFIG_SPI_FLASH=y 37CONFIG_SPI_FLASH=y
38CONFIG_SPI_FLASH_BAR=y 38CONFIG_SPI_FLASH_BAR=y
39CONFIG_SPI_FLASH_SPANSION=y 39CONFIG_SPI_FLASH_SPANSION=y
40CONFIG_PMIC_LP87565=y
41CONFIG_DM_REGULATOR_LP87565=y
40CONFIG_SYS_NS16550=y 42CONFIG_SYS_NS16550=y
41CONFIG_TI_QSPI=y 43CONFIG_TI_QSPI=y
42CONFIG_TIMER=y 44CONFIG_TIMER=y
@@ -49,12 +51,12 @@ CONFIG_USB_DWC3_PHY_OMAP=y
49CONFIG_USB_GADGET=y 51CONFIG_USB_GADGET=y
50CONFIG_FIT=y 52CONFIG_FIT=y
51CONFIG_SPL_OF_LIBFDT=y 53CONFIG_SPL_OF_LIBFDT=y
52CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm" 54CONFIG_SPL_LOAD_FIT=y
55CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
53CONFIG_DM_ETH=y 56CONFIG_DM_ETH=y
54CONFIG_DM_PMIC=y 57CONFIG_DM_PMIC=y
55CONFIG_PMIC_PALMAS=y 58CONFIG_PMIC_PALMAS=y
56CONFIG_PMIC_LP873X=y 59CONFIG_PMIC_LP873X=y
57CONFIG_SPL_LOAD_FIT=y
58CONFIG_DISK=y 60CONFIG_DISK=y
59CONFIG_DWC_AHCI=y 61CONFIG_DWC_AHCI=y
60CONFIG_DM_MMC=y 62CONFIG_DM_MMC=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index c055711e43..87efcb262d 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -41,6 +41,8 @@ CONFIG_DM_MMC=y
41CONFIG_SPI_FLASH=y 41CONFIG_SPI_FLASH=y
42CONFIG_SPI_FLASH_BAR=y 42CONFIG_SPI_FLASH_BAR=y
43CONFIG_SPI_FLASH_SPANSION=y 43CONFIG_SPI_FLASH_SPANSION=y
44CONFIG_PMIC_LP87565=y
45CONFIG_DM_REGULATOR_LP87565=y
44CONFIG_SYS_NS16550=y 46CONFIG_SYS_NS16550=y
45CONFIG_TI_QSPI=y 47CONFIG_TI_QSPI=y
46CONFIG_TIMER=y 48CONFIG_TIMER=y
@@ -55,7 +57,7 @@ CONFIG_FIT=y
55CONFIG_SPL_OF_LIBFDT=y 57CONFIG_SPL_OF_LIBFDT=y
56CONFIG_SPL_LOAD_FIT=y 58CONFIG_SPL_LOAD_FIT=y
57CONFIG_SPL_PANIC_ON_NON_FIT_IMAGE=y 59CONFIG_SPL_PANIC_ON_NON_FIT_IMAGE=y
58CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm" 60CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
59CONFIG_DM_ETH=y 61CONFIG_DM_ETH=y
60CONFIG_DM_PMIC=y 62CONFIG_DM_PMIC=y
61CONFIG_PMIC_PALMAS=y 63CONFIG_PMIC_PALMAS=y
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c
index 23a5dc7580..64278866f1 100644
--- a/drivers/power/palmas.c
+++ b/drivers/power/palmas.c
@@ -41,7 +41,7 @@ int lp873x_mmc1_poweron_ldo(uint voltage)
41} 41}
42#endif 42#endif
43 43
44int palmas_mmc1_poweron_ldo(uint voltage) 44int palmas_mmc1_poweron_ldo(uint ldo_volt, uint ldo_ctrl, uint voltage)
45{ 45{
46 u8 val = 0; 46 u8 val = 0;
47 47
@@ -50,13 +50,13 @@ int palmas_mmc1_poweron_ldo(uint voltage)
50 * Currently valid for the dra7xx_evm board: 50 * Currently valid for the dra7xx_evm board:
51 * Set TPS659038 LDO1 to 3.0 V 51 * Set TPS659038 LDO1 to 3.0 V
52 */ 52 */
53 if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_VOLTAGE, voltage)) { 53 if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, ldo_volt, voltage)) {
54 printf("tps65903x: could not set LDO1 voltage.\n"); 54 printf("tps65903x: could not set LDO1 voltage.\n");
55 return 1; 55 return 1;
56 } 56 }
57 /* TURN ON LDO1 */ 57 /* TURN ON LDO1 */
58 val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE; 58 val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE;
59 if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_CTRL, val)) { 59 if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, ldo_ctrl, val)) {
60 printf("tps65903x: could not turn on LDO1.\n"); 60 printf("tps65903x: could not turn on LDO1.\n");
61 return 1; 61 return 1;
62 } 62 }
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 00fcacbdd3..aa56efc66f 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -149,3 +149,10 @@ config PMIC_LP873X
149 ---help--- 149 ---help---
150 The LP873X is a PMIC containing couple of LDOs and couple of SMPS. 150 The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
151 This driver binds the pmic children. 151 This driver binds the pmic children.
152
153config PMIC_LP87565
154 bool "Enable driver for Texas Instruments LP87565 PMIC"
155 depends on DM_PMIC
156 ---help---
157 The LP87565 is a PMIC containing a bunch of SMPS.
158 This driver binds the pmic children.
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 334a24fdb7..b953c03a14 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
17obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o 17obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
18obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o 18obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
19obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o 19obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
20obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
20 21
21obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o 22obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
22obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o 23obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
diff --git a/drivers/power/pmic/lp87565.c b/drivers/power/pmic/lp87565.c
new file mode 100644
index 0000000000..a5f29d7760
--- /dev/null
+++ b/drivers/power/pmic/lp87565.c
@@ -0,0 +1,89 @@
1/*
2 * (C) Copyright 2017 Texas Instruments Incorporated, <www.ti.com>
3 * Keerthy <j-keerthy@ti.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <fdtdec.h>
10#include <errno.h>
11#include <dm.h>
12#include <i2c.h>
13#include <power/pmic.h>
14#include <power/regulator.h>
15#include <power/lp87565.h>
16#include <dm/device.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
20static const struct pmic_child_info pmic_children_info[] = {
21 { .prefix = "buck", .driver = LP87565_BUCK_DRIVER },
22 { },
23};
24
25static int lp87565_write(struct udevice *dev, uint reg, const uint8_t *buff,
26 int len)
27{
28 int ret;
29
30 ret = dm_i2c_write(dev, reg, buff, len);
31 if (ret)
32 error("write error to device: %p register: %#x!", dev, reg);
33
34 return ret;
35}
36
37static int lp87565_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
38{
39 int ret;
40
41 ret = dm_i2c_read(dev, reg, buff, len);
42 if (ret)
43 error("read error from device: %p register: %#x!", dev, reg);
44
45 return ret;
46}
47
48static int lp87565_bind(struct udevice *dev)
49{
50 int regulators_node;
51 const void *blob = gd->fdt_blob;
52 int children;
53 int node = dev->of_offset;
54
55 regulators_node = fdt_subnode_offset(blob, node, "regulators");
56 if (regulators_node <= 0) {
57 debug("%s: %s regulators subnode not found!", __func__,
58 dev->name);
59 return -ENXIO;
60 }
61
62 debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
63
64 children = pmic_bind_children(dev, regulators_node, pmic_children_info);
65 if (!children)
66 printf("%s: %s - no child found\n", __func__, dev->name);
67
68 /* Always return success for this device */
69 return 0;
70}
71
72static struct dm_pmic_ops lp87565_ops = {
73 .read = lp87565_read,
74 .write = lp87565_write,
75};
76
77static const struct udevice_id lp87565_ids[] = {
78 { .compatible = "ti,lp87565", .data = LP87565 },
79 { .compatible = "ti,lp87565-q1", .data = LP87565_Q1 },
80 { }
81};
82
83U_BOOT_DRIVER(pmic_lp87565) = {
84 .name = "lp87565_pmic",
85 .id = UCLASS_PMIC,
86 .of_match = lp87565_ids,
87 .bind = lp87565_bind,
88 .ops = &lp87565_ops,
89};
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 35af579cba..8696d7dce7 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -139,3 +139,13 @@ config DM_REGULATOR_LP873X
139 This enables implementation of driver-model regulator uclass 139 This enables implementation of driver-model regulator uclass
140 features for REGULATOR LP873X and the family of LP873X PMICs. 140 features for REGULATOR LP873X and the family of LP873X PMICs.
141 The driver implements get/set api for: value and enable. 141 The driver implements get/set api for: value and enable.
142
143config DM_REGULATOR_LP87565
144 bool "Enable driver for LP87565 PMIC regulators"
145 depends on PMIC_LP87565
146 ---help---
147 This enables implementation of driver-model regulator uclass
148 features for REGULATOR LP87565 and the family of LP87565 PMICs.
149 LP87565 series of PMICs have 4 single phase BUCKs that can also
150 be configured in multi phase modes. The driver implements
151 get/set api for value and enable.
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 2d350cb2fe..2862bcc1b1 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
17obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o 17obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
18obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o 18obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o
19obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o 19obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
20obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
diff --git a/drivers/power/regulator/lp87565_regulator.c b/drivers/power/regulator/lp87565_regulator.c
new file mode 100644
index 0000000000..2a0b8ca642
--- /dev/null
+++ b/drivers/power/regulator/lp87565_regulator.c
@@ -0,0 +1,199 @@
1/*
2 * (C) Copyright 2017
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Keerthy <j-keerthy@ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
11#include <fdtdec.h>
12#include <errno.h>
13#include <dm.h>
14#include <i2c.h>
15#include <power/pmic.h>
16#include <power/regulator.h>
17#include <power/lp87565.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21static const char lp87565_buck_ctrl1[LP87565_BUCK_NUM] = {0x2, 0x4, 0x6, 0x8, 0x2, 0x6};
22static const char lp87565_buck_vout[LP87565_BUCK_NUM] = {0xA, 0xC, 0xE, 0x10, 0xA, 0xE };
23
24static int lp87565_buck_enable(struct udevice *dev, int op, bool *enable)
25{
26 int ret;
27 unsigned int adr;
28 struct dm_regulator_uclass_platdata *uc_pdata;
29
30 uc_pdata = dev_get_uclass_platdata(dev);
31 adr = uc_pdata->ctrl_reg;
32
33 ret = pmic_reg_read(dev->parent, adr);
34 if (ret < 0)
35 return ret;
36
37 if (op == PMIC_OP_GET) {
38 ret &= LP87565_BUCK_MODE_MASK;
39
40 if (ret)
41 *enable = true;
42 else
43 *enable = false;
44
45 return 0;
46 } else if (op == PMIC_OP_SET) {
47 if (*enable)
48 ret |= LP87565_BUCK_MODE_MASK;
49 else
50 ret &= ~LP87565_BUCK_MODE_MASK;
51 ret = pmic_reg_write(dev->parent, adr, ret);
52 if (ret)
53 return ret;
54 }
55
56 return 0;
57}
58
59static int lp87565_buck_volt2val(int uV)
60{
61 if (uV > LP87565_BUCK_VOLT_MAX)
62 return -EINVAL;
63 else if (uV > 1400000)
64 return (uV - 1420000) / 20000 + 0x9E;
65 else if (uV > 730000)
66 return (uV - 735000) / 5000 + 0x18;
67 else if (uV >= 500000)
68 return (uV - 500000) / 10000;
69 else
70 return -EINVAL;
71}
72
73static int lp87565_buck_val2volt(int val)
74{
75 if (val > LP87565_BUCK_VOLT_MAX_HEX)
76 return -EINVAL;
77 else if (val > 0x9D)
78 return 1400000 + (val - 0x9D) * 20000;
79 else if (val > 0x17)
80 return 730000 + (val - 0x17) * 5000;
81 else if (val >= 0x0)
82 return 500000 + val * 10000;
83 else
84 return -EINVAL;
85}
86
87static int lp87565_buck_val(struct udevice *dev, int op, int *uV)
88{
89 unsigned int hex, adr;
90 int ret;
91 struct dm_regulator_uclass_platdata *uc_pdata;
92
93 uc_pdata = dev_get_uclass_platdata(dev);
94
95 if (op == PMIC_OP_GET)
96 *uV = 0;
97
98 adr = uc_pdata->volt_reg;
99
100 ret = pmic_reg_read(dev->parent, adr);
101 if (ret < 0)
102 return ret;
103
104 if (op == PMIC_OP_GET) {
105 ret &= LP87565_BUCK_VOLT_MASK;
106 ret = lp87565_buck_val2volt(ret);
107 if (ret < 0)
108 return ret;
109 *uV = ret;
110
111 return 0;
112 }
113
114 hex = lp87565_buck_volt2val(*uV);
115 if (hex < 0)
116 return hex;
117
118 ret &= 0x0;
119 ret = hex;
120
121 ret = pmic_reg_write(dev->parent, adr, ret);
122
123 return ret;
124}
125
126static int lp87565_buck_probe(struct udevice *dev)
127{
128 struct dm_regulator_uclass_platdata *uc_pdata;
129 int idx;
130
131 uc_pdata = dev_get_uclass_platdata(dev);
132 uc_pdata->type = REGULATOR_TYPE_BUCK;
133
134 idx = dev->driver_data;
135 if (idx == 0 || idx == 1 || idx == 2 || idx == 3) {
136 debug("Single phase regulator\n");
137 } else if (idx == 23) {
138 idx = 5;
139 } else if (idx == 10) {
140 idx = 4;
141 } else {
142 printf("Wrong ID for regulator\n");
143 return -EINVAL;
144 }
145
146 uc_pdata->ctrl_reg = lp87565_buck_ctrl1[idx];
147 uc_pdata->volt_reg = lp87565_buck_vout[idx];
148
149 return 0;
150}
151
152static int buck_get_value(struct udevice *dev)
153{
154 int uV;
155 int ret;
156
157 ret = lp87565_buck_val(dev, PMIC_OP_GET, &uV);
158 if (ret)
159 return ret;
160
161 return uV;
162}
163
164static int buck_set_value(struct udevice *dev, int uV)
165{
166 return lp87565_buck_val(dev, PMIC_OP_SET, &uV);
167}
168
169static bool buck_get_enable(struct udevice *dev)
170{
171 bool enable = false;
172 int ret;
173
174
175 ret = lp87565_buck_enable(dev, PMIC_OP_GET, &enable);
176 if (ret)
177 return ret;
178
179 return enable;
180}
181
182static int buck_set_enable(struct udevice *dev, bool enable)
183{
184 return lp87565_buck_enable(dev, PMIC_OP_SET, &enable);
185}
186
187static const struct dm_regulator_ops lp87565_buck_ops = {
188 .get_value = buck_get_value,
189 .set_value = buck_set_value,
190 .get_enable = buck_get_enable,
191 .set_enable = buck_set_enable,
192};
193
194U_BOOT_DRIVER(lp87565_buck) = {
195 .name = LP87565_BUCK_DRIVER,
196 .id = UCLASS_REGULATOR,
197 .ops = &lp87565_buck_ops,
198 .probe = lp87565_buck_probe,
199};
diff --git a/drivers/power/regulator/palmas_regulator.c b/drivers/power/regulator/palmas_regulator.c
index cce7cd2fc2..b40bad2042 100644
--- a/drivers/power/regulator/palmas_regulator.c
+++ b/drivers/power/regulator/palmas_regulator.c
@@ -377,7 +377,11 @@ static int palmas_smps_probe(struct udevice *dev)
377 uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx]; 377 uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
378 uc_pdata->volt_reg = palmas_smps_volt[type][idx]; 378 uc_pdata->volt_reg = palmas_smps_volt[type][idx];
379 break; 379 break;
380 380 case 12:
381 idx = 0;
382 uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
383 uc_pdata->volt_reg = palmas_smps_volt[type][idx];
384 break;
381 default: 385 default:
382 printf("Wrong ID for regulator\n"); 386 printf("Wrong ID for regulator\n");
383 } 387 }
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index ceaa0bd0b1..ea0f3b8424 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -16,6 +16,7 @@
16#include <asm/omap_gpio.h> 16#include <asm/omap_gpio.h>
17#include <asm/omap_common.h> 17#include <asm/omap_common.h>
18#include <asm/ti-common/ti-edma3.h> 18#include <asm/ti-common/ti-edma3.h>
19#include <linux/kernel.h>
19 20
20DECLARE_GLOBAL_DATA_PTR; 21DECLARE_GLOBAL_DATA_PTR;
21 22
@@ -117,21 +118,18 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
117 if (!hz) 118 if (!hz)
118 clk_div = 0; 119 clk_div = 0;
119 else 120 else
120 clk_div = (priv->fclk / hz) - 1; 121 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
122
123 /* truncate clk_div value to QSPI_CLK_DIV_MAX */
124 if (clk_div > QSPI_CLK_DIV_MAX)
125 clk_div = QSPI_CLK_DIV_MAX;
121 126
122 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); 127 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
123 128
124 /* disable SCLK */ 129 /* disable SCLK */
125 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, 130 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
126 &priv->base->clk_ctrl); 131 &priv->base->clk_ctrl);
127 132 /* enable SCLK and program the clk divider */
128 /* assign clk_div values */
129 if (clk_div < 0)
130 clk_div = 0;
131 else if (clk_div > QSPI_CLK_DIV_MAX)
132 clk_div = QSPI_CLK_DIV_MAX;
133
134 /* enable SCLK */
135 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); 133 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
136} 134}
137 135
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 171cc9aa36..975679c238 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -128,6 +128,8 @@
128 "setenv fdtfile dra72-evm.dtb; fi;" \ 128 "setenv fdtfile dra72-evm.dtb; fi;" \
129 "if test $board_name = dra71x; then " \ 129 "if test $board_name = dra71x; then " \
130 "setenv fdtfile dra71-evm.dtb; fi;" \ 130 "setenv fdtfile dra71-evm.dtb; fi;" \
131 "if test $board_name = dra76x; then " \
132 "setenv fdtfile dra76-evm.dtb; fi;" \
131 "if test $board_name = beagle_x15; then " \ 133 "if test $board_name = beagle_x15; then " \
132 "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ 134 "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
133 "if test $board_name = beagle_x15_revb1; then " \ 135 "if test $board_name = beagle_x15_revb1; then " \
diff --git a/include/palmas.h b/include/palmas.h
index 96ba8ed566..5addf97eca 100644
--- a/include/palmas.h
+++ b/include/palmas.h
@@ -35,6 +35,10 @@
35#define LDO2_CTRL 0x52 35#define LDO2_CTRL 0x52
36#define LDO2_VOLTAGE 0x53 36#define LDO2_VOLTAGE 0x53
37 37
38/* LDO2 control/voltage */
39#define LDO4_CTRL 0x5e
40#define LDO4_VOLTAGE 0x5f
41
38/* LDO9 control/voltage */ 42/* LDO9 control/voltage */
39#define LDO9_CTRL 0x60 43#define LDO9_CTRL 0x60
40#define LDO9_VOLTAGE 0x61 44#define LDO9_VOLTAGE 0x61
@@ -126,7 +130,7 @@ static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
126} 130}
127 131
128void palmas_init_settings(void); 132void palmas_init_settings(void);
129int palmas_mmc1_poweron_ldo(uint voltage); 133int palmas_mmc1_poweron_ldo(uint ldo_volt, uint ldo_ctrl, uint voltage);
130int lp873x_mmc1_poweron_ldo(uint voltage); 134int lp873x_mmc1_poweron_ldo(uint voltage);
131int twl603x_mmc1_set_ldo9(u8 vsel); 135int twl603x_mmc1_set_ldo9(u8 vsel);
132int twl603x_audio_power(u8 on); 136int twl603x_audio_power(u8 on);
diff --git a/include/power/lp87565.h b/include/power/lp87565.h
new file mode 100644
index 0000000000..5160f5df6c
--- /dev/null
+++ b/include/power/lp87565.h
@@ -0,0 +1,12 @@
1#define LP87565 0x0
2#define LP87565_Q1 0x1
3
4#define LP87565_BUCK_NUM 6
5
6/* Drivers name */
7#define LP87565_BUCK_DRIVER "lp87565_buck"
8
9#define LP87565_BUCK_VOLT_MASK 0xFF
10#define LP87565_BUCK_VOLT_MAX_HEX 0xFF
11#define LP87565_BUCK_VOLT_MAX 3360000
12#define LP87565_BUCK_MODE_MASK 0x80