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authorVishal Mahaveer2017-12-17 16:05:27 -0600
committerVishal Mahaveer2017-12-17 16:05:27 -0600
commit2437280fb7209d0d5cbd8c590cb998978c77f4eb (patch)
tree94a510e226af9516b27157110b4023ff6fdd19f1
parent6f6aaabf5ae197b6a64787565c5f5843483b3a1c (diff)
parent4a7f3c93d75b07bf68a8927a0ba4c7160c507611 (diff)
downloadu-boot-2437280fb7209d0d5cbd8c590cb998978c77f4eb.tar.gz
u-boot-2437280fb7209d0d5cbd8c590cb998978c77f4eb.tar.xz
u-boot-2437280fb7209d0d5cbd8c590cb998978c77f4eb.zip
Merge remote-tracking branch 'bb/lcard_bringup_o_revb' into p-ti-u-boot-2016.05
Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Conflicts: arch/arm/cpu/armv7/omap-common/utils.c board/ti/dra7xx/evm.c board/ti/dra7xx/mux_data.h configs/dra7xx_evm_nodt_defconfig Change-Id: I1c1189efc6325a32a3763ba0442c383a29f12d68
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c2
-rw-r--r--board/ti/dra7xx/evm.c155
-rw-r--r--board/ti/dra7xx/mux_data.h475
-rw-r--r--configs/dra7xx_evm_nodt_defconfig1
4 files changed, 253 insertions, 380 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index ae25a74638..22d6f041ea 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -706,7 +706,7 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = {
706const struct ctrl_ioregs ioregs_dra72x_es2 = { 706const struct ctrl_ioregs ioregs_dra72x_es2 = {
707 .ctrl_ddrch = 0x40404040, 707 .ctrl_ddrch = 0x40404040,
708 .ctrl_lpddr2ch = 0x40404040, 708 .ctrl_lpddr2ch = 0x40404040,
709 .ctrl_ddr3ch = 0x60606060, 709 .ctrl_ddr3ch = 0x80808080,
710 .ctrl_ddrio_0 = 0x00094A40, 710 .ctrl_ddrio_0 = 0x00094A40,
711 .ctrl_ddrio_1 = 0x00000000, 711 .ctrl_ddrio_1 = 0x00000000,
712 .ctrl_ddrio_2 = 0x00000000, 712 .ctrl_ddrio_2 = 0x00000000,
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 08c0987afe..4c38621766 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -39,6 +39,7 @@
39#define board_is_dra74x_evm() board_ti_is("5777xCPU") 39#define board_is_dra74x_evm() board_ti_is("5777xCPU")
40#define board_is_dra72x_evm() board_ti_is("DRA72x-T") 40#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
41#define board_is_dra71x_evm() board_ti_is("DRA79x,D") 41#define board_is_dra71x_evm() board_ti_is("DRA79x,D")
42#define board_is_dra71x_lcard() board_ti_is("DRA71x_L")
42#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \ 43#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
43 (strncmp("H", board_ti_get_rev(), 1) <= 0)) 44 (strncmp("H", board_ti_get_rev(), 1) <= 0))
44#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \ 45#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
@@ -137,12 +138,12 @@ static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
137}; 138};
138 139
139const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = { 140const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
140 .sdram_config_init = 0x61862BB2, 141 .sdram_config_init = 0x62822BB2,
141 .sdram_config = 0x61862BB2, 142 .sdram_config = 0x62822BB2,
142 .sdram_config2 = 0x00000000, 143 .sdram_config2 = 0x00000000,
143 .ref_ctrl = 0x0000514D, 144 .ref_ctrl = 0x0000514D,
144 .ref_ctrl_final = 0x0000144A, 145 .ref_ctrl_final = 0x0000144A,
145 .sdram_tim1 = 0xD1137824, 146 .sdram_tim1 = 0xD113783C,
146 .sdram_tim2 = 0x30B37FE3, 147 .sdram_tim2 = 0x30B37FE3,
147 .sdram_tim3 = 0x409F8AD8, 148 .sdram_tim3 = 0x409F8AD8,
148 .read_idle_ctrl = 0x00050000, 149 .read_idle_ctrl = 0x00050000,
@@ -571,6 +572,54 @@ struct vcores_data dra718_volts = {
571 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 572 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
572}; 573};
573 574
575struct vcores_data dra718_lcard_volts = {
576 /*
577 * In the case of dra71x GPU MPU and CORE
578 * are all powered up by SMPS1
579 */
580 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
581 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
582 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
583 .mpu.addr = TPS65917_REG_ADDR_SMPS1,
584 .mpu.pmic = &tps659038,
585 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
586
587 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
588 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
589 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
590 .core.addr = TPS65917_REG_ADDR_SMPS1,
591 .core.pmic = &tps659038,
592
593 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
594 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
595 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
596 .gpu.addr = TPS65917_REG_ADDR_SMPS1,
597 .gpu.pmic = &tps659038,
598 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
599
600 /*
601 * The DSPEVE and IVA rails are grouped on DRA71x-evm
602 * and are powered by SMPS3
603 */
604 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
605 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
606 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
607 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
608 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
609 .eve.addr = TPS65917_REG_ADDR_SMPS3,
610 .eve.pmic = &tps659038,
611 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
612
613 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
614 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
615 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
616 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
617 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
618 .iva.addr = TPS65917_REG_ADDR_SMPS3,
619 .iva.pmic = &tps659038,
620 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
621};
622
574int get_voltrail_opp(int rail_offset) 623int get_voltrail_opp(int rail_offset)
575{ 624{
576 int opp; 625 int opp;
@@ -749,6 +798,8 @@ void vcores_update(void)
749 *omap_vcores = &dra722_volts; 798 *omap_vcores = &dra722_volts;
750 } else if (board_is_dra71x_evm()) { 799 } else if (board_is_dra71x_evm()) {
751 *omap_vcores = &dra718_volts; 800 *omap_vcores = &dra718_volts;
801 } else if (board_is_dra71x_lcard()) {
802 *omap_vcores = &dra718_lcard_volts;
752 } else if (board_is_dra76x_evm()) { 803 } else if (board_is_dra76x_evm()) {
753 *omap_vcores = &dra76x_volts; 804 *omap_vcores = &dra76x_volts;
754 } else { 805 } else {
@@ -762,8 +813,13 @@ void vcores_update(void)
762 813
763void set_muxconf_regs(void) 814void set_muxconf_regs(void)
764{ 815{
765 do_set_mux32((*ctrl)->control_padconf_core_base, 816 if (board_is_dra71x_lcard()) {
766 early_padconf, ARRAY_SIZE(early_padconf)); 817 do_set_mux32((*ctrl)->control_padconf_core_base,
818 dra71x_lcard_early_padconf, ARRAY_SIZE(dra71x_lcard_early_padconf));
819 } else {
820 do_set_mux32((*ctrl)->control_padconf_core_base,
821 early_padconf, ARRAY_SIZE(early_padconf));
822 }
767} 823}
768 824
769#ifdef CONFIG_IODELAY_RECALIBRATION 825#ifdef CONFIG_IODELAY_RECALIBRATION
@@ -785,6 +841,11 @@ void recalibrate_iodelay(void)
785 npads = ARRAY_SIZE(dra71x_core_padconf_array); 841 npads = ARRAY_SIZE(dra71x_core_padconf_array);
786 iodelay = dra71_iodelay_cfg_array; 842 iodelay = dra71_iodelay_cfg_array;
787 niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array); 843 niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
844 } else if (board_is_dra71x_lcard()) {
845 pads = dra71x_lcard_core_padconf_array;
846 npads = ARRAY_SIZE(dra71x_lcard_core_padconf_array);
847 iodelay = dra71_lcard_iodelay_cfg_array;
848 niodelays = ARRAY_SIZE(dra71_lcard_iodelay_cfg_array);
788 } else if (board_is_dra72x_revc_or_later()) { 849 } else if (board_is_dra72x_revc_or_later()) {
789 delta_pads = dra72x_rgmii_padconf_array_revc; 850 delta_pads = dra72x_rgmii_padconf_array_revc;
790 delta_npads = 851 delta_npads =
@@ -875,90 +936,6 @@ void board_mmc_poweron_ldo(uint voltage)
875#endif 936#endif
876 937
877#ifdef CONFIG_OMAP_HSMMC 938#ifdef CONFIG_OMAP_HSMMC
878#if defined(CONFIG_IODELAY_RECALIBRATION) && \
879 (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC))
880
881struct pinctrl_desc {
882 const char *name;
883 struct omap_hsmmc_pinctrl_state *pinctrl;
884};
885
886static struct pinctrl_desc pinctrl_descs_hsmmc1[] = {
887 {"default", &hsmmc1_default},
888 {"hs", &hsmmc1_default},
889 {NULL}
890};
891
892static struct pinctrl_desc pinctrl_descs_hsmmc2_rev20[] = {
893 {"default", &hsmmc2_default_hs},
894 {"hs", &hsmmc2_default_hs},
895 {"ddr_1_8v", &hsmmc2_ddr_1v8_rev20},
896 {"hs200_1_8v", &hsmmc2_hs200_1v8_rev20},
897 {NULL}
898};
899
900static struct pinctrl_desc pinctrl_descs_hsmmc2_rev11[] = {
901 {"default", &hsmmc2_default_hs},
902 {"hs", &hsmmc2_default_hs},
903 {"ddr_1_8v", &hsmmc2_ddr_1v8_rev11},
904 {"hs200_1_8v", &hsmmc2_hs200_1v8_rev11},
905 {NULL}
906};
907
908static struct pinctrl_desc pinctrl_descs_hsmmc2_dra72x[] = {
909 {"default", &hsmmc2_default_hs},
910 {"hs", &hsmmc2_default_hs},
911 {"ddr_1_8v", &hsmmc2_ddr_1v8_dra72},
912 {"hs200_1_8v", &hsmmc2_hs200_1v8_dra72},
913 {NULL}
914};
915
916static struct pinctrl_desc pinctrl_descs_hsmmc2_dra76x[] = {
917 {"default", &hsmmc2_default_hs},
918 {"hs", &hsmmc2_default_hs},
919 {"ddr_1_8v", &hsmmc2_default_hs},
920 {"hs200_1_8v", &hsmmc2_hs200_1v8_dra76},
921 {NULL}
922};
923
924struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
925 (struct hsmmc *base, const char *mode)
926{
927 struct pinctrl_desc *p = NULL;
928
929 switch ((uint32_t)base) {
930 case OMAP_HSMMC1_BASE:
931 p = pinctrl_descs_hsmmc1;
932 break;
933 case OMAP_HSMMC2_BASE:
934 if ((omap_revision() == DRA752_ES1_0) ||
935 (omap_revision() == DRA752_ES1_1))
936 p = pinctrl_descs_hsmmc2_rev11;
937 else if (is_dra72x())
938 p = pinctrl_descs_hsmmc2_dra72x;
939 else if (is_dra76x())
940 p = pinctrl_descs_hsmmc2_dra76x;
941 else if (is_dra7xx())
942 p = pinctrl_descs_hsmmc2_rev20;
943 break;
944 default:
945 break;
946 }
947
948 if (!p) {
949 printf("%s no pinctrl defined for MMC@%p\n", __func__,
950 base);
951 return NULL;
952 }
953 while (p->name) {
954 if (strcmp(mode, p->name) == 0)
955 return p->pinctrl;
956 p++;
957 }
958 return NULL;
959}
960#endif
961
962int platform_fixup_disable_uhs_mode(void) 939int platform_fixup_disable_uhs_mode(void)
963{ 940{
964 return omap_revision() == DRA752_ES1_1; 941 return omap_revision() == DRA752_ES1_1;
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 37a75f9b89..02d5be36ae 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -527,6 +527,158 @@ const struct pad_conf_entry dra71x_core_padconf_array[] = {
527#endif 527#endif
528}; 528};
529 529
530const struct pad_conf_entry dra71x_lcard_core_padconf_array[] = {
531 {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
532 {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
533 {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
534 {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
535 {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
536 {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
537 {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
538 {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
539 {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
540 {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
541 {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
542 {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
543 {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
544 {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
545 {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
546 {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
547 {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
548 {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
549 {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
550 {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
551 {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
552 {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
553 {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
554 {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
555 {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
556 {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
557 {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
558 {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */
559 {GPMC_A12, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a12.gpio2_2 */
560 {GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.gpio2_3 */
561 {GPMC_A14, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a14.gpio2_4 */
562 {GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.gpio2_5 */
563 {GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.gpio2_6 */
564 {GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.gpio2_7 */
565 {GPMC_A18, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a18.gpio2_8 */
566 {GPMC_A19, (M1 | PIN_INPUT)}, /* gpmc_a19.mmc2_dat4 */
567 {GPMC_A20, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a20.mmc2_dat5 */
568 {GPMC_A21, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a21.mmc2_dat6 */
569 {GPMC_A22, (M1 | PIN_INPUT)}, /* gpmc_a22.mmc2_dat7 */
570 {GPMC_A23, (M1 | PIN_INPUT)}, /* gpmc_a23.mmc2_clk */
571 {GPMC_A24, (M1 | PIN_INPUT)}, /* gpmc_a24.mmc2_dat0 */
572 {GPMC_A25, (M1 | PIN_INPUT)}, /* gpmc_a25.mmc2_dat1 */
573 {GPMC_A26, (M1 | PIN_INPUT)}, /* gpmc_a26.mmc2_dat2 */
574 {GPMC_A27, (M1 | PIN_INPUT)}, /* gpmc_a27.mmc2_dat3 */
575 {GPMC_CS1, (M1 | PIN_INPUT)}, /* gpmc_cs1.mmc2_cmd */
576 {GPMC_CS0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs0.gpio2_19 */
577 {GPMC_CS2, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.gpio2_20 */
578 {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
579 {GPMC_CLK, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_clk.gpio2_22 */
580 {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */
581 {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */
582 {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */
583 {GPMC_BEN0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_ben0.gpio2_26 */
584 {GPMC_BEN1, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_ben1.gpio2_27 */
585 {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */
586 {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_clk0.vin2a_clk0 */
587 {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_hsync0.vin2a_hsync0 */
588 {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_vsync0.vin2a_vsync0 */
589 {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d0.vin2a_d0 */
590 {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d1.vin2a_d1 */
591 {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d2.vin2a_d2 */
592 {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d3.vin2a_d3 */
593 {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d4.vin2a_d4 */
594 {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.vin2a_d5 */
595 {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d6.vin2a_d6 */
596 {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d7.vin2a_d7 */
597 {VIN2A_D10, (M3 | PIN_INPUT_PULLUP)}, /* vin2a_d10.mdio_mclk */
598 {VIN2A_D11, (M3 | PIN_INPUT_PULLUP)}, /* vin2a_d11.mdio_d */
599 {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
600 {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
601 {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
602 {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
603 {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
604 {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
605 {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
606 {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
607 {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
608 {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
609 {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
610 {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
611 {MDIO_MCLK, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.gpio5_15 */
612 {MDIO_D, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.gpio5_16 */
613 {UART3_RXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_rxd.gpio5_18 */
614 {RGMII0_RXD3, (M14 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd3.gpio5_28 */
615 {RGMII0_RXD2, (M14 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd2.gpio5_29 */
616 {RGMII0_RXD1, (M14 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd1.gpio5_30 */
617 {RGMII0_RXD0, (M14 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd0.gpio5_31 */
618 {USB1_DRVVBUS, (M14 | PIN_OUTPUT)}, /* usb1_drvvbus.gpio6_12 */
619 {USB2_DRVVBUS, (M14 | PIN_OUTPUT)}, /* usb2_drvvbus.gpio6_13 */
620 {GPIO6_14, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_14.gpio6_14 */
621 {GPIO6_15, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_15.gpio6_15 */
622 {XREF_CLK3, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.atl_clk3 */
623 {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE15)}, /* mcasp2_aclkx.mcasp2_aclkx */
624 {MCASP2_FSX, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE15)}, /* mcasp2_fsx.mcasp2_fsx */
625 {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp2_axr0.mcasp2_axr0 */
626 {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp2_axr1.mcasp2_axr1 */
627 {MCASP2_AXR2, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE8)}, /* mcasp2_axr2.mcasp3_axr2 */
628 {MCASP2_AXR3, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE8)}, /* mcasp2_axr3.mcasp3_axr3 */
629 {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp2_axr4.mcasp2_axr4 */
630 {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp2_axr5.mcasp2_axr5 */
631 {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* mcasp3_aclkx.mcasp3_aclkx */
632 {MCASP3_FSX, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE8)}, /* mcasp3_fsx.mcasp3_fsx */
633 {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE8)}, /* mcasp3_axr0.mcasp3_axr0 */
634 {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
635 {MCASP4_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.mcasp4_aclkx */
636 {MCASP4_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.mcasp4_fsx */
637 {MCASP4_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.mcasp4_axr0 */
638 {MCASP4_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr1.mcasp4_axr1 */
639 {MCASP5_ACLKX, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp5_aclkx.mcasp5_aclkx */
640 {MCASP5_FSX, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp5_fsx.mcasp5_fsx */
641 {MCASP5_AXR0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp5_axr0.mcasp5_axr0 */
642 {MCASP5_AXR1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp5_axr1.mcasp5_axr1 */
643 {MMC1_CLK, (M0 | PIN_INPUT)}, /* mmc1_clk.mmc1_clk */
644 {MMC1_CMD, (M0 | PIN_INPUT)}, /* mmc1_cmd.mmc1_cmd */
645 {MMC1_DAT0, (M0 | PIN_INPUT)}, /* mmc1_dat0.mmc1_dat0 */
646 {MMC1_DAT1, (M0 | PIN_INPUT)}, /* mmc1_dat1.mmc1_dat1 */
647 {MMC1_DAT2, (M0 | PIN_INPUT)}, /* mmc1_dat2.mmc1_dat2 */
648 {MMC1_DAT3, (M0 | PIN_INPUT)}, /* mmc1_dat3.mmc1_dat3 */
649 {GPIO6_10, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_10.ehrpwm2A */
650 {GPIO6_11, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_11.ehrpwm2B */
651 {MMC3_CLK, (M14 | PIN_INPUT_PULLUP)}, /* mmc3_clk.gpio6_29 */
652 {MMC3_CMD, (M14 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.gpio6_30 */
653 {MMC3_DAT0, (M2 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.uart5_rxd */
654 {MMC3_DAT1, (M2 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.uart5_txd */
655 {MMC3_DAT2, (M2 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.uart5_ctsn */
656 {MMC3_DAT3, (M2 | PIN_INPUT_PULLUP)}, /* mmc3_dat3.uart5_rtsn */
657 {MMC3_DAT4, (M10 | PIN_INPUT_PULLUP)}, /* mmc3_dat4.ehrpwm3A */
658 {MMC3_DAT5, (M14 | PIN_INPUT_PULLUP)}, /* mmc3_dat5.gpio1_23 */
659 {MMC3_DAT6, (M14 | PIN_INPUT_PULLUP)}, /* mmc3_dat6.gpio1_24 */
660 {MMC3_DAT7, (M14 | PIN_INPUT_PULLUP)}, /* mmc3_dat7.gpio1_25 */
661 {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
662 {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
663 {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
664 {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
665 {SPI1_CS1, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs1.spi1_cs1 */
666 {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
667 {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
668 {UART1_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.uart9_rxd */
669 {UART1_RTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.uart9_txd */
670 {UART2_RXD, (M14 | PIN_INPUT)}, /* uart2_rxd.gpio7_26 */
671 {UART2_TXD, (M14 | PIN_INPUT)}, /* uart2_txd.gpio7_27 */
672 {UART2_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.uart3_rxd */
673 {UART2_RTSN, (M1 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.uart3_txd */
674 {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
675 {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
676 {WAKEUP0, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_0 */
677 {WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */
678 {MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */
679 {MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */
680};
681
530const struct pad_conf_entry early_padconf[] = { 682const struct pad_conf_entry early_padconf[] = {
531#if (CONFIG_CONS_INDEX == 1) 683#if (CONFIG_CONS_INDEX == 1)
532 {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */ 684 {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
@@ -539,6 +691,13 @@ const struct pad_conf_entry early_padconf[] = {
539 {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */ 691 {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */
540}; 692};
541 693
694const struct pad_conf_entry dra71x_lcard_early_padconf[] = {
695 {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
696 {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
697 {I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */
698 {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */
699};
700
542#ifdef CONFIG_IODELAY_RECALIBRATION 701#ifdef CONFIG_IODELAY_RECALIBRATION
543const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revb[] = { 702const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revb[] = {
544 {0x6F0, 359, 0}, /* RGMMI0_RXC_IN */ 703 {0x6F0, 359, 0}, /* RGMMI0_RXC_IN */
@@ -661,6 +820,32 @@ const struct iodelay_cfg_entry dra71_iodelay_cfg_array[] = {
661 {0x0B7C, 1943, 0}, /* CFG_VIN2A_HSYNC0_IN */ 820 {0x0B7C, 1943, 0}, /* CFG_VIN2A_HSYNC0_IN */
662 {0x0B88, 1612, 0}, /* CFG_VIN2A_VSYNC0_IN */ 821 {0x0B88, 1612, 0}, /* CFG_VIN2A_VSYNC0_IN */
663}; 822};
823
824const struct iodelay_cfg_entry dra71_lcard_iodelay_cfg_array[] = {
825 {0x0A38, 0, 0}, /* CFG_VIN2A_CLK0_IN */
826 {0x0A44, 1936, 0}, /* CFG_VIN2A_D0_IN */
827 {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
828 {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
829 {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
830 {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
831 {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
832 {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
833 {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
834 {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
835 {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
836 {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
837 {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
838 {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
839 {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
840 {0x0B04, 1736, 0}, /* CFG_VIN2A_D2_IN */
841 {0x0B10, 1943, 0}, /* CFG_VIN2A_D3_IN */
842 {0x0B1C, 1601, 0}, /* CFG_VIN2A_D4_IN */
843 {0x0B28, 2052, 0}, /* CFG_VIN2A_D5_IN */
844 {0x0B34, 1571, 0}, /* CFG_VIN2A_D6_IN */
845 {0x0B40, 1855, 0}, /* CFG_VIN2A_D7_IN */
846 {0x0B7C, 1943, 0}, /* CFG_VIN2A_HSYNC0_IN */
847 {0x0B88, 1612, 0}, /* CFG_VIN2A_VSYNC0_IN */
848};
664#endif 849#endif
665 850
666const struct pad_conf_entry dra74x_core_padconf_array[] = { 851const struct pad_conf_entry dra74x_core_padconf_array[] = {
@@ -1463,294 +1648,4 @@ const struct iodelay_cfg_entry dra76x_es1_0_iodelay_cfg_array[] = {
1463}; 1648};
1464#endif 1649#endif
1465 1650
1466
1467#if defined(CONFIG_IODELAY_RECALIBRATION) && \
1468 (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC)) && \
1469 defined(CONFIG_OMAP_HSMMC)
1470
1471static struct pad_conf_entry hsmmc1_default_padconf[] = {
1472 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP) /* mmc1_clk.clk */},
1473 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP) /* mmc1_cmd.cmd */},
1474 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat0.dat0 */},
1475 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat1.dat1 */},
1476 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat2.dat2 */},
1477 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat3.dat3 */},
1478};
1479
1480static struct pad_conf_entry mmc2_pins_default_hs[] = {
1481 {GPMC_A23, (M1 | PIN_INPUT_PULLUP) /* g pmc_a23.mmc2_clk */},
1482 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP) /* gpmc_cs1.mmc2_cmd */},
1483 {GPMC_A24, (M1 | PIN_INPUT_PULLUP) /* gpmc_a24.mmc2_dat0 */},
1484 {GPMC_A25, (M1 | PIN_INPUT_PULLUP) /* gpmc_a25.mmc2_dat1 */},
1485 {GPMC_A26, (M1 | PIN_INPUT_PULLUP) /* gpmc_a26.mmc2_dat2 */},
1486 {GPMC_A27, (M1 | PIN_INPUT_PULLUP) /* gpmc_a27.mmc2_dat3 */},
1487 {GPMC_A19, (M1 | PIN_INPUT_PULLUP) /* gpmc_a19.mmc2_dat4 */},
1488 {GPMC_A20, (M1 | PIN_INPUT_PULLUP) /* gpmc_a20.mmc2_dat5 */},
1489 {GPMC_A21, (M1 | PIN_INPUT_PULLUP) /* gpmc_a21.mmc2_dat6 */},
1490 {GPMC_A22, (M1 | PIN_INPUT_PULLUP) /* gpmc_a22.mmc2_dat7 */},
1491};
1492
1493static struct pad_conf_entry mmc2_pins_ddr_hs200_1_8v[] = {
1494 {GPMC_A23, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a23.mmc2_clk */},
1495 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_cs1.mmc2_cmd */},
1496 {GPMC_A24, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a24.mmc2_dat0 */},
1497 {GPMC_A25, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a25.mmc2_dat1 */},
1498 {GPMC_A26, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a26.mmc2_dat2 */},
1499 {GPMC_A27, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a27.mmc2_dat3 */},
1500 {GPMC_A19, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a19.mmc2_dat4 */},
1501 {GPMC_A20, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a20.mmc2_dat5 */},
1502 {GPMC_A21, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a21.mmc2_dat6 */},
1503 {GPMC_A22, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a22.mmc2_dat7 */},
1504};
1505
1506static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_rev11_conf[] = {
1507 {0x190, 621, 600 /* CFG_GPMC_A19_OEN */},
1508 {0x194, 300, 0 /* CFG_GPMC_A19_OUT */},
1509 {0x1a8, 739, 600 /* CFG_GPMC_A20_OEN */},
1510 {0x1ac, 240, 0 /* CFG_GPMC_A20_OUT */},
1511 {0x1b4, 812, 600 /* CFG_GPMC_A21_OEN */},
1512 {0x1b8, 240, 0 /* CFG_GPMC_A21_OUT */},
1513 {0x1c0, 954, 600 /* CFG_GPMC_A22_OEN */},
1514 {0x1c4, 60, 0 /* CFG_GPMC_A22_OUT */},
1515 {0x1d0, 1340, 420 /* CFG_GPMC_A23_OUT */},
1516 {0x1d8, 935, 600 /* CFG_GPMC_A24_OEN */},
1517 {0x1dc, 0, 0 /* CFG_GPMC_A24_OUT */},
1518 {0x1e4, 525, 600 /* CFG_GPMC_A25_OEN */},
1519 {0x1e8, 120, 0 /* CFG_GPMC_A25_OUT */},
1520 {0x1f0, 767, 600 /* CFG_GPMC_A26_OEN */},
1521 {0x1f4, 225, 0 /* CFG_GPMC_A26_OUT */},
1522 {0x1fc, 565, 600 /* CFG_GPMC_A27_OEN */},
1523 {0x200, 60, 0 /* CFG_GPMC_A27_OUT */},
1524 {0x364, 969, 600 /* CFG_GPMC_CS1_OEN */},
1525 {0x368, 180, 0 /* CFG_GPMC_CS1_OUT */},
1526};
1527
1528static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_rev20_conf[] = {
1529 {0x190, 274, 0 /* CFG_GPMC_A19_OEN */},
1530 {0x194, 162, 0 /* CFG_GPMC_A19_OUT */},
1531 {0x1a8, 401, 0 /* CFG_GPMC_A20_OEN */},
1532 {0x1ac, 73, 0 /* CFG_GPMC_A20_OUT */},
1533 {0x1b4, 465, 0 /* CFG_GPMC_A21_OEN */},
1534 {0x1b8, 115, 0 /* CFG_GPMC_A21_OUT */},
1535 {0x1c0, 633, 0 /* CFG_GPMC_A22_OEN */},
1536 {0x1c4, 47, 0 /* CFG_GPMC_A22_OUT */},
1537 {0x1d0, 935, 280 /* CFG_GPMC_A23_OUT */},
1538 {0x1d8, 621, 0 /* CFG_GPMC_A24_OEN */},
1539 {0x1dc, 0, 0 /* CFG_GPMC_A24_OUT */},
1540 {0x1e4, 183, 0 /* CFG_GPMC_A25_OEN */},
1541 {0x1e8, 0, 0 /* CFG_GPMC_A25_OUT */},
1542 {0x1f0, 467, 0 /* CFG_GPMC_A26_OEN */},
1543 {0x1f4, 0, 0 /* CFG_GPMC_A26_OUT */},
1544 {0x1fc, 262, 0 /* CFG_GPMC_A27_OEN */},
1545 {0x200, 46, 0 /* CFG_GPMC_A27_OUT */},
1546 {0x364, 684, 0 /* CFG_GPMC_CS1_OEN */},
1547 {0x368, 76, 0 /* CFG_GPMC_CS1_OUT */},
1548};
1549
1550static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_rev11_conf[] = {
1551 {0x18c, 0, 0 /* CFG_GPMC_A19_IN */},
1552 {0x1a4, 274, 240 /* CFG_GPMC_A20_IN */},
1553 {0x1b0, 0, 60 /* CFG_GPMC_A21_IN */},
1554 {0x1bc, 0, 60 /* CFG_GPMC_A22_IN */},
1555 {0x1c8, 514, 360 /* CFG_GPMC_A23_IN */},
1556 {0x1d4, 187, 120 /* CFG_GPMC_A24_IN */},
1557 {0x1e0, 0, 0 /* CFG_GPMC_A25_IN */},
1558 {0x1ec, 0, 60 /* CFG_GPMC_A26_IN */},
1559 {0x1f8, 121, 60 /* CFG_GPMC_A27_IN */},
1560 {0x360, 0, 0 /* CFG_GPMC_CS1_IN */},
1561 {0x190, 0, 0 /* CFG_GPMC_A19_OEN */},
1562 {0x194, 174, 0 /* CFG_GPMC_A19_OUT */},
1563 {0x1a8, 0, 0 /* CFG_GPMC_A20_OEN */},
1564 {0x1ac, 168, 0 /* CFG_GPMC_A20_OUT */},
1565 {0x1b4, 0, 0 /* CFG_GPMC_A21_OEN */},
1566 {0x1b8, 136, 0 /* CFG_GPMC_A21_OUT */},
1567 {0x1c0, 0, 0 /* CFG_GPMC_A22_OEN */},
1568 {0x1c4, 0, 0 /* CFG_GPMC_A22_OUT */},
1569 {0x1d0, 879, 0 /* CFG_GPMC_A23_OUT */},
1570 {0x1d8, 0, 0 /* CFG_GPMC_A24_OEN */},
1571 {0x1dc, 0, 0 /* CFG_GPMC_A24_OUT */},
1572 {0x1e4, 0, 0 /* CFG_GPMC_A25_OEN */},
1573 {0x1e8, 34, 0 /* CFG_GPMC_A25_OUT */},
1574 {0x1f0, 0, 0 /* CFG_GPMC_A26_OEN */},
1575 {0x1f4, 120, 0 /* CFG_GPMC_A26_OUT */},
1576 {0x1fc, 0, 0 /* CFG_GPMC_A27_OEN */},
1577 {0x200, 0, 0 /* CFG_GPMC_A27_OUT */},
1578 {0x364, 0, 0 /* CFG_GPMC_CS1_OEN */},
1579 {0x368, 11, 0 /* CFG_GPMC_CS1_OUT */},
1580};
1581
1582static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_rev20_conf[] = {
1583 {0x18c, 270, 0 /* CFG_GPMC_A19_IN */},
1584 {0x1a4, 0, 0 /* CFG_GPMC_A20_IN */},
1585 {0x1b0, 170, 0 /* CFG_GPMC_A21_IN */},
1586 {0x1bc, 758, 0 /* CFG_GPMC_A22_IN */},
1587 {0x1c8, 0, 0 /* CFG_GPMC_A23_IN */},
1588 {0x1d4, 81, 0 /* CFG_GPMC_A24_IN */},
1589 {0x1e0, 286, 0 /* CFG_GPMC_A25_IN */},
1590 {0x1ec, 0, 0 /* CFG_GPMC_A26_IN */},
1591 {0x1f8, 123, 0 /* CFG_GPMC_A27_IN */},
1592 {0x360, 346, 0 /* CFG_GPMC_CS1_IN */},
1593 {0x190, 0, 0 /* CFG_GPMC_A19_OEN */},
1594 {0x194, 55, 0 /* CFG_GPMC_A19_OUT */},
1595 {0x1a8, 0, 0 /* CFG_GPMC_A20_OEN */},
1596 {0x1ac, 422, 0 /* CFG_GPMC_A20_OUT */},
1597 {0x1b4, 642, 0 /* CFG_GPMC_A21_OEN */},
1598 {0x1b8, 0, 0 /* CFG_GPMC_A21_OUT */},
1599 {0x1c0, 0, 0 /* CFG_GPMC_A22_OEN */},
1600 {0x1c4, 128, 0 /* CFG_GPMC_A22_OUT */},
1601 {0x1d0, 0, 0 /* CFG_GPMC_A23_OUT */},
1602 {0x1d8, 0, 0 /* CFG_GPMC_A24_OEN */},
1603 {0x1dc, 395, 0 /* CFG_GPMC_A24_OUT */},
1604 {0x1e4, 0, 0 /* CFG_GPMC_A25_OEN */},
1605 {0x1e8, 0, 0 /* CFG_GPMC_A25_OUT */},
1606 {0x1f0, 623, 0 /* CFG_GPMC_A26_OEN */},
1607 {0x1f4, 0, 0 /* CFG_GPMC_A26_OUT */},
1608 {0x1fc, 54, 0 /* CFG_GPMC_A27_OEN */},
1609 {0x200, 0, 0 /* CFG_GPMC_A27_OUT */},
1610 {0x364, 0, 0 /* CFG_GPMC_CS1_OEN */},
1611 {0x368, 0, 0 /* CFG_GPMC_CS1_OUT */},
1612};
1613
1614static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_dra72_conf[] = {
1615 {0x18c, 0, 0, /* CFG_GPMC_A19_IN */},
1616 {0x1a4, 121, 0, /* CFG_GPMC_A20_IN */},
1617 {0x1b0, 0, 0, /* CFG_GPMC_A21_IN */},
1618 {0x1bc, 20, 0, /* CFG_GPMC_A22_IN */},
1619 {0x1c8, 108, 0, /* CFG_GPMC_A23_IN */},
1620 {0x1d4, 31, 0, /* CFG_GPMC_A24_IN */},
1621 {0x1e0, 0, 0, /* CFG_GPMC_A25_IN */},
1622 {0x1ec, 24, 0, /* CFG_GPMC_A26_IN */},
1623 {0x1f8, 0, 0, /* CFG_GPMC_A27_IN */},
1624 {0x360, 0, 0, /* CFG_GPMC_CS1_IN */},
1625 {0x194, 152, 0, /* CFG_GPMC_A19_OUT */},
1626 {0x1ac, 206, 0, /* CFG_GPMC_A20_OUT */},
1627 {0x1b8, 78, 0, /* CFG_GPMC_A21_OUT */},
1628 {0x1c4, 2, 0, /* CFG_GPMC_A22_OUT */},
1629 {0x1d0, 266, 0, /* CFG_GPMC_A23_OUT */},
1630 {0x1dc, 0, 0, /* CFG_GPMC_A24_OUT */},
1631 {0x1e8, 0, 0, /* CFG_GPMC_A25_OUT */},
1632 {0x1f4, 43, 0, /* CFG_GPMC_A26_OUT */},
1633 {0x200, 0, 0, /* CFG_GPMC_A27_OUT */},
1634 {0x368, 0, 0, /* CFG_GPMC_CS1_OUT */},
1635 {0x190, 0, 0, /* CFG_GPMC_A19_OEN */},
1636 {0x1a8, 0, 0, /* CFG_GPMC_A20_OEN */},
1637 {0x1b4, 0, 0, /* CFG_GPMC_A21_OEN */},
1638 {0x1c0, 0, 0, /* CFG_GPMC_A22_OEN */},
1639 {0x1d8, 0, 0, /* CFG_GPMC_A24_OEN */},
1640 {0x1e4, 0, 0, /* CFG_GPMC_A25_OEN */},
1641 {0x1f0, 0, 0, /* CFG_GPMC_A26_OEN */},
1642 {0x1fc, 0, 0, /* CFG_GPMC_A27_OEN */},
1643 {0x364, 0, 0, /* CFG_GPMC_CS1_OEN */},
1644};
1645
1646static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_dra72_conf[] = {
1647 {0x194, 150 , 95 /* CFG_GPMC_A19_OUT */},
1648 {0x1AC, 250 , 0 /* CFG_GPMC_A20_OUT */},
1649 {0x1B8, 125 , 0 /* CFG_GPMC_A21_OUT */},
1650 {0x1C4, 100 , 0 /* CFG_GPMC_A22_OUT */},
1651 {0x1D0, 870 , 415 /* CFG_GPMC_A23_OUT */},
1652 {0x1DC, 30 , 0 /* CFG_GPMC_A24_OUT */},
1653 {0x1E8, 200 , 0 /* CFG_GPMC_A25_OUT */},
1654 {0x1F4, 200 , 0 /* CFG_GPMC_A26_OUT */},
1655 {0x200, 0 , 0 /* CFG_GPMC_A27_OUT */},
1656 {0x368, 240 , 0 /* CFG_GPMC_CS1_OUT */},
1657 {0x190, 695 , 0 /* CFG_GPMC_A19_OEN */},
1658 {0x1A8, 924 , 0 /* CFG_GPMC_A20_OEN */},
1659 {0x1B4, 719 , 0 /* CFG_GPMC_A21_OEN */},
1660 {0x1C0, 824 , 0 /* CFG_GPMC_A22_OEN */},
1661 {0x1D8, 877 , 0 /* CFG_GPMC_A24_OEN */},
1662 {0x1E4, 446 , 0 /* CFG_GPMC_A25_OEN */},
1663 {0x1F0, 847 , 0 /* CFG_GPMC_A26_OEN */},
1664 {0x1FC, 586 , 0 /* CFG_GPMC_A27_OEN */},
1665 {0x364, 1039 , 0 /* CFG_GPMC_CS1_OEN */},
1666};
1667
1668static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_dra76_conf[] = {
1669 {0x190, 384 , 0 /* CFG_GPMC_A19_OEN */},
1670 {0x194, 0 , 174 /* CFG_GPMC_A19_OUT */},
1671 {0x1A8, 410 , 0 /* CFG_GPMC_A20_OEN */},
1672 {0x1AC, 85 , 0 /* CFG_GPMC_A20_OUT */},
1673 {0x1B4, 468 , 0 /* CFG_GPMC_A21_OEN */},
1674 {0x1B8, 139 , 0 /* CFG_GPMC_A21_OUT */},
1675 {0x1C0, 676 , 0 /* CFG_GPMC_A22_OEN */},
1676 {0x1C4, 69 , 0 /* CFG_GPMC_A22_OUT */},
1677 {0x1D0, 1062, 154 /* CFG_GPMC_A23_OUT */},
1678 {0x1D8, 640 , 0 /* CFG_GPMC_A24_OEN */},
1679 {0x1DC, 0 , 0 /* CFG_GPMC_A24_OUT */},
1680 {0x1E4, 356 , 0 /* CFG_GPMC_A25_OEN */},
1681 {0x1E8, 0 , 0 /* CFG_GPMC_A25_OUT */},
1682 {0x1F0, 579 , 0 /* CFG_GPMC_A26_OEN */},
1683 {0x1F4, 0 , 0 /* CFG_GPMC_A26_OUT */},
1684 {0x1FC, 435 , 0 /* CFG_GPMC_A27_OEN */},
1685 {0x200, 36 , 0 /* CFG_GPMC_A27_OUT */},
1686 {0x364, 759 , 0 /* CFG_GPMC_CS1_OEN */},
1687 {0x368, 72 , 0 /* CFG_GPMC_CS1_OUT */},
1688};
1689
1690#define dimof(t) (sizeof(t) / sizeof(t[0]))
1691static struct omap_hsmmc_pinctrl_state hsmmc1_default = {
1692 .padconf = hsmmc1_default_padconf,
1693 .npads = dimof(hsmmc1_default_padconf),
1694 .iodelay = NULL,
1695 .niodelays = 0,
1696};
1697
1698static struct omap_hsmmc_pinctrl_state hsmmc2_default_hs = {
1699 .padconf = mmc2_pins_default_hs,
1700 .npads = dimof(mmc2_pins_default_hs),
1701 .iodelay = NULL,
1702 .niodelays = 0,
1703};
1704
1705static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_1v8_rev11 = {
1706 .padconf = mmc2_pins_ddr_hs200_1_8v,
1707 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1708 .iodelay = mmc2_iodelay_ddr_1_8v_rev11_conf,
1709 .niodelays = dimof(mmc2_iodelay_ddr_1_8v_rev11_conf),
1710};
1711
1712static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_1v8_rev20 = {
1713 .padconf = mmc2_pins_ddr_hs200_1_8v,
1714 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1715 .iodelay = mmc2_iodelay_ddr_1_8v_rev20_conf,
1716 .niodelays = dimof(mmc2_iodelay_ddr_1_8v_rev20_conf),
1717};
1718
1719static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_rev11 = {
1720 .padconf = mmc2_pins_ddr_hs200_1_8v,
1721 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1722 .iodelay = mmc2_iodelay_hs200_1_8v_rev11_conf,
1723 .niodelays = dimof(mmc2_iodelay_hs200_1_8v_rev11_conf),
1724};
1725
1726static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_rev20 = {
1727 .padconf = mmc2_pins_ddr_hs200_1_8v,
1728 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1729 .iodelay = mmc2_iodelay_hs200_1_8v_rev20_conf,
1730 .niodelays = dimof(mmc2_iodelay_hs200_1_8v_rev20_conf),
1731};
1732
1733
1734static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_1v8_dra72 = {
1735 .padconf = mmc2_pins_ddr_hs200_1_8v,
1736 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1737 .iodelay = mmc2_iodelay_ddr_1_8v_dra72_conf,
1738 .niodelays = dimof(mmc2_iodelay_ddr_1_8v_dra72_conf),
1739};
1740
1741static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_dra72 = {
1742 .padconf = mmc2_pins_ddr_hs200_1_8v,
1743 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1744 .iodelay = mmc2_iodelay_hs200_1_8v_dra72_conf,
1745 .niodelays = dimof(mmc2_iodelay_hs200_1_8v_dra72_conf),
1746};
1747
1748static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_dra76 = {
1749 .padconf = mmc2_pins_ddr_hs200_1_8v,
1750 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1751 .iodelay = mmc2_iodelay_hs200_1_8v_dra76_conf,
1752 .niodelays = dimof(mmc2_iodelay_hs200_1_8v_dra76_conf),
1753};
1754#endif
1755
1756#endif /* _MUX_DATA_DRA7XX_H_ */ 1651#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/configs/dra7xx_evm_nodt_defconfig b/configs/dra7xx_evm_nodt_defconfig
index 64609f31b4..e09cedfafe 100644
--- a/configs/dra7xx_evm_nodt_defconfig
+++ b/configs/dra7xx_evm_nodt_defconfig
@@ -46,3 +46,4 @@ CONFIG_OF_BOARD_SETUP=y
46CONFIG_DRA7_DSPEVE_OPP_HIGH=y 46CONFIG_DRA7_DSPEVE_OPP_HIGH=y
47CONFIG_DRA7_IVA_OPP_HIGH=y 47CONFIG_DRA7_IVA_OPP_HIGH=y
48CONFIG_DRA7_GPU_OPP_PLUS=y 48CONFIG_DRA7_GPU_OPP_PLUS=y
49CONFIG_CONS_INDEX=3