aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorVenkateswara Rao Mandela2017-08-08 06:21:08 -0500
committerVenkateswara Rao Mandela2017-08-31 00:07:30 -0500
commit2e6a3711b84f2048d1735c95798b96f1170ceeba (patch)
tree6e0e7a11616151193183fa4bfa717f4a223783b7
parent52ea2ffe64d4f01e9bb60ec09ea4bd46e9c28fe8 (diff)
downloadu-boot-2e6a3711b84f2048d1735c95798b96f1170ceeba.tar.gz
u-boot-2e6a3711b84f2048d1735c95798b96f1170ceeba.tar.xz
u-boot-2e6a3711b84f2048d1735c95798b96f1170ceeba.zip
spl: dra7xx: early boot: code cleanup
- tie the size of the page table area set aside for each core to a macro. Size of page table is now PAGE_TABLE_SIZE instead of 32 KB hard coded earlier. This allows us to increase the page table size if we need more memory for L2 page tables. - modify the page table location for each core so that there is no overlap between the regions. The setup in u-boot now matches the kernel device tree setup. We only have to specify the base address of the page table region using the macro DRA7_PGTBL_BASE_ADDR. All page table locations are calculated by incrementing the base address appropriately. Change-Id: I8bad0780fcd90c679a144264c0dc5fd770ac5106 Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
-rw-r--r--board/ti/dra7xx/lateattach.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/board/ti/dra7xx/lateattach.c b/board/ti/dra7xx/lateattach.c
index a86e10dc80..0f1d1fd293 100644
--- a/board/ti/dra7xx/lateattach.c
+++ b/board/ti/dra7xx/lateattach.c
@@ -161,11 +161,6 @@
161#define DRA7_RPROC_CMA_SIZE_DSP1 0x04000000 161#define DRA7_RPROC_CMA_SIZE_DSP1 0x04000000
162#define DRA7_RPROC_CMA_SIZE_DSP2 0x00800000 162#define DRA7_RPROC_CMA_SIZE_DSP2 0x00800000
163 163
164#define DRA7_PGTBL_BASE_IPU1 0xbfc00000
165#define DRA7_PGTBL_BASE_IPU2 0xbfc08000
166#define DRA7_PGTBL_BASE_DSP1 0xbfc10000
167#define DRA7_PGTBL_BASE_DSP2 0xbfc18000
168
169/* 164/*
170 * The page table (32 KB) is placed at the end of the CMA reserved area. 165 * The page table (32 KB) is placed at the end of the CMA reserved area.
171 * It's possible that this location is needed by the firmware (in which 166 * It's possible that this location is needed by the firmware (in which
@@ -201,6 +196,15 @@
201 (1UL<<((nbits) % BITS_PER_LONG))-1 : ~0UL \ 196 (1UL<<((nbits) % BITS_PER_LONG))-1 : ~0UL \
202) 197)
203 198
199#define DRA7_PGTBL_BASE_ADDR 0xbfc00000
200#define DRA7_PGTBL_BASE_IPU1 (DRA7_PGTBL_BASE_ADDR)
201#define DRA7_PGTBL_BASE_IPU2 (DRA7_PGTBL_BASE_IPU1 + \
202 PAGE_TABLE_SIZE)
203#define DRA7_PGTBL_BASE_DSP1 (DRA7_PGTBL_BASE_IPU2 + \
204 PAGE_TABLE_SIZE)
205#define DRA7_PGTBL_BASE_DSP2 (DRA7_PGTBL_BASE_DSP1 + \
206 PAGE_TABLE_SIZE)
207
204/* 208/*
205 * Determine if a valid ELF image exists at the given memory location. 209 * Determine if a valid ELF image exists at the given memory location.
206 * First look at the ELF header magic field, then make sure that it is 210 * First look at the ELF header magic field, then make sure that it is