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authorVenkateswara Rao Mandela2017-08-29 10:53:06 -0500
committerVenkateswara Rao Mandela2017-08-31 00:07:20 -0500
commit52ea2ffe64d4f01e9bb60ec09ea4bd46e9c28fe8 (patch)
tree12bcb182a12cb1d8107dfac009efca4922768778
parentc8a0b5ceb8d530d0b0402b826799e81e8bcfccaa (diff)
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spl: dra7xx: early boot: handle watchdog timer for DSP2
Timer 13 has been added as watchdog timer for DSP2. Handle the same in MLO for early boot/late attach. Change-Id: I4c155fc51be0acec5b1ad754c46adcc93ee3752d Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
-rw-r--r--board/ti/dra7xx/lateattach.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/board/ti/dra7xx/lateattach.c b/board/ti/dra7xx/lateattach.c
index 0db28aef6b..a86e10dc80 100644
--- a/board/ti/dra7xx/lateattach.c
+++ b/board/ti/dra7xx/lateattach.c
@@ -93,6 +93,7 @@
93#define CM_IPU_TIMER8_CLKCTRL (IPU_CM_CORE_AON + 0x70) 93#define CM_IPU_TIMER8_CLKCTRL (IPU_CM_CORE_AON + 0x70)
94#define CM_L4PER2_L4_PER2_CLKCTRL (L4PER_CM_CORE + 0x0C) 94#define CM_L4PER2_L4_PER2_CLKCTRL (L4PER_CM_CORE + 0x0C)
95#define CM_L4PER3_L4_PER3_CLKCTRL (L4PER_CM_CORE + 0x14) 95#define CM_L4PER3_L4_PER3_CLKCTRL (L4PER_CM_CORE + 0x14)
96#define CM_L4PER3_TIMER13_CLKCTRL (L4PER_CM_CORE + 0xC8)
96#define CM_L4PER_I2C1_CLKCTRL (L4PER_CM_CORE + 0xA0) 97#define CM_L4PER_I2C1_CLKCTRL (L4PER_CM_CORE + 0xA0)
97#define CM_L4PER_I2C2_CLKCTRL (L4PER_CM_CORE + 0xA8) 98#define CM_L4PER_I2C2_CLKCTRL (L4PER_CM_CORE + 0xA8)
98#define CM_L4PER_I2C3_CLKCTRL (L4PER_CM_CORE + 0xB0) 99#define CM_L4PER_I2C3_CLKCTRL (L4PER_CM_CORE + 0xB0)
@@ -621,6 +622,7 @@ void enable_common_clocks(void)
621 __raw_writel(0x2, CM_DMA_CLKSTCTRL); 622 __raw_writel(0x2, CM_DMA_CLKSTCTRL);
622 __raw_writel(0x2, CM_COREAON_CLKSTCTRL); 623 __raw_writel(0x2, CM_COREAON_CLKSTCTRL);
623 __raw_writel(0x2, CM_L4PER_CLKSTCTRL); 624 __raw_writel(0x2, CM_L4PER_CLKSTCTRL);
625 __raw_writel(0x2, CM_L4PER3_CLKSTCTRL);
624 626
625 /* Some of the timers are on the IPU clock domain */ 627 /* Some of the timers are on the IPU clock domain */
626 __raw_writel(0x2, CM_IPU_CLKSTCTRL); 628 __raw_writel(0x2, CM_IPU_CLKSTCTRL);
@@ -894,6 +896,7 @@ u32 dsp_start_clocks(u32 core_id, struct rproc *cfg)
894 prm_base = DSP2_PRM_BASE; 896 prm_base = DSP2_PRM_BASE;
895 dsp_clkstctrl = CM_DSP2_CLKSTCTRL; 897 dsp_clkstctrl = CM_DSP2_CLKSTCTRL;
896 mmu_config = DSP2_SYS_MMU_CONFIG; 898 mmu_config = DSP2_SYS_MMU_CONFIG;
899 wdt_ctrl = CM_L4PER3_TIMER13_CLKCTRL;
897 } 900 }
898 901
899 /* Using TIMER_SYS_CLK as the clock source */ 902 /* Using TIMER_SYS_CLK as the clock source */