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authorVishal Mahaveer2017-03-16 11:36:37 -0500
committerVishal Mahaveer2017-03-24 10:15:04 -0500
commitac9b0c4edead4f846ea38cdca5c9905c4be900a0 (patch)
treef1bd36c614a12d32a3f5e87d9551bbe57f284110
parent999672f9eab156409fd826c07ac5ccaf650e26e6 (diff)
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dra71x: lcard: initial pmic and pad conf changes
Basic changes to get to u-boot console via nodt defconfig. padconf data is generated based on PCT board file shared by Robert. For first time boot, use USB peripheral boot and DFU configuration in MLO to get in to fastboot mode and flash emmc. Change-Id: I32871fa4b5ae8a2a76b18c21ba4efd7b2b2df5f9 Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
-rw-r--r--board/ti/dra7xx/evm.c55
-rw-r--r--board/ti/dra7xx/mux_data.h181
-rw-r--r--configs/dra7xx_evm_nodt_defconfig1
-rw-r--r--include/configs/dra7xx_evm.h2
4 files changed, 239 insertions, 0 deletions
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index f2e54276f6..c3a015f6b8 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -453,6 +453,50 @@ struct vcores_data dra718_volts = {
453 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 453 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
454}; 454};
455 455
456struct vcores_data dra718_lcard_volts = {
457 /*
458 * In the case of dra71x GPU MPU and CORE
459 * are all powered up by SMPS1
460 */
461 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
462 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
463 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
464 .mpu.addr = TPS65917_REG_ADDR_SMPS1,
465 .mpu.pmic = &tps659038,
466 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
467
468 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
469 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
470 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
471 .core.addr = TPS65917_REG_ADDR_SMPS1,
472 .core.pmic = &tps659038,
473
474 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
475 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
476 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
477 .gpu.addr = TPS65917_REG_ADDR_SMPS1,
478 .gpu.pmic = &tps659038,
479 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
480
481 /*
482 * The DSPEVE and IVA rails are grouped on DRA71x-evm
483 * and are powered by SMPS3
484 */
485 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
486 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
487 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
488 .eve.addr = TPS65917_REG_ADDR_SMPS3,
489 .eve.pmic = &tps659038,
490 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
491
492 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
493 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
494 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
495 .iva.addr = TPS65917_REG_ADDR_SMPS3,
496 .iva.pmic = &tps659038,
497 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
498};
499
456int get_voltrail_opp(int rail_offset) 500int get_voltrail_opp(int rail_offset)
457{ 501{
458 int opp; 502 int opp;
@@ -607,7 +651,11 @@ void vcores_update(void)
607 } else if (board_is_dra72x_evm()) { 651 } else if (board_is_dra72x_evm()) {
608 *omap_vcores = &dra722_volts; 652 *omap_vcores = &dra722_volts;
609 } else if (board_is_dra71x_evm()) { 653 } else if (board_is_dra71x_evm()) {
654#ifdef CONFIG_DRA71X_LCARD
655 *omap_vcores = &dra718_lcard_volts;
656#else
610 *omap_vcores = &dra718_volts; 657 *omap_vcores = &dra718_volts;
658#endif
611 } else { 659 } else {
612 /* If EEPROM is not populated */ 660 /* If EEPROM is not populated */
613 if (is_dra72x()) 661 if (is_dra72x())
@@ -637,10 +685,17 @@ void recalibrate_iodelay(void)
637 pads = dra72x_core_padconf_array_common; 685 pads = dra72x_core_padconf_array_common;
638 npads = ARRAY_SIZE(dra72x_core_padconf_array_common); 686 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
639 if (board_is_dra71x_evm()) { 687 if (board_is_dra71x_evm()) {
688#ifdef CONFIG_DRA71X_LCARD
689 pads = dra71x_lcard_core_padconf_array;
690 npads = ARRAY_SIZE(dra71x_lcard_core_padconf_array);
691 iodelay = dra71_lcard_iodelay_cfg_array;
692 niodelays = ARRAY_SIZE(dra71_lcard_iodelay_cfg_array);
693#else
640 pads = dra71x_core_padconf_array; 694 pads = dra71x_core_padconf_array;
641 npads = ARRAY_SIZE(dra71x_core_padconf_array); 695 npads = ARRAY_SIZE(dra71x_core_padconf_array);
642 iodelay = dra71_iodelay_cfg_array; 696 iodelay = dra71_iodelay_cfg_array;
643 niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array); 697 niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
698#endif
644 } else if (board_is_dra72x_revc_or_later()) { 699 } else if (board_is_dra72x_revc_or_later()) {
645 delta_pads = dra72x_rgmii_padconf_array_revc; 700 delta_pads = dra72x_rgmii_padconf_array_revc;
646 delta_npads = 701 delta_npads =
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 931d76d8eb..4c095dd6dd 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -470,14 +470,169 @@ const struct pad_conf_entry dra71x_core_padconf_array[] = {
470#endif 470#endif
471}; 471};
472 472
473const struct pad_conf_entry dra71x_lcard_core_padconf_array[] = {
474 {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
475 {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
476 {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
477 {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
478 {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
479 {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
480 {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
481 {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
482 {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
483 {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
484 {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
485 {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
486 {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
487 {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
488 {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
489 {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
490 {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
491 {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
492 {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
493 {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
494 {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
495 {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
496 {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
497 {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
498 {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
499 {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
500 {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
501 {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */
502 {GPMC_A12, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a12.gpio2_2 */
503 {GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.gpio2_3 */
504 {GPMC_A14, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a14.gpio2_4 */
505 {GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.gpio2_5 */
506 {GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.gpio2_6 */
507 {GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.gpio2_7 */
508 {GPMC_A18, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a18.gpio2_8 */
509 {GPMC_A19, (M1 | PIN_INPUT)}, /* gpmc_a19.mmc2_dat4 */
510 {GPMC_A20, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a20.mmc2_dat5 */
511 {GPMC_A21, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a21.mmc2_dat6 */
512 {GPMC_A22, (M1 | PIN_INPUT)}, /* gpmc_a22.mmc2_dat7 */
513 {GPMC_A23, (M1 | PIN_INPUT)}, /* gpmc_a23.mmc2_clk */
514 {GPMC_A24, (M1 | PIN_INPUT)}, /* gpmc_a24.mmc2_dat0 */
515 {GPMC_A25, (M1 | PIN_INPUT)}, /* gpmc_a25.mmc2_dat1 */
516 {GPMC_A26, (M1 | PIN_INPUT)}, /* gpmc_a26.mmc2_dat2 */
517 {GPMC_A27, (M1 | PIN_INPUT)}, /* gpmc_a27.mmc2_dat3 */
518 {GPMC_CS1, (M1 | PIN_INPUT)}, /* gpmc_cs1.mmc2_cmd */
519 {GPMC_CS0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs0.gpio2_19 */
520 {GPMC_CS2, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.gpio2_20 */
521 {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
522 {GPMC_CLK, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_clk.gpio2_22 */
523 {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */
524 {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */
525 {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */
526 {GPMC_BEN0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_ben0.gpio2_26 */
527 {GPMC_BEN1, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_ben1.gpio2_27 */
528 {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */
529 {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_clk0.vin2a_clk0 */
530 {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_hsync0.vin2a_hsync0 */
531 {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_vsync0.vin2a_vsync0 */
532 {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d0.vin2a_d0 */
533 {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d1.vin2a_d1 */
534 {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d2.vin2a_d2 */
535 {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d3.vin2a_d3 */
536 {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d4.vin2a_d4 */
537 {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.vin2a_d5 */
538 {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d6.vin2a_d6 */
539 {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d7.vin2a_d7 */
540 {VIN2A_D10, (M3 | PIN_INPUT_PULLUP)}, /* vin2a_d10.mdio_mclk */
541 {VIN2A_D11, (M3 | PIN_INPUT_PULLUP)}, /* vin2a_d11.mdio_d */
542 {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
543 {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
544 {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
545 {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
546 {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
547 {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
548 {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
549 {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
550 {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
551 {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
552 {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
553 {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
554 {MDIO_MCLK, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.gpio5_15 */
555 {MDIO_D, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.gpio5_16 */
556 {UART3_RXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_rxd.gpio5_18 */
557 {RGMII0_RXD3, (M14 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd3.gpio5_28 */
558 {RGMII0_RXD2, (M14 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd2.gpio5_29 */
559 {RGMII0_RXD1, (M14 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd1.gpio5_30 */
560 {RGMII0_RXD0, (M14 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd0.gpio5_31 */
561 {USB1_DRVVBUS, (M14 | PIN_OUTPUT)}, /* usb1_drvvbus.gpio6_12 */
562 {USB2_DRVVBUS, (M14 | PIN_OUTPUT)}, /* usb2_drvvbus.gpio6_13 */
563 {GPIO6_14, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_14.gpio6_14 */
564 {GPIO6_15, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_15.gpio6_15 */
565 {XREF_CLK3, (M14 | PIN_INPUT_PULLUP)}, /* xref_clk3.gpio6_20 */
566 {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE15)}, /* mcasp2_aclkx.mcasp2_aclkx */
567 {MCASP2_FSX, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE15)}, /* mcasp2_fsx.mcasp2_fsx */
568 {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp2_axr0.mcasp2_axr0 */
569 {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp2_axr1.mcasp2_axr1 */
570 {MCASP2_AXR2, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE8)}, /* mcasp2_axr2.mcasp3_axr2 */
571 {MCASP2_AXR3, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE8)}, /* mcasp2_axr3.mcasp3_axr3 */
572 {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp2_axr4.mcasp2_axr4 */
573 {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp2_axr5.mcasp2_axr5 */
574 {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* mcasp3_aclkx.mcasp3_aclkx */
575 {MCASP3_FSX, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE8)}, /* mcasp3_fsx.mcasp3_fsx */
576 {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE8)}, /* mcasp3_axr0.mcasp3_axr0 */
577 {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
578 {MCASP4_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.mcasp4_aclkx */
579 {MCASP4_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.mcasp4_fsx */
580 {MCASP4_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.mcasp4_axr0 */
581 {MCASP4_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr1.mcasp4_axr1 */
582 {MCASP5_ACLKX, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp5_aclkx.mcasp5_aclkx */
583 {MCASP5_FSX, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp5_fsx.mcasp5_fsx */
584 {MCASP5_AXR0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp5_axr0.mcasp5_axr0 */
585 {MCASP5_AXR1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* mcasp5_axr1.mcasp5_axr1 */
586 {MMC1_CLK, (M0 | PIN_INPUT)}, /* mmc1_clk.mmc1_clk */
587 {MMC1_CMD, (M0 | PIN_INPUT)}, /* mmc1_cmd.mmc1_cmd */
588 {MMC1_DAT0, (M0 | PIN_INPUT)}, /* mmc1_dat0.mmc1_dat0 */
589 {MMC1_DAT1, (M0 | PIN_INPUT)}, /* mmc1_dat1.mmc1_dat1 */
590 {MMC1_DAT2, (M0 | PIN_INPUT)}, /* mmc1_dat2.mmc1_dat2 */
591 {MMC1_DAT3, (M0 | PIN_INPUT)}, /* mmc1_dat3.mmc1_dat3 */
592 {GPIO6_10, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_10.ehrpwm2A */
593 {GPIO6_11, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_11.ehrpwm2B */
594 {MMC3_CLK, (M14 | PIN_INPUT_PULLUP)}, /* mmc3_clk.gpio6_29 */
595 {MMC3_CMD, (M14 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.gpio6_30 */
596 {MMC3_DAT0, (M2 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.uart5_rxd */
597 {MMC3_DAT1, (M2 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.uart5_txd */
598 {MMC3_DAT2, (M2 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.uart5_ctsn */
599 {MMC3_DAT3, (M2 | PIN_INPUT_PULLUP)}, /* mmc3_dat3.uart5_rtsn */
600 {MMC3_DAT4, (M10 | PIN_INPUT_PULLUP)}, /* mmc3_dat4.ehrpwm3A */
601 {MMC3_DAT5, (M14 | PIN_INPUT_PULLUP)}, /* mmc3_dat5.gpio1_23 */
602 {MMC3_DAT6, (M14 | PIN_INPUT_PULLUP)}, /* mmc3_dat6.gpio1_24 */
603 {MMC3_DAT7, (M14 | PIN_INPUT_PULLUP)}, /* mmc3_dat7.gpio1_25 */
604 {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
605 {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
606 {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
607 {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
608 {SPI1_CS1, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs1.spi1_cs1 */
609 {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
610 {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
611 {UART1_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.uart9_rxd */
612 {UART1_RTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.uart9_txd */
613 {UART2_RXD, (M14 | PIN_INPUT)}, /* uart2_rxd.gpio7_26 */
614 {UART2_TXD, (M14 | PIN_INPUT)}, /* uart2_txd.gpio7_27 */
615 {UART2_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.uart3_rxd */
616 {UART2_RTSN, (M1 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.uart3_txd */
617 {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
618 {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
619 {WAKEUP0, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_0 */
620 {WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */
621};
622
473const struct pad_conf_entry early_padconf[] = { 623const struct pad_conf_entry early_padconf[] = {
474#if (CONFIG_CONS_INDEX == 1) 624#if (CONFIG_CONS_INDEX == 1)
475 {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */ 625 {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
476 {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */ 626 {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */
477#elif (CONFIG_CONS_INDEX == 3) 627#elif (CONFIG_CONS_INDEX == 3)
628#ifdef CONFIG_DRA71X_LCARD
629 {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
630 {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
631#else
478 {UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */ 632 {UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */
479 {UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */ 633 {UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */
480#endif 634#endif
635#endif
481 {I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */ 636 {I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */
482 {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */ 637 {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */
483}; 638};
@@ -604,6 +759,32 @@ const struct iodelay_cfg_entry dra71_iodelay_cfg_array[] = {
604 {0x0B7C, 1943, 0}, /* CFG_VIN2A_HSYNC0_IN */ 759 {0x0B7C, 1943, 0}, /* CFG_VIN2A_HSYNC0_IN */
605 {0x0B88, 1612, 0}, /* CFG_VIN2A_VSYNC0_IN */ 760 {0x0B88, 1612, 0}, /* CFG_VIN2A_VSYNC0_IN */
606}; 761};
762
763const struct iodelay_cfg_entry dra71_lcard_iodelay_cfg_array[] = {
764 {0x0A38, 0, 0}, /* CFG_VIN2A_CLK0_IN */
765 {0x0A44, 1936, 0}, /* CFG_VIN2A_D0_IN */
766 {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
767 {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
768 {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
769 {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
770 {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
771 {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
772 {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
773 {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
774 {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
775 {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
776 {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
777 {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
778 {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
779 {0x0B04, 1736, 0}, /* CFG_VIN2A_D2_IN */
780 {0x0B10, 1943, 0}, /* CFG_VIN2A_D3_IN */
781 {0x0B1C, 1601, 0}, /* CFG_VIN2A_D4_IN */
782 {0x0B28, 2052, 0}, /* CFG_VIN2A_D5_IN */
783 {0x0B34, 1571, 0}, /* CFG_VIN2A_D6_IN */
784 {0x0B40, 1855, 0}, /* CFG_VIN2A_D7_IN */
785 {0x0B7C, 1943, 0}, /* CFG_VIN2A_HSYNC0_IN */
786 {0x0B88, 1612, 0}, /* CFG_VIN2A_VSYNC0_IN */
787};
607#endif 788#endif
608 789
609const struct pad_conf_entry dra74x_core_padconf_array[] = { 790const struct pad_conf_entry dra74x_core_padconf_array[] = {
diff --git a/configs/dra7xx_evm_nodt_defconfig b/configs/dra7xx_evm_nodt_defconfig
index 9c13366939..9701e30001 100644
--- a/configs/dra7xx_evm_nodt_defconfig
+++ b/configs/dra7xx_evm_nodt_defconfig
@@ -46,3 +46,4 @@ CONFIG_OF_BOARD_SETUP=y
46CONFIG_DRA7_DSPEVE_OPP_HIGH=y 46CONFIG_DRA7_DSPEVE_OPP_HIGH=y
47CONFIG_DRA7_IVA_OPP_HIGH=y 47CONFIG_DRA7_IVA_OPP_HIGH=y
48CONFIG_DRA7_GPU_OPP_HIGH=y 48CONFIG_DRA7_GPU_OPP_HIGH=y
49CONFIG_CONS_INDEX=3
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 820ef4a485..9faef73dbd 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -15,6 +15,8 @@
15#define CONFIG_DRA7XX 15#define CONFIG_DRA7XX
16#define CONFIG_BOARD_EARLY_INIT_F 16#define CONFIG_BOARD_EARLY_INIT_F
17 17
18#define CONFIG_DRA71X_LCARD
19
18#define CONFIG_IODELAY_RECALIBRATION 20#define CONFIG_IODELAY_RECALIBRATION
19#define CONFIG_SPL_SAVEENV 21#define CONFIG_SPL_SAVEENV
20 22