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authorVishal Mahaveer2017-08-28 12:21:34 -0500
committerVishal Mahaveer2017-08-28 12:21:34 -0500
commitaed1ae446f326044ee5982389d684f7bfb8f7b71 (patch)
tree02ff8b5b7e54ff221d71f4250646d7b31c48457b
parentc7a89832126796910d43409f8a3f2d2d455d4f6a (diff)
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Revert "arm: omap: enable high speed mode support in SPL for the eMMC on DRA7x and DRA72."
This reverts commit a5d52023de3c37231190454f833ea834a321c1ce.
-rw-r--r--board/ti/dra7xx/evm.c74
-rw-r--r--board/ti/dra7xx/mux_data.h261
2 files changed, 0 insertions, 335 deletions
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 25d5bd75c7..5c1a9569e7 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -917,80 +917,6 @@ void board_mmc_poweron_ldo(uint voltage)
917#endif 917#endif
918 918
919#ifdef CONFIG_OMAP_HSMMC 919#ifdef CONFIG_OMAP_HSMMC
920#if defined(CONFIG_IODELAY_RECALIBRATION) && \
921 (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC))
922
923struct pinctrl_desc {
924 const char *name;
925 struct omap_hsmmc_pinctrl_state *pinctrl;
926};
927
928static struct pinctrl_desc pinctrl_descs_hsmmc1[] = {
929 {"default", &hsmmc1_default},
930 {"hs", &hsmmc1_default},
931 {NULL}
932};
933
934static struct pinctrl_desc pinctrl_descs_hsmmc2_rev20[] = {
935 {"default", &hsmmc2_default_hs},
936 {"hs", &hsmmc2_default_hs},
937 {"ddr_1_8v", &hsmmc2_ddr_1v8_rev20},
938 {"hs200_1_8v", &hsmmc2_hs200_1v8_rev20},
939 {NULL}
940};
941
942static struct pinctrl_desc pinctrl_descs_hsmmc2_rev11[] = {
943 {"default", &hsmmc2_default_hs},
944 {"hs", &hsmmc2_default_hs},
945 {"ddr_1_8v", &hsmmc2_ddr_1v8_rev11},
946 {"hs200_1_8v", &hsmmc2_hs200_1v8_rev11},
947 {NULL}
948};
949
950static struct pinctrl_desc pinctrl_descs_hsmmc2_dra72x[] = {
951 {"default", &hsmmc2_default_hs},
952 {"hs", &hsmmc2_default_hs},
953 {"ddr_1_8v", &hsmmc2_ddr_1v8_dra72},
954 {"hs200_1_8v", &hsmmc2_hs200_1v8_dra72},
955 {NULL}
956};
957
958struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
959 (struct hsmmc *base, const char *mode)
960{
961 struct pinctrl_desc *p = NULL;
962
963 switch ((uint32_t)base) {
964 case OMAP_HSMMC1_BASE:
965 p = pinctrl_descs_hsmmc1;
966 break;
967 case OMAP_HSMMC2_BASE:
968 if ((omap_revision() == DRA752_ES1_0) ||
969 (omap_revision() == DRA752_ES1_1))
970 p = pinctrl_descs_hsmmc2_rev11;
971 else if (is_dra72x())
972 p = pinctrl_descs_hsmmc2_dra72x;
973 else if (is_dra7xx())
974 p = pinctrl_descs_hsmmc2_rev20;
975 break;
976 default:
977 break;
978 }
979
980 if (!p) {
981 printf("%s no pinctrl defined for MMC@%p\n", __func__,
982 base);
983 return NULL;
984 }
985 while (p->name) {
986 if (strcmp(mode, p->name) == 0)
987 return p->pinctrl;
988 p++;
989 }
990 return NULL;
991}
992#endif
993
994int platform_fixup_disable_uhs_mode(void) 920int platform_fixup_disable_uhs_mode(void)
995{ 921{
996 return omap_revision() == DRA752_ES1_1; 922 return omap_revision() == DRA752_ES1_1;
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 054e2c1429..0e1cb2d2dc 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -1556,265 +1556,4 @@ const struct iodelay_cfg_entry dra76x_es1_0_iodelay_cfg_array[] = {
1556}; 1556};
1557#endif 1557#endif
1558 1558
1559
1560#if defined(CONFIG_IODELAY_RECALIBRATION) && \
1561 (defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC)) && \
1562 defined(CONFIG_OMAP_HSMMC)
1563
1564static struct pad_conf_entry hsmmc1_default_padconf[] = {
1565 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP) /* mmc1_clk.clk */},
1566 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP) /* mmc1_cmd.cmd */},
1567 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat0.dat0 */},
1568 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat1.dat1 */},
1569 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat2.dat2 */},
1570 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat3.dat3 */},
1571};
1572
1573static struct pad_conf_entry mmc2_pins_default_hs[] = {
1574 {GPMC_A23, (M1 | PIN_INPUT_PULLUP) /* g pmc_a23.mmc2_clk */},
1575 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP) /* gpmc_cs1.mmc2_cmd */},
1576 {GPMC_A24, (M1 | PIN_INPUT_PULLUP) /* gpmc_a24.mmc2_dat0 */},
1577 {GPMC_A25, (M1 | PIN_INPUT_PULLUP) /* gpmc_a25.mmc2_dat1 */},
1578 {GPMC_A26, (M1 | PIN_INPUT_PULLUP) /* gpmc_a26.mmc2_dat2 */},
1579 {GPMC_A27, (M1 | PIN_INPUT_PULLUP) /* gpmc_a27.mmc2_dat3 */},
1580 {GPMC_A19, (M1 | PIN_INPUT_PULLUP) /* gpmc_a19.mmc2_dat4 */},
1581 {GPMC_A20, (M1 | PIN_INPUT_PULLUP) /* gpmc_a20.mmc2_dat5 */},
1582 {GPMC_A21, (M1 | PIN_INPUT_PULLUP) /* gpmc_a21.mmc2_dat6 */},
1583 {GPMC_A22, (M1 | PIN_INPUT_PULLUP) /* gpmc_a22.mmc2_dat7 */},
1584};
1585
1586static struct pad_conf_entry mmc2_pins_ddr_hs200_1_8v[] = {
1587 {GPMC_A23, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a23.mmc2_clk */},
1588 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_cs1.mmc2_cmd */},
1589 {GPMC_A24, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a24.mmc2_dat0 */},
1590 {GPMC_A25, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a25.mmc2_dat1 */},
1591 {GPMC_A26, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a26.mmc2_dat2 */},
1592 {GPMC_A27, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a27.mmc2_dat3 */},
1593 {GPMC_A19, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a19.mmc2_dat4 */},
1594 {GPMC_A20, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a20.mmc2_dat5 */},
1595 {GPMC_A21, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a21.mmc2_dat6 */},
1596 {GPMC_A22, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a22.mmc2_dat7 */},
1597};
1598
1599static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_rev11_conf[] = {
1600 {0x190, 621, 600 /* CFG_GPMC_A19_OEN */},
1601 {0x194, 300, 0 /* CFG_GPMC_A19_OUT */},
1602 {0x1a8, 739, 600 /* CFG_GPMC_A20_OEN */},
1603 {0x1ac, 240, 0 /* CFG_GPMC_A20_OUT */},
1604 {0x1b4, 812, 600 /* CFG_GPMC_A21_OEN */},
1605 {0x1b8, 240, 0 /* CFG_GPMC_A21_OUT */},
1606 {0x1c0, 954, 600 /* CFG_GPMC_A22_OEN */},
1607 {0x1c4, 60, 0 /* CFG_GPMC_A22_OUT */},
1608 {0x1d0, 1340, 420 /* CFG_GPMC_A23_OUT */},
1609 {0x1d8, 935, 600 /* CFG_GPMC_A24_OEN */},
1610 {0x1dc, 0, 0 /* CFG_GPMC_A24_OUT */},
1611 {0x1e4, 525, 600 /* CFG_GPMC_A25_OEN */},
1612 {0x1e8, 120, 0 /* CFG_GPMC_A25_OUT */},
1613 {0x1f0, 767, 600 /* CFG_GPMC_A26_OEN */},
1614 {0x1f4, 225, 0 /* CFG_GPMC_A26_OUT */},
1615 {0x1fc, 565, 600 /* CFG_GPMC_A27_OEN */},
1616 {0x200, 60, 0 /* CFG_GPMC_A27_OUT */},
1617 {0x364, 969, 600 /* CFG_GPMC_CS1_OEN */},
1618 {0x368, 180, 0 /* CFG_GPMC_CS1_OUT */},
1619};
1620
1621static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_rev20_conf[] = {
1622 {0x190, 274, 0 /* CFG_GPMC_A19_OEN */},
1623 {0x194, 162, 0 /* CFG_GPMC_A19_OUT */},
1624 {0x1a8, 401, 0 /* CFG_GPMC_A20_OEN */},
1625 {0x1ac, 73, 0 /* CFG_GPMC_A20_OUT */},
1626 {0x1b4, 465, 0 /* CFG_GPMC_A21_OEN */},
1627 {0x1b8, 115, 0 /* CFG_GPMC_A21_OUT */},
1628 {0x1c0, 633, 0 /* CFG_GPMC_A22_OEN */},
1629 {0x1c4, 47, 0 /* CFG_GPMC_A22_OUT */},
1630 {0x1d0, 935, 280 /* CFG_GPMC_A23_OUT */},
1631 {0x1d8, 621, 0 /* CFG_GPMC_A24_OEN */},
1632 {0x1dc, 0, 0 /* CFG_GPMC_A24_OUT */},
1633 {0x1e4, 183, 0 /* CFG_GPMC_A25_OEN */},
1634 {0x1e8, 0, 0 /* CFG_GPMC_A25_OUT */},
1635 {0x1f0, 467, 0 /* CFG_GPMC_A26_OEN */},
1636 {0x1f4, 0, 0 /* CFG_GPMC_A26_OUT */},
1637 {0x1fc, 262, 0 /* CFG_GPMC_A27_OEN */},
1638 {0x200, 46, 0 /* CFG_GPMC_A27_OUT */},
1639 {0x364, 684, 0 /* CFG_GPMC_CS1_OEN */},
1640 {0x368, 76, 0 /* CFG_GPMC_CS1_OUT */},
1641};
1642
1643static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_rev11_conf[] = {
1644 {0x18c, 0, 0 /* CFG_GPMC_A19_IN */},
1645 {0x1a4, 274, 240 /* CFG_GPMC_A20_IN */},
1646 {0x1b0, 0, 60 /* CFG_GPMC_A21_IN */},
1647 {0x1bc, 0, 60 /* CFG_GPMC_A22_IN */},
1648 {0x1c8, 514, 360 /* CFG_GPMC_A23_IN */},
1649 {0x1d4, 187, 120 /* CFG_GPMC_A24_IN */},
1650 {0x1e0, 0, 0 /* CFG_GPMC_A25_IN */},
1651 {0x1ec, 0, 60 /* CFG_GPMC_A26_IN */},
1652 {0x1f8, 121, 60 /* CFG_GPMC_A27_IN */},
1653 {0x360, 0, 0 /* CFG_GPMC_CS1_IN */},
1654 {0x190, 0, 0 /* CFG_GPMC_A19_OEN */},
1655 {0x194, 174, 0 /* CFG_GPMC_A19_OUT */},
1656 {0x1a8, 0, 0 /* CFG_GPMC_A20_OEN */},
1657 {0x1ac, 168, 0 /* CFG_GPMC_A20_OUT */},
1658 {0x1b4, 0, 0 /* CFG_GPMC_A21_OEN */},
1659 {0x1b8, 136, 0 /* CFG_GPMC_A21_OUT */},
1660 {0x1c0, 0, 0 /* CFG_GPMC_A22_OEN */},
1661 {0x1c4, 0, 0 /* CFG_GPMC_A22_OUT */},
1662 {0x1d0, 879, 0 /* CFG_GPMC_A23_OUT */},
1663 {0x1d8, 0, 0 /* CFG_GPMC_A24_OEN */},
1664 {0x1dc, 0, 0 /* CFG_GPMC_A24_OUT */},
1665 {0x1e4, 0, 0 /* CFG_GPMC_A25_OEN */},
1666 {0x1e8, 34, 0 /* CFG_GPMC_A25_OUT */},
1667 {0x1f0, 0, 0 /* CFG_GPMC_A26_OEN */},
1668 {0x1f4, 120, 0 /* CFG_GPMC_A26_OUT */},
1669 {0x1fc, 0, 0 /* CFG_GPMC_A27_OEN */},
1670 {0x200, 0, 0 /* CFG_GPMC_A27_OUT */},
1671 {0x364, 0, 0 /* CFG_GPMC_CS1_OEN */},
1672 {0x368, 11, 0 /* CFG_GPMC_CS1_OUT */},
1673};
1674
1675static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_rev20_conf[] = {
1676 {0x18c, 270, 0 /* CFG_GPMC_A19_IN */},
1677 {0x1a4, 0, 0 /* CFG_GPMC_A20_IN */},
1678 {0x1b0, 170, 0 /* CFG_GPMC_A21_IN */},
1679 {0x1bc, 758, 0 /* CFG_GPMC_A22_IN */},
1680 {0x1c8, 0, 0 /* CFG_GPMC_A23_IN */},
1681 {0x1d4, 81, 0 /* CFG_GPMC_A24_IN */},
1682 {0x1e0, 286, 0 /* CFG_GPMC_A25_IN */},
1683 {0x1ec, 0, 0 /* CFG_GPMC_A26_IN */},
1684 {0x1f8, 123, 0 /* CFG_GPMC_A27_IN */},
1685 {0x360, 346, 0 /* CFG_GPMC_CS1_IN */},
1686 {0x190, 0, 0 /* CFG_GPMC_A19_OEN */},
1687 {0x194, 55, 0 /* CFG_GPMC_A19_OUT */},
1688 {0x1a8, 0, 0 /* CFG_GPMC_A20_OEN */},
1689 {0x1ac, 422, 0 /* CFG_GPMC_A20_OUT */},
1690 {0x1b4, 642, 0 /* CFG_GPMC_A21_OEN */},
1691 {0x1b8, 0, 0 /* CFG_GPMC_A21_OUT */},
1692 {0x1c0, 0, 0 /* CFG_GPMC_A22_OEN */},
1693 {0x1c4, 128, 0 /* CFG_GPMC_A22_OUT */},
1694 {0x1d0, 0, 0 /* CFG_GPMC_A23_OUT */},
1695 {0x1d8, 0, 0 /* CFG_GPMC_A24_OEN */},
1696 {0x1dc, 395, 0 /* CFG_GPMC_A24_OUT */},
1697 {0x1e4, 0, 0 /* CFG_GPMC_A25_OEN */},
1698 {0x1e8, 0, 0 /* CFG_GPMC_A25_OUT */},
1699 {0x1f0, 623, 0 /* CFG_GPMC_A26_OEN */},
1700 {0x1f4, 0, 0 /* CFG_GPMC_A26_OUT */},
1701 {0x1fc, 54, 0 /* CFG_GPMC_A27_OEN */},
1702 {0x200, 0, 0 /* CFG_GPMC_A27_OUT */},
1703 {0x364, 0, 0 /* CFG_GPMC_CS1_OEN */},
1704 {0x368, 0, 0 /* CFG_GPMC_CS1_OUT */},
1705};
1706
1707static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_dra72_conf[] = {
1708 {0x18c, 0, 0, /* CFG_GPMC_A19_IN */},
1709 {0x1a4, 121, 0, /* CFG_GPMC_A20_IN */},
1710 {0x1b0, 0, 0, /* CFG_GPMC_A21_IN */},
1711 {0x1bc, 20, 0, /* CFG_GPMC_A22_IN */},
1712 {0x1c8, 108, 0, /* CFG_GPMC_A23_IN */},
1713 {0x1d4, 31, 0, /* CFG_GPMC_A24_IN */},
1714 {0x1e0, 0, 0, /* CFG_GPMC_A25_IN */},
1715 {0x1ec, 24, 0, /* CFG_GPMC_A26_IN */},
1716 {0x1f8, 0, 0, /* CFG_GPMC_A27_IN */},
1717 {0x360, 0, 0, /* CFG_GPMC_CS1_IN */},
1718 {0x194, 152, 0, /* CFG_GPMC_A19_OUT */},
1719 {0x1ac, 206, 0, /* CFG_GPMC_A20_OUT */},
1720 {0x1b8, 78, 0, /* CFG_GPMC_A21_OUT */},
1721 {0x1c4, 2, 0, /* CFG_GPMC_A22_OUT */},
1722 {0x1d0, 266, 0, /* CFG_GPMC_A23_OUT */},
1723 {0x1dc, 0, 0, /* CFG_GPMC_A24_OUT */},
1724 {0x1e8, 0, 0, /* CFG_GPMC_A25_OUT */},
1725 {0x1f4, 43, 0, /* CFG_GPMC_A26_OUT */},
1726 {0x200, 0, 0, /* CFG_GPMC_A27_OUT */},
1727 {0x368, 0, 0, /* CFG_GPMC_CS1_OUT */},
1728 {0x190, 0, 0, /* CFG_GPMC_A19_OEN */},
1729 {0x1a8, 0, 0, /* CFG_GPMC_A20_OEN */},
1730 {0x1b4, 0, 0, /* CFG_GPMC_A21_OEN */},
1731 {0x1c0, 0, 0, /* CFG_GPMC_A22_OEN */},
1732 {0x1d8, 0, 0, /* CFG_GPMC_A24_OEN */},
1733 {0x1e4, 0, 0, /* CFG_GPMC_A25_OEN */},
1734 {0x1f0, 0, 0, /* CFG_GPMC_A26_OEN */},
1735 {0x1fc, 0, 0, /* CFG_GPMC_A27_OEN */},
1736 {0x364, 0, 0, /* CFG_GPMC_CS1_OEN */},
1737};
1738
1739static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_dra72_conf[] = {
1740 {0x194, 150 , 95 /* CFG_GPMC_A19_OUT */},
1741 {0x1AC, 250 , 0 /* CFG_GPMC_A20_OUT */},
1742 {0x1B8, 125 , 0 /* CFG_GPMC_A21_OUT */},
1743 {0x1C4, 100 , 0 /* CFG_GPMC_A22_OUT */},
1744 {0x1D0, 870 , 415 /* CFG_GPMC_A23_OUT */},
1745 {0x1DC, 30 , 0 /* CFG_GPMC_A24_OUT */},
1746 {0x1E8, 200 , 0 /* CFG_GPMC_A25_OUT */},
1747 {0x1F4, 200 , 0 /* CFG_GPMC_A26_OUT */},
1748 {0x200, 0 , 0 /* CFG_GPMC_A27_OUT */},
1749 {0x368, 240 , 0 /* CFG_GPMC_CS1_OUT */},
1750 {0x190, 695 , 0 /* CFG_GPMC_A19_OEN */},
1751 {0x1A8, 924 , 0 /* CFG_GPMC_A20_OEN */},
1752 {0x1B4, 719 , 0 /* CFG_GPMC_A21_OEN */},
1753 {0x1C0, 824 , 0 /* CFG_GPMC_A22_OEN */},
1754 {0x1D8, 877 , 0 /* CFG_GPMC_A24_OEN */},
1755 {0x1E4, 446 , 0 /* CFG_GPMC_A25_OEN */},
1756 {0x1F0, 847 , 0 /* CFG_GPMC_A26_OEN */},
1757 {0x1FC, 586 , 0 /* CFG_GPMC_A27_OEN */},
1758 {0x364, 1039 , 0 /* CFG_GPMC_CS1_OEN */},
1759};
1760
1761#define dimof(t) (sizeof(t) / sizeof(t[0]))
1762static struct omap_hsmmc_pinctrl_state hsmmc1_default = {
1763 .padconf = hsmmc1_default_padconf,
1764 .npads = dimof(hsmmc1_default_padconf),
1765 .iodelay = NULL,
1766 .niodelays = 0,
1767};
1768
1769static struct omap_hsmmc_pinctrl_state hsmmc2_default_hs = {
1770 .padconf = mmc2_pins_default_hs,
1771 .npads = dimof(mmc2_pins_default_hs),
1772 .iodelay = NULL,
1773 .niodelays = 0,
1774};
1775
1776static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_1v8_rev11 = {
1777 .padconf = mmc2_pins_ddr_hs200_1_8v,
1778 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1779 .iodelay = mmc2_iodelay_ddr_1_8v_rev11_conf,
1780 .niodelays = dimof(mmc2_iodelay_ddr_1_8v_rev11_conf),
1781};
1782
1783static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_1v8_rev20 = {
1784 .padconf = mmc2_pins_ddr_hs200_1_8v,
1785 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1786 .iodelay = mmc2_iodelay_ddr_1_8v_rev20_conf,
1787 .niodelays = dimof(mmc2_iodelay_ddr_1_8v_rev20_conf),
1788};
1789
1790static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_rev11 = {
1791 .padconf = mmc2_pins_ddr_hs200_1_8v,
1792 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1793 .iodelay = mmc2_iodelay_hs200_1_8v_rev11_conf,
1794 .niodelays = dimof(mmc2_iodelay_hs200_1_8v_rev11_conf),
1795};
1796
1797static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_rev20 = {
1798 .padconf = mmc2_pins_ddr_hs200_1_8v,
1799 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1800 .iodelay = mmc2_iodelay_hs200_1_8v_rev20_conf,
1801 .niodelays = dimof(mmc2_iodelay_hs200_1_8v_rev20_conf),
1802};
1803
1804
1805static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_1v8_dra72 = {
1806 .padconf = mmc2_pins_ddr_hs200_1_8v,
1807 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1808 .iodelay = mmc2_iodelay_ddr_1_8v_dra72_conf,
1809 .niodelays = dimof(mmc2_iodelay_ddr_1_8v_dra72_conf),
1810};
1811
1812static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_dra72 = {
1813 .padconf = mmc2_pins_ddr_hs200_1_8v,
1814 .npads = dimof(mmc2_pins_ddr_hs200_1_8v),
1815 .iodelay = mmc2_iodelay_hs200_1_8v_dra72_conf,
1816 .niodelays = dimof(mmc2_iodelay_hs200_1_8v_dra72_conf),
1817};
1818#endif
1819
1820#endif /* _MUX_DATA_DRA7XX_H_ */ 1559#endif /* _MUX_DATA_DRA7XX_H_ */