aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorNikhil Devshatwar2017-08-22 03:12:01 -0500
committerDavid Huang2017-08-28 12:21:11 -0500
commitc8a0b5ceb8d530d0b0402b826799e81e8bcfccaa (patch)
treeb9044687c73e3ad34097e6d34044600192c9be82
parent4f1202c7773834bfd24876e7ac675deac8e089f1 (diff)
downloadu-boot-c8a0b5ceb8d530d0b0402b826799e81e8bcfccaa.tar.gz
u-boot-c8a0b5ceb8d530d0b0402b826799e81e8bcfccaa.tar.xz
u-boot-c8a0b5ceb8d530d0b0402b826799e81e8bcfccaa.zip
ti: dra71: Add J6entry vision pinmux
Add pinmux data for J6entry when used with vision board. This enables all vin1a, vin1b, vin2a, vin2b ports in 8bit mode and sets up the required iodelay configuration. Change-Id: I9c749e8274a9f7335fc0d713ec4b19cc1e13f3b7 Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
-rw-r--r--board/ti/dra7xx/mux_data.h57
1 files changed, 57 insertions, 0 deletions
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index a1929b0598..7e9dea677e 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -468,6 +468,63 @@ const struct pad_conf_entry dra71x_core_padconf_array[] = {
468 {MCASP4_ACLKX, (M4 | PIN_INPUT_PULLUP)},/* mcasp4_aclkx.i2c4_sda */ 468 {MCASP4_ACLKX, (M4 | PIN_INPUT_PULLUP)},/* mcasp4_aclkx.i2c4_sda */
469 {MCASP4_FSX, (M4 | PIN_INPUT_PULLUP)}, /* mcasp4_fsx.i2c4_scl */ 469 {MCASP4_FSX, (M4 | PIN_INPUT_PULLUP)}, /* mcasp4_fsx.i2c4_scl */
470#endif 470#endif
471#ifdef CONFIG_TARGET_DRA7XX_EVM_VISION
472 /* vin1a */
473 { GPMC_AD0, (M2 | PIN_INPUT | VIRTUAL_MODE12) }, /* gpmc_ad0.vin1a_d0 */
474 { GPMC_AD1, (M2 | PIN_INPUT | VIRTUAL_MODE12) }, /* gpmc_ad1.vin1a_d1 */
475 { GPMC_AD2, (M2 | PIN_INPUT | VIRTUAL_MODE12) }, /* gpmc_ad2.vin1a_d2 */
476 { GPMC_AD3, (M2 | PIN_INPUT | VIRTUAL_MODE12) }, /* gpmc_ad3.vin1a_d3 */
477 { GPMC_AD4, (M2 | PIN_INPUT | VIRTUAL_MODE12) }, /* gpmc_ad4.vin1a_d4 */
478 { GPMC_AD5, (M2 | PIN_INPUT | VIRTUAL_MODE12) }, /* gpmc_ad5.vin1a_d5 */
479 { GPMC_AD6, (M2 | PIN_INPUT | VIRTUAL_MODE12) }, /* gpmc_ad6.vin1a_d6 */
480 { GPMC_AD7, (M2 | PIN_INPUT | VIRTUAL_MODE12) }, /* gpmc_ad7.vin1a_d7 */
481 { GPMC_A8, (M2 | PIN_INPUT | VIRTUAL_MODE12) }, /* gpmc_a8.vin1a_hsync0 */
482 { GPMC_A9, (M2 | PIN_INPUT | VIRTUAL_MODE12) }, /* gpmc_a9.vin1a_vsync0 */
483 { GPMC_CS3, (M2 | PIN_INPUT | VIRTUAL_MODE11) }, /* gpmc_cs3.vin1a_clk0 */
484
485 /* vin1b */
486 { MDIO_MCLK, (M5 | PIN_INPUT | SLEWCONTROL | VIRTUAL_MODE10) }, /* mdio_mclk.vin1b_clk1 */
487 { MDIO_D, (M5 | PIN_INPUT | SLEWCONTROL | VIRTUAL_MODE10) }, /* mdio_d.vin1b_d0 */
488 { UART3_RXD, (M5 | PIN_INPUT | SLEWCONTROL | VIRTUAL_MODE10) }, /* uart3_rxd.vin1b_d1 */
489 { UART3_TXD, (M5 | PIN_INPUT | SLEWCONTROL | VIRTUAL_MODE10) }, /* uart3_txd.vin1b_d2 */
490 { RGMII0_TXC, (M5 | PIN_INPUT | VIRTUAL_MODE10) }, /* rgmii0_txc.vin1b_d3 */
491 { RGMII0_TXCTL, (M5 | PIN_INPUT | VIRTUAL_MODE10) }, /* rgmii0_txctl.vin1b_d4 */
492 { RGMII0_TXD2, (M5 | PIN_INPUT | VIRTUAL_MODE10) }, /* rgmii0_txd2.vin1b_hsync1 */
493 { RGMII0_TXD1, (M5 | PIN_INPUT | VIRTUAL_MODE10) }, /* rgmii0_txd1.vin1b_vsync1 */
494 { RGMII0_RXC, (M5 | PIN_INPUT | VIRTUAL_MODE10) }, /* rgmii0_rxc.vin1b_d5 */
495 { RGMII0_RXCTL, (M5 | PIN_INPUT | VIRTUAL_MODE10) }, /* rgmii0_rxctl.vin1b_d6 */
496 { RGMII0_RXD3, (M5 | PIN_INPUT | VIRTUAL_MODE10) }, /* rgmii0_rxd3.vin1b_d7 */
497
498 /* vin2a */
499 { VIN2A_CLK0, (M0 | PIN_INPUT | VIRTUAL_MODE9) }, /* vin2a_clk0.vin2a_clk0 */
500 { VIN2A_HSYNC0, (M0 | PIN_INPUT | VIRTUAL_MODE6) }, /* vin2a_hsync0.vin2a_hsync0 */
501 { VIN2A_VSYNC0, (M0 | PIN_INPUT | VIRTUAL_MODE9) }, /* vin2a_vsync0.vin2a_vsync0 */
502 { VIN2A_D0, (M0 | PIN_INPUT | VIRTUAL_MODE14) }, /* vin2a_d0.vin2a_d0 */
503 { VIN2A_D1, (M0 | PIN_INPUT | VIRTUAL_MODE14) }, /* vin2a_d1.vin2a_d1 */
504 { VIN2A_D2, (M0 | PIN_INPUT | VIRTUAL_MODE14) }, /* vin2a_d2.vin2a_d2 */
505 { VIN2A_D3, (M0 | PIN_INPUT | VIRTUAL_MODE8) }, /* vin2a_d3.vin2a_d3 */
506 { VIN2A_D4, (M0 | PIN_INPUT | VIRTUAL_MODE8) }, /* vin2a_d4.vin2a_d4 */
507 { VIN2A_D5, (M0 | PIN_INPUT | VIRTUAL_MODE8) }, /* vin2a_d5.vin2a_d5 */
508 { VIN2A_D6, (M0 | PIN_INPUT | VIRTUAL_MODE6) }, /* vin2a_d6.vin2a_d6 */
509 { VIN2A_D7, (M0 | PIN_INPUT | VIRTUAL_MODE6) }, /* vin2a_d7.vin2a_d7 */
510
511 /* vin2b */
512 { GPIO6_10, (M4 | PIN_INPUT | VIRTUAL_MODE8) }, /* gpio6_10.vin2b_hsync1 */
513 { GPIO6_11, (M4 | PIN_INPUT | VIRTUAL_MODE8) }, /* gpio6_11.vin2b_vsync1 */
514 { MMC3_CLK, (M4 | PIN_INPUT | VIRTUAL_MODE7) }, /* mmc3_clk.vin2b_d7 */
515 { MMC3_CMD, (M4 | PIN_INPUT | VIRTUAL_MODE7) }, /* mmc3_cmd.vin2b_d6 */
516 { MMC3_DAT0, (M4 | PIN_INPUT | VIRTUAL_MODE7) }, /* mmc3_dat0.vin2b_d5 */
517 { MMC3_DAT1, (M4 | PIN_INPUT | VIRTUAL_MODE7) }, /* mmc3_dat1.vin2b_d4 */
518 { MMC3_DAT2, (M4 | PIN_INPUT | VIRTUAL_MODE7) }, /* mmc3_dat2.vin2b_d3 */
519 { MMC3_DAT3, (M4 | PIN_INPUT | VIRTUAL_MODE7) }, /* mmc3_dat3.vin2b_d2 */
520 { MMC3_DAT4, (M4 | PIN_INPUT | VIRTUAL_MODE7) }, /* mmc3_dat4.vin2b_d1 */
521 { MMC3_DAT5, (M4 | PIN_INPUT | VIRTUAL_MODE7) }, /* mmc3_dat5.vin2b_d0 */
522 { MMC3_DAT7, (M4 | PIN_INPUT | VIRTUAL_MODE7) }, /* mmc3_dat7.vin2b_clk1 */
523
524 /* alternate mdio */
525 { VIN2A_D10, (M3 | PIN_INPUT_PULLUP) }, /* vin2a_d10.mdio_mclk */
526 { VIN2A_D11, (M3 | PIN_INPUT_PULLUP) }, /* vin2a_d11.mdio_d */
527#endif
471}; 528};
472 529
473const struct pad_conf_entry early_padconf[] = { 530const struct pad_conf_entry early_padconf[] = {