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authorVenkateswara Rao Mandela2016-06-30 18:51:39 -0500
committerPraneeth Bajjuri2016-06-30 18:51:44 -0500
commita217ac45f11b86b35cd8cce203a1c9e42b86c736 (patch)
tree60717922d512089206000ebff105e0dc0672deba
parent18770706457d77b7ebce944da7ad1758442639a5 (diff)
downloadu-boot-p-ti-u-boot-2014.07-earlylinux.tar.gz
u-boot-p-ti-u-boot-2014.07-earlylinux.tar.xz
u-boot-p-ti-u-boot-2014.07-earlylinux.zip
TMP: dra7:clock: configure mpu at opp_highp-ti-u-boot-2014.07-earlylinux
configuring uboot to run at OPP_HIGH instead of OPP_NOM by default. Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c16
-rw-r--r--arch/arm/include/asm/arch-omap5/clock.h1
2 files changed, 14 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index ed99319643..a0f5d8d71f 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -83,6 +83,16 @@ static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
83 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 83 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
84}; 84};
85 85
86static const struct dpll_params mpu_dpll_params_dra75_1_5ghz[NUM_SYS_CLKS] = {
87 {-1, -1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
88 {750, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
89 {-1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
90 {-1, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
91 {-1, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
92 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
93 {-1, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
94};
95
86static const struct dpll_params 96static const struct dpll_params
87 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { 97 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
88 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ 98 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
@@ -286,7 +296,7 @@ struct dplls omap5_dplls_es2 = {
286}; 296};
287 297
288struct dplls dra7xx_dplls = { 298struct dplls dra7xx_dplls = {
289 .mpu = mpu_dpll_params_1ghz, 299 .mpu = mpu_dpll_params_dra75_1_5ghz,
290 .core = core_dpll_params_2128mhz_dra7xx, 300 .core = core_dpll_params_2128mhz_dra7xx,
291 .per = per_dpll_params_768mhz_dra7xx, 301 .per = per_dpll_params_768mhz_dra7xx,
292 .abe = abe_dpll_params_sysclk2_361267khz, 302 .abe = abe_dpll_params_sysclk2_361267khz,
@@ -362,8 +372,8 @@ struct vcores_data omap5430_volts_es2 = {
362}; 372};
363 373
364struct vcores_data dra752_volts = { 374struct vcores_data dra752_volts = {
365 .mpu.value = VDD_MPU_DRA752, 375 .mpu.value = VDD_MPU_HIGH_DRA752,
366 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, 376 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_HIGH,
367 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 377 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
368 .mpu.addr = TPS659038_REG_ADDR_SMPS12, 378 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
369 .mpu.pmic = &tps659038, 379 .mpu.pmic = &tps659038,
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index dec83ffeee..2fa6b14b03 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -241,6 +241,7 @@
241 241
242/* TPS659038 Voltage settings in mv for OPP_NOMINAL */ 242/* TPS659038 Voltage settings in mv for OPP_NOMINAL */
243#define VDD_MPU_DRA752 1100 243#define VDD_MPU_DRA752 1100
244#define VDD_MPU_HIGH_DRA752 1250
244#define VDD_EVE_DRA752 1060 245#define VDD_EVE_DRA752 1060
245#define VDD_CORE_DRA752 1060 246#define VDD_CORE_DRA752 1060
246#define VDD_IVA_DRA752 1060 247#define VDD_IVA_DRA752 1060