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authorMatt Porter2013-06-07 11:32:44 -0500
committerTom Rini2013-06-07 12:14:07 -0500
commit187e3a2fa0a678b2a29e93d46976f4c47c317c34 (patch)
tree47f950bbf152db2c5c30c1f51ac1e10fd99c1765
parente2315adf674b60132f0c5c8fe6eac5d109b81688 (diff)
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omap5: add qspi support
Add QSPI definitions and clock configuration support. Signed-off-by: Matt Porter <mporter@ti.com> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c5
-rw-r--r--arch/arm/cpu/armv7/omap5/prcm-regs.c1
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h3
-rw-r--r--arch/arm/include/asm/arch-omap5/spl.h1
-rw-r--r--arch/arm/include/asm/omap_common.h1
5 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 9374c6a82e..3f46211b50 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -186,7 +186,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
186 186
187static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { 187static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
188 {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ 188 {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
189 {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ 189 {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
190 {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 190 {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
191 {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 191 {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
192 {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ 192 {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
@@ -423,6 +423,7 @@ void enable_basic_clocks(void)
423 (*prcm)->cm_wkup_wdtimer2_clkctrl, 423 (*prcm)->cm_wkup_wdtimer2_clkctrl,
424 (*prcm)->cm_l4per_uart3_clkctrl, 424 (*prcm)->cm_l4per_uart3_clkctrl,
425 (*prcm)->cm_l4per_i2c1_clkctrl, 425 (*prcm)->cm_l4per_i2c1_clkctrl,
426 (*prcm)->cm_l4per_qspi_clkctrl,
426 0 427 0
427 }; 428 };
428 429
@@ -451,6 +452,8 @@ void enable_basic_clocks(void)
451 clk_modules_explicit_en_essential, 452 clk_modules_explicit_en_essential,
452 1); 453 1);
453 454
455 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
456
454 /* Enable SCRM OPT clocks for PER and CORE dpll */ 457 /* Enable SCRM OPT clocks for PER and CORE dpll */
455 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, 458 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
456 OPTFCLKEN_SCRM_PER_MASK); 459 OPTFCLKEN_SCRM_PER_MASK);
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 331117c35c..debc56bb64 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -926,6 +926,7 @@ struct prcm_regs const dra7xx_prcm = {
926 .cm_l4per_gpio8_clkctrl = 0x4a009818, 926 .cm_l4per_gpio8_clkctrl = 0x4a009818,
927 .cm_l4per_mmcsd3_clkctrl = 0x4a009820, 927 .cm_l4per_mmcsd3_clkctrl = 0x4a009820,
928 .cm_l4per_mmcsd4_clkctrl = 0x4a009828, 928 .cm_l4per_mmcsd4_clkctrl = 0x4a009828,
929 .cm_l4per_qspi_clkctrl = 0x4a009838,
929 .cm_l4per_uart1_clkctrl = 0x4a009840, 930 .cm_l4per_uart1_clkctrl = 0x4a009840,
930 .cm_l4per_uart2_clkctrl = 0x4a009848, 931 .cm_l4per_uart2_clkctrl = 0x4a009848,
931 .cm_l4per_uart3_clkctrl = 0x4a009850, 932 .cm_l4per_uart3_clkctrl = 0x4a009850,
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index e7d79fc3c4..d2c493011d 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -67,6 +67,9 @@
67/* GPMC */ 67/* GPMC */
68#define OMAP54XX_GPMC_BASE 0x50000000 68#define OMAP54XX_GPMC_BASE 0x50000000
69 69
70/* QSPI */
71#define QSPI_BASE 0x4B300000
72
70/* 73/*
71 * Hardware Register Details 74 * Hardware Register Details
72 */ 75 */
diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h
index d4d353c80b..8905cb8999 100644
--- a/arch/arm/include/asm/arch-omap5/spl.h
+++ b/arch/arm/include/asm/arch-omap5/spl.h
@@ -31,6 +31,7 @@
31#define BOOT_DEVICE_MMC1 5 31#define BOOT_DEVICE_MMC1 5
32#define BOOT_DEVICE_MMC2 6 32#define BOOT_DEVICE_MMC2 6
33#define BOOT_DEVICE_MMC2_2 7 33#define BOOT_DEVICE_MMC2_2 7
34#define BOOT_DEVICE_SPI 10
34 35
35#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 36#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
36#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 37#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index fa2835846a..c8d4619d7c 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -279,6 +279,7 @@ struct prcm_regs {
279 u32 cm_l4per_mmcsd4_clkctrl; 279 u32 cm_l4per_mmcsd4_clkctrl;
280 u32 cm_l4per_msprohg_clkctrl; 280 u32 cm_l4per_msprohg_clkctrl;
281 u32 cm_l4per_slimbus2_clkctrl; 281 u32 cm_l4per_slimbus2_clkctrl;
282 u32 cm_l4per_qspi_clkctrl;
282 u32 cm_l4per_uart1_clkctrl; 283 u32 cm_l4per_uart1_clkctrl;
283 u32 cm_l4per_uart2_clkctrl; 284 u32 cm_l4per_uart2_clkctrl;
284 u32 cm_l4per_uart3_clkctrl; 285 u32 cm_l4per_uart3_clkctrl;