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authorSricharan R2013-05-28 00:02:23 -0500
committerLokesh Vutla2013-05-29 04:34:54 -0500
commit21d6e010f1de9453a8b6f31eaa1f46cab8490f30 (patch)
treebae5424ccda9ad3d2ea7f446e8a5deeae56a6354
parentb9ae28adb93127d89dba7b63526146cd18907e82 (diff)
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ARM: DRA7xx: Correct the SYS_CLK to 20MHZ
The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. Signed-off-by: Sricharan R <r.sricharan@ti.com>
-rw-r--r--include/configs/dra7xx_evm.h4
-rw-r--r--include/configs/omap5_common.h1
-rw-r--r--include/configs/omap5_uevm.h3
3 files changed, 7 insertions, 1 deletions
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index b142049a6c..b0b0bdacf6 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -38,4 +38,8 @@
38#define CONFIG_CONS_INDEX 1 38#define CONFIG_CONS_INDEX 1
39#define CONFIG_SYS_NS16550_COM1 UART1_BASE 39#define CONFIG_SYS_NS16550_COM1 UART1_BASE
40#define CONFIG_BAUDRATE 115200 40#define CONFIG_BAUDRATE 115200
41
42/* Clock Defines */
43#define V_OSCK 20000000 /* Clock output from T2 */
44
41#endif /* __CONFIG_DRA7XX_EVM_H */ 45#endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
index d57c0daed1..9fef21c7d9 100644
--- a/include/configs/omap5_common.h
+++ b/include/configs/omap5_common.h
@@ -46,7 +46,6 @@
46#define CONFIG_DISPLAY_BOARDINFO 46#define CONFIG_DISPLAY_BOARDINFO
47 47
48/* Clock Defines */ 48/* Clock Defines */
49#define V_OSCK 19200000 /* Clock output from T2 */
50#define V_SCLK V_OSCK 49#define V_SCLK V_OSCK
51 50
52#define CONFIG_MISC_INIT_R 51#define CONFIG_MISC_INIT_R
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index ba81e30bb1..4f2d4253c7 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -58,5 +58,8 @@
58 58
59#define CONFIG_SYS_PROMPT "OMAP5430 EVM # " 59#define CONFIG_SYS_PROMPT "OMAP5430 EVM # "
60 60
61/* Clock Defines */
62#define V_OSCK 19200000 /* Clock output from T2 */
63
61#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 64#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
62#endif /* __CONFIG_OMAP5_EVM_H */ 65#endif /* __CONFIG_OMAP5_EVM_H */