aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorEnric Balletbo i Serra2013-04-04 17:27:58 -0500
committerTom Rini2013-05-10 07:25:55 -0500
commit5f5c1d13d3b3bb97fae1ed8c3c9e35b4af0f19e5 (patch)
treed7d47d40d311658b98aff40e4a50ec60da6cd59d
parentcc175e6353b088c6c79d8d51b56d76972aab5c65 (diff)
downloadu-boot-5f5c1d13d3b3bb97fae1ed8c3c9e35b4af0f19e5.tar.gz
u-boot-5f5c1d13d3b3bb97fae1ed8c3c9e35b4af0f19e5.tar.xz
u-boot-5f5c1d13d3b3bb97fae1ed8c3c9e35b4af0f19e5.zip
ARM: Add support for IGEP COM AQUILA/CYGNUS
The IGEP COM AQUILA and CYGNUS are industrial processors modules with following highlights: o AM3352/AM3354 Texas Instruments processor o Cortex-A8 ARM CPU o 3.3 volts Inputs / Outputs use industrial o 256 MB DDR3 SDRAM / 128 Megabytes FLASH o MicroSD card reader on-board o Ethernet controller on-board o JTAG debug connector available o Designed for industrial range purposes Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
-rw-r--r--MAINTAINERS1
-rw-r--r--board/isee/igep0033/Makefile46
-rw-r--r--board/isee/igep0033/board.c232
-rw-r--r--board/isee/igep0033/board.h27
-rw-r--r--board/isee/igep0033/mux.c89
-rw-r--r--boards.cfg1
-rw-r--r--include/configs/igep0033.h284
7 files changed, 680 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 643a5acc41..a46803cd5f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -607,6 +607,7 @@ Enric Balletbo i Serra <eballetbo@iseebcn.com>
607 igep0020 ARM ARMV7 (OMAP3xx SoC) 607 igep0020 ARM ARMV7 (OMAP3xx SoC)
608 igep0030 ARM ARMV7 (OMAP3xx SoC) 608 igep0030 ARM ARMV7 (OMAP3xx SoC)
609 igep0032 ARM ARMV7 (OMAP3xx SoC) 609 igep0032 ARM ARMV7 (OMAP3xx SoC)
610 igep0033 ARM ARMV7 (AM33xx Soc)
610 611
611Eric Benard <eric@eukrea.com> 612Eric Benard <eric@eukrea.com>
612 613
diff --git a/board/isee/igep0033/Makefile b/board/isee/igep0033/Makefile
new file mode 100644
index 0000000000..54a4b75252
--- /dev/null
+++ b/board/isee/igep0033/Makefile
@@ -0,0 +1,46 @@
1#
2# Makefile
3#
4# Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
5#
6# This program is free software; you can redistribute it and/or
7# modify it under the terms of the GNU General Public License as
8# published by the Free Software Foundation; either version 2 of
9# the License, or (at your option) any later version.
10#
11# This program is distributed "as is" WITHOUT ANY WARRANTY of any
12# kind, whether express or implied; without even the implied warranty
13# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14# GNU General Public License for more details.
15#
16
17include $(TOPDIR)/config.mk
18
19LIB = $(obj)lib$(BOARD).o
20
21ifdef CONFIG_SPL_BUILD
22COBJS := mux.o
23endif
24
25COBJS += board.o
26SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
27OBJS := $(addprefix $(obj),$(COBJS))
28SOBJS := $(addprefix $(obj),$(SOBJS))
29
30$(LIB): $(obj).depend $(OBJS) $(SOBJS)
31 $(call cmd_link_o_target, $(OBJS) $(SOBJS))
32
33clean:
34 rm -f $(SOBJS) $(OBJS)
35
36distclean: clean
37 rm -f $(LIB) core *.bak $(obj).depend
38
39#########################################################################
40
41# defines $(obj).depend target
42include $(SRCTREE)/rules.mk
43
44sinclude $(obj).depend
45
46#########################################################################
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
new file mode 100644
index 0000000000..d315516fea
--- /dev/null
+++ b/board/isee/igep0033/board.c
@@ -0,0 +1,232 @@
1/*
2 * Board functions for IGEP COM AQUILA/CYGNUS based boards
3 *
4 * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <common.h>
18#include <errno.h>
19#include <spl.h>
20#include <asm/arch/cpu.h>
21#include <asm/arch/hardware.h>
22#include <asm/arch/omap.h>
23#include <asm/arch/ddr_defs.h>
24#include <asm/arch/clock.h>
25#include <asm/arch/gpio.h>
26#include <asm/arch/mmc_host_def.h>
27#include <asm/arch/sys_proto.h>
28#include <asm/io.h>
29#include <asm/emif.h>
30#include <asm/gpio.h>
31#include <i2c.h>
32#include <miiphy.h>
33#include <cpsw.h>
34#include "board.h"
35
36DECLARE_GLOBAL_DATA_PTR;
37
38static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
39#ifdef CONFIG_SPL_BUILD
40static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
41#endif
42
43/* MII mode defines */
44#define RMII_MODE_ENABLE 0x4D
45
46static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
47
48/* UART Defines */
49#ifdef CONFIG_SPL_BUILD
50#define UART_RESET (0x1 << 1)
51#define UART_CLK_RUNNING_MASK 0x1
52#define UART_SMART_IDLE_EN (0x1 << 0x3)
53
54static void rtc32k_enable(void)
55{
56 struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
57
58 /*
59 * Unlock the RTC's registers. For more details please see the
60 * RTC_SS section of the TRM. In order to unlock we need to
61 * write these specific values (keys) in this order.
62 */
63 writel(0x83e70b13, &rtc->kick0r);
64 writel(0x95a4f1e0, &rtc->kick1r);
65
66 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
67 writel((1 << 3) | (1 << 6), &rtc->osc);
68}
69
70static const struct ddr_data ddr3_data = {
71 .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
72 .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
73 .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
74 .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
75 .datadldiff0 = PHY_DLL_LOCK_DIFF,
76};
77
78static const struct cmd_control ddr3_cmd_ctrl_data = {
79 .cmd0csratio = K4B2G1646EBIH9_RATIO,
80 .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
81 .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
82
83 .cmd1csratio = K4B2G1646EBIH9_RATIO,
84 .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
85 .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
86
87 .cmd2csratio = K4B2G1646EBIH9_RATIO,
88 .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
89 .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
90};
91
92static struct emif_regs ddr3_emif_reg_data = {
93 .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
94 .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
95 .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
96 .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
97 .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
98 .zq_config = K4B2G1646EBIH9_ZQ_CFG,
99 .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
100};
101#endif
102
103/*
104 * Early system init of muxing and clocks.
105 */
106void s_init(void)
107{
108 /* WDT1 is already running when the bootloader gets control
109 * Disable it to avoid "random" resets
110 */
111 writel(0xAAAA, &wdtimer->wdtwspr);
112 while (readl(&wdtimer->wdtwwps) != 0x0)
113 ;
114 writel(0x5555, &wdtimer->wdtwspr);
115 while (readl(&wdtimer->wdtwwps) != 0x0)
116 ;
117
118#ifdef CONFIG_SPL_BUILD
119 /* Setup the PLLs and the clocks for the peripherals */
120 pll_init();
121
122 /* Enable RTC32K clock */
123 rtc32k_enable();
124
125 /* UART softreset */
126 u32 regval;
127
128 enable_uart0_pin_mux();
129
130 regval = readl(&uart_base->uartsyscfg);
131 regval |= UART_RESET;
132 writel(regval, &uart_base->uartsyscfg);
133 while ((readl(&uart_base->uartsyssts) &
134 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
135 ;
136
137 /* Disable smart idle */
138 regval = readl(&uart_base->uartsyscfg);
139 regval |= UART_SMART_IDLE_EN;
140 writel(regval, &uart_base->uartsyscfg);
141
142 gd = &gdata;
143
144 preloader_console_init();
145
146 /* Configure board pin mux */
147 enable_board_pin_mux();
148
149 config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
150 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
151#endif
152}
153
154/*
155 * Basic board specific setup. Pinmux has been handled already.
156 */
157int board_init(void)
158{
159 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
160
161 gpmc_init();
162
163 return 0;
164}
165
166#if defined(CONFIG_DRIVER_TI_CPSW)
167static void cpsw_control(int enabled)
168{
169 /* VTP can be added here */
170
171 return;
172}
173
174static struct cpsw_slave_data cpsw_slaves[] = {
175 {
176 .slave_reg_ofs = 0x208,
177 .sliver_reg_ofs = 0xd80,
178 .phy_id = 0,
179 .phy_if = PHY_INTERFACE_MODE_RMII,
180 },
181};
182
183static struct cpsw_platform_data cpsw_data = {
184 .mdio_base = CPSW_MDIO_BASE,
185 .cpsw_base = CPSW_BASE,
186 .mdio_div = 0xff,
187 .channels = 8,
188 .cpdma_reg_ofs = 0x800,
189 .slaves = 1,
190 .slave_data = cpsw_slaves,
191 .ale_reg_ofs = 0xd00,
192 .ale_entries = 1024,
193 .host_port_reg_ofs = 0x108,
194 .hw_stats_reg_ofs = 0x900,
195 .mac_control = (1 << 5),
196 .control = cpsw_control,
197 .host_port_num = 0,
198 .version = CPSW_CTRL_VERSION_2,
199};
200
201int board_eth_init(bd_t *bis)
202{
203 int rv, ret = 0;
204 uint8_t mac_addr[6];
205 uint32_t mac_hi, mac_lo;
206
207 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
208 /* try reading mac address from efuse */
209 mac_lo = readl(&cdev->macid0l);
210 mac_hi = readl(&cdev->macid0h);
211 mac_addr[0] = mac_hi & 0xFF;
212 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
213 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
214 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
215 mac_addr[4] = mac_lo & 0xFF;
216 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
217 if (is_valid_ether_addr(mac_addr))
218 eth_setenv_enetaddr("ethaddr", mac_addr);
219 }
220
221 writel(RMII_MODE_ENABLE, &cdev->miisel);
222
223 rv = cpsw_register(&cpsw_data);
224 if (rv < 0)
225 printf("Error %d registering CPSW switch\n", rv);
226 else
227 ret += rv;
228
229 return ret;
230}
231#endif
232
diff --git a/board/isee/igep0033/board.h b/board/isee/igep0033/board.h
new file mode 100644
index 0000000000..37988e0fd3
--- /dev/null
+++ b/board/isee/igep0033/board.h
@@ -0,0 +1,27 @@
1/*
2 * IGEP COM AQUILA/CYGNUS boards information header
3 *
4 * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef _BOARD_H_
18#define _BOARD_H_
19
20/*
21 * We must be able to enable uart0, for initial output. We then have a
22 * main pinmux function that can be overridden to enable all other pinmux that
23 * is required on the board.
24 */
25void enable_uart0_pin_mux(void);
26void enable_board_pin_mux(void);
27#endif
diff --git a/board/isee/igep0033/mux.c b/board/isee/igep0033/mux.c
new file mode 100644
index 0000000000..16f4addf3d
--- /dev/null
+++ b/board/isee/igep0033/mux.c
@@ -0,0 +1,89 @@
1/*
2 * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <common.h>
15#include <asm/arch/sys_proto.h>
16#include <asm/arch/hardware.h>
17#include <asm/arch/mux.h>
18#include <asm/io.h>
19#include <i2c.h>
20#include "board.h"
21
22static struct module_pin_mux uart0_pin_mux[] = {
23 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
24 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
25 {-1},
26};
27
28static struct module_pin_mux mmc0_pin_mux[] = {
29 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
30 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
31 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
32 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
33 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
34 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
35 {OFFSET(mcasp0_aclkx), (MODE(4) | RXACTIVE)}, /* MMC0_CD */
36 {-1},
37};
38
39static struct module_pin_mux nand_pin_mux[] = {
40 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
41 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
42 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
43 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
44 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
45 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
46 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
47 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
48 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
49 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
50 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
51 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
52 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
53 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
54 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
55 {-1},
56};
57
58static struct module_pin_mux rmii1_pin_mux[] = {
59 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
60 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
61 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
62 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
63 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
64 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
65 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
66 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REF_CLK */
67 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
68 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
69 {-1},
70};
71
72void enable_uart0_pin_mux(void)
73{
74 configure_module_pin_mux(uart0_pin_mux);
75}
76
77/*
78 * Do board-specific muxes.
79 */
80void enable_board_pin_mux(void)
81{
82 /* NAND Flash */
83 configure_module_pin_mux(nand_pin_mux);
84 /* SD Card */
85 configure_module_pin_mux(mmc0_pin_mux);
86 /* Ethernet pinmux. */
87 configure_module_pin_mux(rmii1_pin_mux);
88}
89
diff --git a/boards.cfg b/boards.cfg
index 31483d623f..06ba9795fa 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -277,6 +277,7 @@ igep0020_nand arm armv7 igep00x0 isee
277igep0030 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND 277igep0030 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND
278igep0030_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND 278igep0030_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND
279igep0032 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND 279igep0032 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND
280igep0033 arm armv7 igep0033 isee am33xx
280am3517_evm arm armv7 am3517evm logicpd omap3 281am3517_evm arm armv7 am3517evm logicpd omap3
281mt_ventoux arm armv7 mt_ventoux teejet omap3 282mt_ventoux arm armv7 mt_ventoux teejet omap3
282omap3_zoom1 arm armv7 zoom1 logicpd omap3 283omap3_zoom1 arm armv7 zoom1 logicpd omap3
diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h
new file mode 100644
index 0000000000..50eafdf60b
--- /dev/null
+++ b/include/configs/igep0033.h
@@ -0,0 +1,284 @@
1/*
2 * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __CONFIG_IGEP0033_H
15#define __CONFIG_IGEP0033_H
16
17#define CONFIG_AM33XX
18
19#include <asm/arch/omap.h>
20
21/* Mach type */
22#define MACH_TYPE_IGEP0033 4521 /* Until the next sync */
23#define CONFIG_MACH_TYPE MACH_TYPE_IGEP0033
24
25/* Clock defines */
26#define V_OSCK 24000000 /* Clock output from T2 */
27#define V_SCLK (V_OSCK)
28
29/* DMA defines */
30#define CONFIG_DMA_COHERENT
31#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
32
33#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
34#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
35#define CONFIG_SYS_LONGHELP /* undef to save memory */
36#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
37#define CONFIG_SYS_PROMPT "U-Boot# "
38#define CONFIG_SYS_NO_FLASH
39
40/* Display cpuinfo */
41#define CONFIG_DISPLAY_CPUINFO
42
43/* Commands to include */
44#include <config_cmd_default.h>
45
46#define CONFIG_CMD_ASKENV
47#define CONFIG_CMD_BOOTZ
48#define CONFIG_CMD_DHCP
49#define CONFIG_CMD_ECHO
50#define CONFIG_CMD_EXT4
51#define CONFIG_CMD_FAT
52#define CONFIG_CMD_FS_GENERIC
53#define CONFIG_CMD_MMC
54#define CONFIG_CMD_MTDPARTS
55#define CONFIG_CMD_NAND
56#define CONFIG_CMD_NET
57#define CONFIG_CMD_PING
58#define CONFIG_CMD_UBI
59#define CONFIG_CMD_UBIFS
60
61/*
62 * Because the issues explained in doc/README.memory-test, the "mtest command
63 * is considered deprecated. It should not be enabled in most normal ports of
64 * U-Boot.
65 */
66#undef CONFIG_CMD_MEMTEST
67
68#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */
69#define CONFIG_ENV_VARS_UBOOT_CONFIG
70#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
71#define CONFIG_EXTRA_ENV_SETTINGS \
72 "loadaddr=0x80200000\0" \
73 "rdaddr=0x81000000\0" \
74 "bootfile=/boot/uImage\0" \
75 "console=ttyO0,115200n8\0" \
76 "optargs=\0" \
77 "mmcdev=0\0" \
78 "mmcroot=/dev/mmcblk0p2 rw\0" \
79 "mmcrootfstype=ext4 rootwait\0" \
80 "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
81 "ramrootfstype=ext2\0" \
82 "mmcargs=setenv bootargs console=${console} " \
83 "${optargs} " \
84 "root=${mmcroot} " \
85 "rootfstype=${mmcrootfstype}\0" \
86 "bootenv=uEnv.txt\0" \
87 "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
88 "importbootenv=echo Importing environment from mmc ...; " \
89 "env import -t $loadaddr $filesize\0" \
90 "ramargs=setenv bootargs console=${console} " \
91 "${optargs} " \
92 "root=${ramroot} " \
93 "rootfstype=${ramrootfstype}\0" \
94 "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
95 "loaduimagefat=load mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
96 "loaduimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
97 "mmcboot=echo Booting from mmc ...; " \
98 "run mmcargs; " \
99 "bootm ${loadaddr}\0" \
100 "ramboot=echo Booting from ramdisk ...; " \
101 "run ramargs; " \
102 "bootm ${loadaddr}\0" \
103
104#define CONFIG_BOOTCOMMAND \
105 "mmc dev ${mmcdev}; if mmc rescan; then " \
106 "echo SD/MMC found on device ${mmcdev};" \
107 "if run loadbootenv; then " \
108 "echo Loaded environment from ${bootenv};" \
109 "run importbootenv;" \
110 "fi;" \
111 "if test -n $uenvcmd; then " \
112 "echo Running uenvcmd ...;" \
113 "run uenvcmd;" \
114 "fi;" \
115 "if run loaduimage; then " \
116 "run mmcboot;" \
117 "fi;" \
118 "fi;" \
119
120/* Max number of command args */
121#define CONFIG_SYS_MAXARGS 16
122
123/* Console I/O Buffer Size */
124#define CONFIG_SYS_CBSIZE 512
125
126/* Print Buffer Size */
127#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
128 + sizeof(CONFIG_SYS_PROMPT) + 16)
129
130/* Boot Argument Buffer Size */
131#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
132#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
133#define CONFIG_SYS_HZ 1000 /* 1ms clock */
134
135/* Physical Memory Map */
136#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
137#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
138#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
139
140#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
141#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
142 GENERATED_GBL_DATA_SIZE)
143/* Platform/Board specific defs */
144#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
145#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
146#define CONFIG_SYS_HZ 1000
147
148/* NS16550 Configuration */
149#define CONFIG_SYS_NS16550
150#define CONFIG_SYS_NS16550_SERIAL
151#define CONFIG_SYS_NS16550_REG_SIZE (-4)
152#define CONFIG_SYS_NS16550_CLK (48000000)
153#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
154
155#define CONFIG_SERIAL_MULTI
156#define CONFIG_CONS_INDEX 1
157#define CONFIG_BAUDRATE 115200
158
159#define CONFIG_ENV_OVERWRITE 1
160#define CONFIG_SYS_CONSOLE_INFO_QUIET
161
162/* MMC support */
163#define CONFIG_MMC
164#define CONFIG_GENERIC_MMC
165#define CONFIG_OMAP_HSMMC
166#define CONFIG_DOS_PARTITION
167
168/* GPIO support */
169#define CONFIG_OMAP_GPIO
170
171/* Ethernet support */
172#define CONFIG_DRIVER_TI_CPSW
173#define CONFIG_MII
174#define CONFIG_BOOTP_DEFAULT
175#define CONFIG_BOOTP_DNS
176#define CONFIG_BOOTP_DNS2
177#define CONFIG_BOOTP_SEND_HOSTNAME
178#define CONFIG_BOOTP_GATEWAY
179#define CONFIG_BOOTP_SUBNETMASK
180#define CONFIG_NET_RETRY_COUNT 10
181#define CONFIG_NET_MULTI
182#define CONFIG_PHYLIB
183#define CONFIG_PHY_ADDR 0
184#define CONFIG_PHY_SMSC
185
186/* NAND support */
187#define CONFIG_NAND
188#define CONFIG_NAND_OMAP_GPMC
189#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
190#define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */
191#define CONFIG_SYS_MAX_NAND_DEVICE 1
192#define CONFIG_SYS_NAND_ONFI_DETECTION 1
193#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
194#define CONFIG_ENV_IS_IN_NAND
195#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
196
197#define CONFIG_MTD_PARTITIONS
198#define CONFIG_MTD_DEVICE
199#define CONFIG_RBTREE
200#define CONFIG_LZO
201
202#define MTDIDS_DEFAULT "nand0=nand"
203#define MTDPARTS_DEFAULT "mtdparts=nand:512k(SPL),"\
204 "1m(U-Boot),128k(U-Boot Env),"\
205 "5m(Kernel),-(File System)"
206
207/* Unsupported features */
208#undef CONFIG_USE_IRQ
209
210/* Defines for SPL */
211#define CONFIG_SPL
212#define CONFIG_SPL_FRAMEWORK
213#define CONFIG_SPL_TEXT_BASE 0x402F0400
214#define CONFIG_SPL_MAX_SIZE (101 * 1024)
215#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
216
217#define CONFIG_SPL_BSS_START_ADDR 0x80000000
218#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
219
220#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
221#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
222#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
223#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
224#define CONFIG_SPL_MMC_SUPPORT
225#define CONFIG_SPL_FAT_SUPPORT
226#define CONFIG_SPL_LIBCOMMON_SUPPORT
227#define CONFIG_SPL_LIBDISK_SUPPORT
228#define CONFIG_SPL_LIBGENERIC_SUPPORT
229#define CONFIG_SPL_SERIAL_SUPPORT
230#define CONFIG_SPL_GPIO_SUPPORT
231#define CONFIG_SPL_YMODEM_SUPPORT
232#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
233
234#define CONFIG_SPL_BOARD_INIT
235#define CONFIG_SPL_NAND_AM33XX_BCH
236#define CONFIG_SPL_NAND_SUPPORT
237#define CONFIG_SPL_NAND_BASE
238#define CONFIG_SPL_NAND_DRIVERS
239#define CONFIG_SPL_NAND_ECC
240#define CONFIG_SYS_NAND_5_ADDR_CYCLE
241#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
242 CONFIG_SYS_NAND_PAGE_SIZE)
243#define CONFIG_SYS_NAND_PAGE_SIZE 2048
244#define CONFIG_SYS_NAND_OOBSIZE 64
245#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
246#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
247#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
248 10, 11, 12, 13, 14, 15, 16, 17, \
249 18, 19, 20, 21, 22, 23, 24, 25, \
250 26, 27, 28, 29, 30, 31, 32, 33, \
251 34, 35, 36, 37, 38, 39, 40, 41, \
252 42, 43, 44, 45, 46, 47, 48, 49, \
253 50, 51, 52, 53, 54, 55, 56, 57, }
254
255#define CONFIG_SYS_NAND_ECCSIZE 512
256#define CONFIG_SYS_NAND_ECCBYTES 14
257
258#define CONFIG_SYS_NAND_ECCSTEPS 4
259#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
260 CONFIG_SYS_NAND_ECCSTEPS)
261
262#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
263
264#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
265
266/*
267 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
268 * 64 bytes before this address should be set aside for u-boot.img's
269 * header. That is 0x800FFFC0--0x80100000 should not be used for any
270 * other needs.
271 */
272#define CONFIG_SYS_TEXT_BASE 0x80800000
273#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
274#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
275
276/*
277 * Since SPL did pll and ddr initialization for us,
278 * we don't need to do it twice.
279 */
280#ifndef CONFIG_SPL_BUILD
281#define CONFIG_SKIP_LOWLEVEL_INIT
282#endif
283
284#endif /* ! __CONFIG_IGEP0033_H */