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authorMatt Porter2013-06-07 11:32:45 -0500
committerTom Rini2013-06-07 12:14:08 -0500
commit6536c7fed62f56dcb5392ae783059d1edbfe916b (patch)
tree75469ab4e6fa4665b889640b8a2eca4572df8890
parent187e3a2fa0a678b2a29e93d46976f4c47c317c34 (diff)
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spi: add TI QSPI driver
Adds a SPI master driver for the TI QSPI peripheral. Signed-off-by: Matt Porter <mporter@ti.com> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/ti_qspi.c262
2 files changed, 263 insertions, 0 deletions
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609effe..f51033dd17 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -54,6 +54,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
54COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o 54COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
55COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o 55COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
56COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o 56COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
57COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
57COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o 58COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
58 59
59COBJS := $(COBJS-y) 60COBJS := $(COBJS-y)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
new file mode 100644
index 0000000000..1973b85a44
--- /dev/null
+++ b/drivers/spi/ti_qspi.c
@@ -0,0 +1,262 @@
1/*
2 * TI QSPI driver
3 *
4 * Copyright (C) 2013, Texas Instruments, Incorporated
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <common.h>
18#include <asm/io.h>
19#include <asm/arch/omap.h>
20#include <malloc.h>
21#include <spi.h>
22
23struct qspi_slave {
24 struct spi_slave slave;
25 unsigned int mode;
26 u32 cmd;
27 u32 dc;
28};
29
30#define to_qspi_slave(s) container_of(s, struct qspi_slave, slave)
31
32struct qspi_regs {
33 u32 pid;
34 u32 pad0[3];
35 u32 sysconfig;
36 u32 pad1[3];
37 u32 intr_status_raw_set;
38 u32 intr_status_enabled_clear;
39 u32 intr_enable_set;
40 u32 intr_enable_clear;
41 u32 intc_eoi;
42 u32 pad2[3];
43 u32 spi_clock_cntrl;
44 u32 spi_dc;
45 u32 spi_cmd;
46 u32 spi_status;
47 u32 spi_data;
48 u32 spi_setup0;
49 u32 spi_setup1;
50 u32 spi_setup2;
51 u32 spi_setup3;
52 u32 spi_switch;
53 u32 spi_data1;
54 u32 spi_data2;
55 u32 spi_data3;
56};
57
58static struct qspi_regs *qspi = (struct qspi_regs *)QSPI_BASE;
59
60#define QSPI_TIMEOUT 2000000
61
62#define QSPI_FCLK 192000000
63
64/* Clock Control */
65#define QSPI_CLK_EN (1 << 31)
66#define QSPI_CLK_DIV_MAX 0xffff
67
68/* Command */
69#define QSPI_EN_CS(n) (n << 28)
70#define QSPI_WLEN(n) ((n-1) << 19)
71#define QSPI_3_PIN (1 << 18)
72#define QSPI_RD_SNGL (1 << 16)
73#define QSPI_WR_SNGL (2 << 16)
74#define QSPI_INVAL (4 << 16)
75
76/* Device Control */
77#define QSPI_DD(m, n) (m << (3 + n*8))
78#define QSPI_CKPHA(n) (1 << (2 + n*8))
79#define QSPI_CSPOL(n) (1 << (1 + n*8))
80#define QSPI_CKPOL(n) (1 << (n*8))
81
82/* Status */
83#define QSPI_WC (1 << 1)
84#define QSPI_BUSY (1 << 0)
85#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
86#define QSPI_XFER_DONE QSPI_WC
87
88int spi_cs_is_valid(unsigned int bus, unsigned int cs)
89{
90 return 1;
91}
92
93void spi_cs_activate(struct spi_slave *slave)
94{
95 /* CS handled in xfer */
96 return;
97}
98
99void spi_cs_deactivate(struct spi_slave *slave)
100{
101 /* CS handled in xfer */
102 return;
103}
104
105void spi_init(void)
106{
107 /* nothing to do */
108}
109
110void spi_set_speed(struct spi_slave *slave, uint hz)
111{
112 uint clk_div;
113
114 if (!hz)
115 clk_div = 0;
116 else
117 clk_div = (QSPI_FCLK / hz) - 1;
118
119 debug("%s: hz: %d, clock divider %d\n", __func__, hz, clk_div);
120
121 /* disable SCLK */
122 writel(readl(&qspi->spi_clock_cntrl) & ~QSPI_CLK_EN, &qspi->spi_clock_cntrl);
123
124 if (clk_div < 0) {
125 debug("%s: clock divider < 0, using /1 divider\n", __func__);
126 clk_div = 0;
127 }
128
129 if (clk_div > QSPI_CLK_DIV_MAX) {
130 debug("%s: clock divider >%d , using /%d divider\n",
131 __func__, QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
132 clk_div = QSPI_CLK_DIV_MAX;
133 }
134
135 /* enable SCLK */
136 writel(QSPI_CLK_EN | clk_div, &qspi->spi_clock_cntrl);
137 debug("%s: spi_clock_cntrl %08x\n", __func__, readl(&qspi->spi_clock_cntrl));
138}
139
140struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
141 unsigned int max_hz, unsigned int mode)
142{
143 struct qspi_slave *qslave;
144
145 qslave = spi_alloc_slave(struct qspi_slave, bus, cs);
146 if (!qslave)
147 return NULL;
148
149 spi_set_speed(&qslave->slave, max_hz);
150 qslave->mode = mode;
151 debug("%s: bus:%i cs:%i mode:%i\n", __func__, bus, cs, mode);
152
153 return &qslave->slave;
154}
155
156void spi_free_slave(struct spi_slave *slave)
157{
158 struct qspi_slave *qslave = to_qspi_slave(slave);
159 free(qslave);
160}
161
162int spi_claim_bus(struct spi_slave *slave)
163{
164 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
165
166 writel(0, &qspi->spi_dc);
167 writel(0, &qspi->spi_cmd);
168 writel(0, &qspi->spi_data);
169
170 return 0;
171}
172
173void spi_release_bus(struct spi_slave *slave)
174{
175 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
176
177 writel(0, &qspi->spi_dc);
178 writel(0, &qspi->spi_cmd);
179 writel(0, &qspi->spi_data);
180}
181
182int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
183 void *din, unsigned long flags)
184{
185 struct qspi_slave *qslave = to_qspi_slave(slave);
186 uint words = bitlen >> 3; /* fixed 8-bit word length */
187 const uchar *txp = dout;
188 uchar *rxp = din;
189 uint status;
190 int timeout;
191
192 debug("%s: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", __func__,
193 slave->bus, slave->cs, bitlen, words, flags);
194 if (bitlen == 0)
195 return -1;
196
197 if (bitlen % 8) {
198 flags |= SPI_XFER_END;
199 return -1;
200 }
201
202 /* setup command reg */
203 qslave->cmd = 0;
204 qslave->cmd |= QSPI_WLEN(8);
205 qslave->cmd |= QSPI_EN_CS(slave->cs);
206 if (flags & SPI_3WIRE)
207 qslave->cmd |= QSPI_3_PIN;
208 qslave->cmd |= 0xfff;
209
210 /* setup device control reg */
211 qslave->dc = 0;
212 if (qslave->mode & SPI_CPHA)
213 qslave->dc |= QSPI_CKPHA(slave->cs);
214 if (qslave->mode & SPI_CPOL)
215 qslave->dc |= QSPI_CKPOL(slave->cs);
216 if (qslave->mode & SPI_CS_HIGH)
217 qslave->dc |= QSPI_CSPOL(slave->cs);
218
219 while (words--) {
220 if (txp) {
221 debug("tx cmd %08x dc %08x data %02x\n",
222 qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp);
223 writel(*txp++, &qspi->spi_data);
224 writel(qslave->dc, &qspi->spi_dc);
225 writel(qslave->cmd | QSPI_WR_SNGL, &qspi->spi_cmd);
226 status = readl(&qspi->spi_status);
227 timeout = QSPI_TIMEOUT;
228 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
229 if (--timeout < 0) {
230 printf("QSPI tx timed out\n");
231 return -1;
232 }
233 status = readl(&qspi->spi_status);
234 }
235 debug("tx done, status %08x\n", status);
236 }
237 if (rxp) {
238 debug("rx cmd %08x dc %08x\n",
239 qslave->cmd | QSPI_RD_SNGL, qslave->dc);
240 writel(qslave->dc, &qspi->spi_dc);
241 writel(qslave->cmd | QSPI_RD_SNGL, &qspi->spi_cmd);
242 status = readl(&qspi->spi_status);
243 timeout = QSPI_TIMEOUT;
244 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
245 if (--timeout < 0) {
246 printf("QSPI rx timed out\n");
247 return -1;
248 }
249 status = readl(&qspi->spi_status);
250 }
251 *rxp++ = readl(&qspi->spi_data);
252 debug("rx done, status %08x, read %02x\n",
253 status, *(rxp-1));
254 }
255 }
256
257 /* Terminate frame */
258 if (flags & SPI_XFER_END)
259 writel(qslave->cmd | QSPI_INVAL, &qspi->spi_cmd);
260
261 return 0;
262}