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authorMatt Porter2013-06-07 11:32:46 -0500
committerTom Rini2013-06-07 12:14:09 -0500
commit69ccf4a520f18f22075aad031d82b4b9e32e2d12 (patch)
tree484a0d1e1a38340c53d2c8aecc2d818389371a43
parent6536c7fed62f56dcb5392ae783059d1edbfe916b (diff)
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dra7xx_evm: add SPL API, QSPI, and serial flash support
Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode. Signed-off-by: Matt Porter <mporter@ti.com> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
-rw-r--r--board/ti/dra7xx/mux_data.h312
-rw-r--r--include/configs/dra7xx_evm.h22
2 files changed, 310 insertions, 24 deletions
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 338a241ce7..b26a9be075 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -29,29 +29,293 @@
29#include <asm/arch/mux_dra7xx.h> 29#include <asm/arch/mux_dra7xx.h>
30 30
31const struct pad_conf_entry core_padconf_array_essential[] = { 31const struct pad_conf_entry core_padconf_array_essential[] = {
32 {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ 32 {MMC1_CLK, (IEN | PTU | PDIS | M0)},
33 {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ 33 {MMC1_CMD, (IEN | PTU | PDIS | M0)},
34 {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ 34 {MMC1_DAT0, (IEN | PTU | PDIS | M0)},
35 {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ 35 {MMC1_DAT1, (IEN | PTU | PDIS | M0)},
36 {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ 36 {MMC1_DAT2, (IEN | PTU | PDIS | M0)},
37 {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ 37 {MMC1_DAT3, (IEN | PTU | PDIS | M0)},
38 {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ 38 {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)},
39 {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ 39 {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)},
40 {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ 40 {GPMC_A19, (IEN | PTU | M1)}, /* mmc2_dat4 */
41 {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ 41 {GPMC_A20, (IEN | PTU | M1)}, /* mmc2_dat5 */
42 {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ 42 {GPMC_A21, (IEN | PTU | M1)}, /* mmc2_dat6 */
43 {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ 43 {GPMC_A22, (IEN | PTU | M1)}, /* mmc2_dat7 */
44 {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ 44 {GPMC_A23, (IEN | PTU | M1)}, /* mmc2_clk */
45 {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ 45 {GPMC_A24, (IEN | PTU | M1)}, /* mmc2_dat0 */
46 {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ 46 {GPMC_A25, (IEN | PTU | M1)}, /* mmc2_dat1 */
47 {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ 47 {GPMC_A26, (IEN | PTU | M1)}, /* mmc2_dat2 */
48 {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ 48 {GPMC_A27, (IEN | PTU | M1)}, /* mmc2_dat3 */
49 {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ 49 {GPMC_CS1, (IEN | PTU | M1)}, /* mmm2_cmd */
50 {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */ 50 {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)},
51 {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */ 51 {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)},
52 {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */ 52 {UART1_CTSN, (IEN | PTU | PDIS | M3)},
53 {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */ 53 {UART1_RTSN, (IEN | PTU | PDIS | M3)},
54 {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ 54 {I2C1_SDA, (IEN | PTU | PDIS | M0)},
55 {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ 55 {I2C1_SCL, (IEN | PTU | PDIS | M0)},
56 {GPMC_A13, (PTU | IEN | M1)}, /* QSPI1_RTCLK */
57 {GPMC_A18, (PTU | IEN | M1)}, /* QSPI1_SCLK */
58 {GPMC_A17, (PTU | IEN | M1)}, /* QSPI1_D[0] */
59 {GPMC_A16, (PTU | IEN | M1)}, /* QSPI1_D[1] */
60 {GPMC_A15, (PTU | IEN | M1)}, /* QSPI1_D[2] */
61 {GPMC_A14, (PTU | IEN | M1)}, /* QSPI1_D[3] */
62 {GPMC_CS2, (PTU | M1)}, /* QSPI1_CS[0] */
63 {GPMC_CS3, (PTU | M1)}, /* QSPI1_CS[1] */
64 {GPMC_A3, (PTU | M1)}, /* QSPI1_CS[2] */
65 {GPMC_A4, (PTU | M1)}, /* QSPI1_CS[3] */
66};
67
68const struct pad_conf_entry core_padconf_array_non_essential[] = {
69 {GPMC_AD0, (IEN | PTD | PEN | M3)},
70 {GPMC_AD1, (IEN | PTD | PEN | M3)},
71 {GPMC_AD2, (IEN | PTD | PEN | M3)},
72 {GPMC_AD3, (IEN | PTD | PEN | M3)},
73 {GPMC_AD4, (IEN | PTD | PEN | M3)},
74 {GPMC_AD5, (IEN | PTD | PEN | M3)},
75 {GPMC_AD6, (IEN | PTD | PEN | M3)},
76 {GPMC_AD7, (IEN | PTD | PEN | M3)},
77 {GPMC_AD8, (IEN | PTD | PEN | M3)},
78 {GPMC_AD9, (IEN | PTD | PEN | M3)},
79 {GPMC_AD10, (IEN | PTD | PEN | M3)},
80 {GPMC_AD11, (IEN | PTD | PEN | M3)},
81 {GPMC_AD12, (IEN | PTD | PEN | M3)},
82 {GPMC_AD13, (IEN | PTD | PEN | M3)},
83 {GPMC_AD14, (IEN | PTD | PEN | M3)},
84 {GPMC_AD15, (IEN | PTD | PEN | M3)},
85 {GPMC_A0, (IEN | PDIS | M3)},
86 {GPMC_A1, (IEN | PDIS | M3)},
87 {GPMC_A2, (IEN | PDIS | M3)},
88 {GPMC_A3, (IEN | PDIS | M3)},
89 {GPMC_A4, (IEN | PDIS | M3)},
90 {GPMC_A5, (IEN | PDIS | M3)},
91 {GPMC_A6, (IEN | PDIS | M3)},
92 {GPMC_A7, (IEN | PDIS | M3)},
93 {GPMC_A8, (IEN | PDIS | M3)},
94 {GPMC_A9, (IEN | PDIS | M3)},
95 {GPMC_A10, (IEN | PDIS | M3)},
96 {GPMC_A11, (IEN | PDIS | M3)},
97 {GPMC_A12, (IEN | PDIS | M15)},
98 {GPMC_A13, (IEN | PDIS | M1)},
99 {GPMC_A14, (IEN | PDIS | M1)},
100 {GPMC_A15, (IEN | PDIS | M1)},
101 {GPMC_A16, (IEN | PDIS | M1)},
102 {GPMC_A17, (IEN | PDIS | M1)},
103 {GPMC_A18, (IEN | PDIS | M1)},
104 {GPMC_CS0, (IEN | PTU | PDIS | M15)},
105 {GPMC_CS2, (IEN | PTU | PDIS | M1)},
106 {GPMC_CS3, (IEN | PTU | PDIS | M3)},
107 {GPMC_CLK, (IEN | PTU | PDIS | M15)},
108 {GPMC_ADVN_ALE, (IEN | PTU | PDIS | M15)},
109 {GPMC_OEN_REN, (IEN | PTU | PDIS | M15)},
110 {GPMC_WEN, (IEN | PTU | PDIS | M15)},
111 {GPMC_BEN0, (IEN | PTU | PDIS | M15)},
112 {GPMC_BEN1, (IEN | PTU | PDIS | M15)},
113 {GPMC_WAIT0, (FSC | IEN | PTU | PDIS | M15)},
114 {VIN1A_CLK0, (IEN | PDIS | M0)},
115 {VIN1B_CLK1, (FSC | IEN | PDIS | M0)},
116 {VIN1A_DE0, (IEN | PDIS | M0)},
117 {VIN1A_FLD0, (IEN | PDIS | M15)},
118 {VIN1A_HSYNC0, (IEN | PDIS | M0)},
119 {VIN1A_VSYNC0, (IEN | PDIS | M0)},
120 {VIN1A_D0, (IEN | PDIS | M0)},
121 {VIN1A_D1, (IEN | PDIS | M0)},
122 {VIN1A_D2, (IEN | PDIS | M0)},
123 {VIN1A_D3, (IEN | PDIS | M0)},
124 {VIN1A_D4, (IEN | PDIS | M0)},
125 {VIN1A_D5, (IEN | PDIS | M0)},
126 {VIN1A_D6, (IEN | PDIS | M0)},
127 {VIN1A_D7, (IEN | PDIS | M0)},
128 {VIN1A_D8, (IEN | PDIS | M0)},
129 {VIN1A_D9, (IEN | PDIS | M0)},
130 {VIN1A_D10, (IEN | PDIS | M0)},
131 {VIN1A_D11, (IEN | PDIS | M0)},
132 {VIN1A_D12, (IEN | PDIS | M0)},
133 {VIN1A_D13, (IEN | PDIS | M0)},
134 {VIN1A_D14, (IEN | PDIS | M0)},
135 {VIN1A_D15, (IEN | PDIS | M0)},
136 {VIN1A_D16, (IEN | PDIS | M0)},
137 {VIN1A_D17, (IEN | PDIS | M0)},
138 {VIN1A_D18, (IEN | PDIS | M0)},
139 {VIN1A_D19, (IEN | PDIS | M0)},
140 {VIN1A_D20, (IEN | PDIS | M0)},
141 {VIN1A_D21, (IEN | PDIS | M0)},
142 {VIN1A_D22, (IEN | PDIS | M0)},
143 {VIN1A_D23, (IEN | PDIS | M0)},
144 {VIN2A_CLK0, (IEN | PDIS | M15)},
145 {VIN2A_DE0, (IEN | PDIS | M15)},
146 {VIN2A_FLD0, (IEN | PDIS | M15)},
147 {VIN2A_HSYNC0, (IEN | PDIS | M15)},
148 {VIN2A_VSYNC0, (IEN | PDIS | M15)},
149 {VIN2A_D0, (IEN | PDIS | M15)},
150 {VIN2A_D1, (IEN | PDIS | M15)},
151 {VIN2A_D2, (IEN | PDIS | M15)},
152 {VIN2A_D3, (IEN | PDIS | M15)},
153 {VIN2A_D4, (IEN | PDIS | M15)},
154 {VIN2A_D5, (IEN | PDIS | M15)},
155 {VIN2A_D6, (IEN | PDIS | M15)},
156 {VIN2A_D7, (IEN | PDIS | M15)},
157 {VIN2A_D8, (IEN | PDIS | M15)},
158 {VIN2A_D9, (IEN | PDIS | M15)},
159 {VIN2A_D10, (IEN | PDIS | M15)},
160 {VIN2A_D11, (IEN | PDIS | M15)},
161 {VIN2A_D12, (IEN | PDIS | M3)},
162 {VIN2A_D13, (IEN | PDIS | M3)},
163 {VIN2A_D14, (IEN | PDIS | M3)},
164 {VIN2A_D15, (IEN | PDIS | M3)},
165 {VIN2A_D16, (IEN | PDIS | M3)},
166 {VIN2A_D17, (IEN | PDIS | M3)},
167 {VIN2A_D18, (IEN | PDIS | M3)},
168 {VIN2A_D19, (IEN | PDIS | M3)},
169 {VIN2A_D20, (IEN | PDIS | M3)},
170 {VIN2A_D21, (IEN | PDIS | M3)},
171 {VIN2A_D22, (IEN | PDIS | M3)},
172 {VIN2A_D23, (IEN | PDIS | M3)},
173 {VOUT1_CLK, (IEN | PDIS | M0)},
174 {VOUT1_DE, (IEN | PDIS | M0)},
175 {VOUT1_FLD, (IEN | PDIS | M15)},
176 {VOUT1_HSYNC, (IEN | PDIS | M0)},
177 {VOUT1_VSYNC, (IEN | PDIS | M0)},
178 {VOUT1_D0, (IEN | PDIS | M0)},
179 {VOUT1_D1, (IEN | PDIS | M0)},
180 {VOUT1_D2, (IEN | PDIS | M0)},
181 {VOUT1_D3, (IEN | PDIS | M0)},
182 {VOUT1_D4, (IEN | PDIS | M0)},
183 {VOUT1_D5, (IEN | PDIS | M0)},
184 {VOUT1_D6, (IEN | PDIS | M0)},
185 {VOUT1_D7, (IEN | PDIS | M0)},
186 {VOUT1_D8, (IEN | PDIS | M0)},
187 {VOUT1_D9, (IEN | PDIS | M0)},
188 {VOUT1_D10, (IEN | PDIS | M0)},
189 {VOUT1_D11, (IEN | PDIS | M0)},
190 {VOUT1_D12, (IEN | PDIS | M0)},
191 {VOUT1_D13, (IEN | PDIS | M0)},
192 {VOUT1_D14, (IEN | PDIS | M0)},
193 {VOUT1_D15, (IEN | PDIS | M0)},
194 {VOUT1_D16, (IEN | PDIS | M0)},
195 {VOUT1_D17, (IEN | PDIS | M0)},
196 {VOUT1_D18, (IEN | PDIS | M0)},
197 {VOUT1_D19, (IEN | PDIS | M0)},
198 {VOUT1_D20, (IEN | PDIS | M0)},
199 {VOUT1_D21, (IEN | PDIS | M0)},
200 {VOUT1_D22, (IEN | PDIS | M0)},
201 {VOUT1_D23, (IEN | PDIS | M0)},
202 {MDIO_MCLK, (FSC | IEN | PTU | PEN | M0)},
203 {MDIO_D, (FSC | IEN | PTU | PEN | M0)},
204 {RMII_MHZ_50_CLK, (IEN | PDIS | M15)},
205 {UART3_RXD, (FSC | IEN | PDIS | M15)},
206 {UART3_TXD, (FSC | IEN | PDIS | M15)},
207 {RGMII0_TXC, (IEN | PDIS | M0)},
208 {RGMII0_TXCTL, (IEN | PDIS | M0)},
209 {RGMII0_TXD3, (IEN | PDIS | M0)},
210 {RGMII0_TXD2, (IEN | PDIS | M0)},
211 {RGMII0_TXD1, (IEN | PDIS | M0)},
212 {RGMII0_TXD0, (IEN | PDIS | M0)},
213 {RGMII0_RXC, (IEN | PDIS | M0)},
214 {RGMII0_RXCTL, (IEN | PDIS | M0)},
215 {RGMII0_RXD3, (IEN | PDIS | M0)},
216 {RGMII0_RXD2, (IEN | PDIS | M0)},
217 {RGMII0_RXD1, (IEN | PDIS | M0)},
218 {RGMII0_RXD0, (IEN | PDIS | M0)},
219 {USB1_DRVVBUS, (FSC | IEN | PDIS | M0)},
220 {USB2_DRVVBUS, (FSC | IEN | PDIS | M0)},
221 {GPIO6_14, (IEN | PTU | PEN | M9)},
222 {GPIO6_15, (IEN | PTU | PEN | M9)},
223 {GPIO6_16, (IEN | PTU | PDIS | M14)},
224 {XREF_CLK0, (IEN | PDIS | M4)},
225 {XREF_CLK1, (IEN | PDIS | M4)},
226 {XREF_CLK2, (IEN | PDIS | M3)},
227 {XREF_CLK3, (IEN | PTD | PEN | M14)},
228 {MCASP1_ACLKX, (IEN | PDIS | M0)},
229 {MCASP1_FSX, (FSC | IEN | PDIS | M0)},
230 {MCASP1_ACLKR, (IEN | PTD | PEN | M14)},
231 {MCASP1_FSR, (IEN | PDIS | M15)},
232 {MCASP1_AXR0, (FSC | IEN | PDIS | M0)},
233 {MCASP1_AXR1, (FSC | IEN | PDIS | M0)},
234 {MCASP1_AXR2, (IEN | PTD | PEN | M14)},
235 {MCASP1_AXR3, (IEN | PTD | PEN | M14)},
236 {MCASP1_AXR4, (IEN | PTD | PEN | M14)},
237 {MCASP1_AXR5, (IEN | PTD | PEN | M14)},
238 {MCASP1_AXR6, (IEN | PTD | PEN | M14)},
239 {MCASP1_AXR7, (IEN | PTD | PEN | M14)},
240 {MCASP1_AXR8, (FSC | IEN | PDIS | M1)},
241 {MCASP1_AXR9, (FSC | IEN | PDIS | M1)},
242 {MCASP1_AXR10, (FSC | IEN | PDIS | M1)},
243 {MCASP1_AXR11, (FSC | IEN | PDIS | M1)},
244 {MCASP1_AXR12, (FSC | IEN | PDIS | M1)},
245 {MCASP1_AXR13, (FSC | IEN | PDIS | M1)},
246 {MCASP1_AXR14, (FSC | IEN | PDIS | M1)},
247 {MCASP1_AXR15, (FSC | IEN | PDIS | M1)},
248 {MCASP2_ACLKX, (IEN | PDIS | M0)},
249 {MCASP2_FSX, (FSC | IEN | PDIS | M0)},
250 {MCASP2_ACLKR, (IEN | PDIS | M15)},
251 {MCASP2_FSR, (IEN | PDIS | M15)},
252 {MCASP2_AXR0, (IEN | PDIS | M0)},
253 {MCASP2_AXR1, (IEN | PDIS | M0)},
254 {MCASP2_AXR2, (FSC | IEN | PDIS | M0)},
255 {MCASP2_AXR3, (FSC | IEN | PDIS | M0)},
256 {MCASP2_AXR4, (IEN | PDIS | M0)},
257 {MCASP2_AXR5, (IEN | PDIS | M0)},
258 {MCASP2_AXR6, (IEN | PDIS | M0)},
259 {MCASP2_AXR7, (IEN | PDIS | M0)},
260 {MCASP3_ACLKX, (IEN | PDIS | M0)},
261 {MCASP3_FSX, (FSC | IEN | PDIS | M0)},
262 {MCASP3_AXR0, (FSC | IEN | PDIS | M0)},
263 {MCASP3_AXR1, (FSC | IEN | PDIS | M0)},
264 {MCASP4_ACLKX, (IEN | PTU | PEN | M4)},
265 {MCASP4_FSX, (IEN | PTU | PEN | M4)},
266 {MCASP4_AXR0, (IEN | PDIS | M15)},
267 {MCASP4_AXR1, (IEN | PDIS | M15)},
268 {MCASP5_ACLKX, (IEN | PDIS | M0)},
269 {MCASP5_FSX, (IEN | PDIS | M0)},
270 {MCASP5_AXR0, (IEN | PDIS | M0)},
271 {MCASP5_AXR1, (IEN | PDIS | M15)},
272 {GPIO6_10, (IEN | PTU | PDIS | M15)},
273 {GPIO6_11, (IEN | PTU | PDIS | M0)},
274 {MMC3_CLK, (IEN | PTU | PDIS | M0)},
275 {MMC3_CMD, (IEN | PTU | PDIS | M0)},
276 {MMC3_DAT0, (IEN | PTU | PDIS | M0)},
277 {MMC3_DAT1, (IEN | PTU | PDIS | M0)},
278 {MMC3_DAT2, (IEN | PTU | PDIS | M0)},
279 {MMC3_DAT3, (IEN | PTU | PDIS | M0)},
280 {MMC3_DAT4, (IEN | PTU | PDIS | M15)},
281 {MMC3_DAT5, (IEN | PTU | PDIS | M15)},
282 {MMC3_DAT6, (IEN | PTU | PDIS | M15)},
283 {MMC3_DAT7, (IEN | PTU | PDIS | M15)},
284 {SPI1_SCLK, (IEN | PDIS | M0)},
285 {SPI1_D1, (IEN | PDIS | M0)},
286 {SPI1_D0, (IEN | PDIS | M0)},
287 {SPI1_CS0, (IEN | PTU | PDIS | M0)},
288 {SPI1_CS1, (IEN | PTU | PDIS | M0)},
289 {SPI1_CS2, (FSC | IEN | PTU | PDIS | M6)},
290 {SPI1_CS3, (FSC | IEN | PTU | PEN | M6)},
291 {SPI2_SCLK, (IEN | PDIS | M1)},
292 {SPI2_D1, (FSC | IEN | PDIS | M1)},
293 {SPI2_D0, (FSC | IEN | PDIS | M1)},
294 {SPI2_CS0, (FSC | IEN | PTU | PDIS | M1)},
295 {DCAN1_TX, (FSC | IEN | PTU | PDIS | M0)},
296 {DCAN1_RX, (FSC | IEN | PTU | PDIS | M0)},
297 {UART2_RXD, (IEN | PTU | PDIS | M3)},
298 {UART2_TXD, (IEN | PTU | PDIS | M3)},
299 {UART2_CTSN, (IEN | PTU | PDIS | M3)},
300 {UART2_RTSN, (IEN | PTU | PDIS | M3)},
301 {I2C2_SDA, (IEN | PTU | PDIS | M0)},
302 {I2C2_SCL, (IEN | PTU | PDIS | M0)},
303 {WAKEUP0, (PEN | M0)},
304 {WAKEUP1, (PEN | M0)},
305 {WAKEUP2, (PTU | PEN | M14)},
306 {WAKEUP3, (PEN | M15)},
307 {ON_OFF, (PTU | PDIS | M0)},
308 {RTC_PORZ, (PEN | M0)},
309 {TMS, (IEN | PTU | PDIS | M0)},
310 {TDI, (FSC | IEN | PTU | PDIS | M0)},
311 {TDO, (IEN | PTU | PDIS | M0)},
312 {TCLK, (IEN | PTU | PDIS | M0)},
313 {TRSTN, (IEN | PDIS | M0)},
314 {RTCK, (IEN | PTD | PEN | M0)},
315 {EMU0, (IEN | PTU | PDIS | M0)},
316 {EMU1, (IEN | PTU | PDIS | M0)},
317 {RESETN, (PTU | PDIS | M0)},
318 {NMIN, (PDIS | M0)},
319 {RSTOUTN, (PDIS | M0)},
56}; 320};
57#endif /* _MUX_DATA_DRA7XX_H_ */ 321#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 6b37e1dc83..05838585d8 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -46,4 +46,26 @@
46#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ 46#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
47 47
48#define CONFIG_SYS_OMAP_ABE_SYSCK 48#define CONFIG_SYS_OMAP_ABE_SYSCK
49#define CONFIG_SYS_DCACHE_OFF
50#define CONFIG_SYS_ICACHE_OFF
51
52#define EMIF1_EMIF2
53
54/* SPI */
55#define CONFIG_TI_QSPI
56#define CONFIG_SPI_FLASH
57#define CONFIG_SPI_FLASH_SPANSION
58#define CONFIG_CMD_SF
59#define CONFIG_CMD_SPI
60#define CONFIG_SF_DEFAULT_SPEED 12000000
61#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
62
63/* SPI SPL */
64#define CONFIG_SPL_SPI_SUPPORT
65#define CONFIG_SPL_SPI_LOAD
66#define CONFIG_SPL_SPI_FLASH_SUPPORT
67#define CONFIG_SPL_SPI_BUS 0
68#define CONFIG_SPL_SPI_CS 0
69#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
70
49#endif /* __CONFIG_DRA7XX_EVM_H */ 71#endif /* __CONFIG_DRA7XX_EVM_H */