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authorLokesh Vutla2013-05-27 23:28:11 -0500
committerLokesh Vutla2013-05-29 04:35:08 -0500
commitd82549eb8ac15f156e5bdfc985b19c073a927ccb (patch)
tree9ba334f8af4cfbe8dda09eda9e6356b439d40452
parent853f3993dfd323534a236ce3811a253f95ab6c4b (diff)
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ARM: DRA7xx: clocks: Update PLL values
Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>
-rw-r--r--arch/arm/cpu/armv7/omap-common/clocks-common.c16
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c87
-rw-r--r--arch/arm/cpu/armv7/omap5/prcm-regs.c1
-rw-r--r--arch/arm/include/asm/arch-omap4/clocks.h2
-rw-r--r--arch/arm/include/asm/arch-omap5/clocks.h8
-rw-r--r--arch/arm/include/asm/omap_common.h3
-rw-r--r--include/configs/dra7xx_evm.h1
7 files changed, 72 insertions, 46 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 928327ab63..88d93926cb 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -50,13 +50,12 @@
50 50
51const u32 sys_clk_array[8] = { 51const u32 sys_clk_array[8] = {
52 12000000, /* 12 MHz */ 52 12000000, /* 12 MHz */
53 13000000, /* 13 MHz */ 53 20000000, /* 20 MHz */
54 16800000, /* 16.8 MHz */ 54 16800000, /* 16.8 MHz */
55 19200000, /* 19.2 MHz */ 55 19200000, /* 19.2 MHz */
56 26000000, /* 26 MHz */ 56 26000000, /* 26 MHz */
57 27000000, /* 27 MHz */ 57 27000000, /* 27 MHz */
58 38400000, /* 38.4 MHz */ 58 38400000, /* 38.4 MHz */
59 20000000, /* 20 MHz */
60}; 59};
61 60
62static inline u32 __get_sys_clk_index(void) 61static inline u32 __get_sys_clk_index(void)
@@ -75,13 +74,6 @@ static inline u32 __get_sys_clk_index(void)
75 /* SYS_CLKSEL - 1 to match the dpll param array indices */ 74 /* SYS_CLKSEL - 1 to match the dpll param array indices */
76 ind = (readl((*prcm)->cm_sys_clksel) & 75 ind = (readl((*prcm)->cm_sys_clksel) &
77 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; 76 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
78 /*
79 * SYS_CLKSEL value for 20MHz is 0. This is introduced newly
80 * in DRA7XX socs. SYS_CLKSEL -1 will be greater than
81 * NUM_SYS_CLK. So considering the last 3 bits as the index
82 * for the dpll param array.
83 */
84 ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
85 } 77 }
86 return ind; 78 return ind;
87} 79}
@@ -441,6 +433,12 @@ static void setup_non_essential_dplls(void)
441 params = get_abe_dpll_params(*dplls_data); 433 params = get_abe_dpll_params(*dplls_data);
442#ifdef CONFIG_SYS_OMAP_ABE_SYSCK 434#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
443 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; 435 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
436
437 if (omap_revision() == DRA752_ES1_0)
438 /* Select the sys clk for dpll_abe */
439 clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
440 CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
441 CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
444#else 442#else
445 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; 443 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
446 /* 444 /*
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 53aea93077..83033907d9 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -100,14 +100,13 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
100}; 100};
101 101
102static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { 102static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
103 {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 103 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
104 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 104 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
105 {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 105 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
106 {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 106 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
107 {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 107 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
108 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 108 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
109 {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 109 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
110 {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
111}; 110};
112 111
113static const struct dpll_params 112static const struct dpll_params
@@ -133,15 +132,14 @@ static const struct dpll_params
133}; 132};
134 133
135static const struct dpll_params 134static const struct dpll_params
136 core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = { 135 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
137 {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */ 136 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
138 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 137 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
139 {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */ 138 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
140 {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */ 139 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
141 {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */ 140 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
142 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 141 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
143 {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */ 142 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
144 {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */
145}; 143};
146 144
147static const struct dpll_params 145static const struct dpll_params
@@ -187,14 +185,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
187}; 185};
188 186
189static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { 187static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
190 {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ 188 {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
191 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 189 {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
192 {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 190 {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
193 {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 191 {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
194 {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ 192 {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
195 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 193 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
196 {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ 194 {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
197 {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */
198}; 195};
199 196
200static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { 197static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
@@ -207,6 +204,16 @@ static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
207 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 204 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
208}; 205};
209 206
207static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
208 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
209 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
210 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
211 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
212 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
213 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
214 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
215};
216
210/* ABE M & N values with sys_clk as source */ 217/* ABE M & N values with sys_clk as source */
211static const struct dpll_params 218static const struct dpll_params
212 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { 219 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
@@ -224,26 +231,36 @@ static const struct dpll_params abe_dpll_params_32k_196608khz = {
224 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 231 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
225}; 232};
226 233
234/* ABE M & N values with sysclk2(22.5792 MHz) as input */
235static const struct dpll_params
236 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
237 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
238 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
239 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
240 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
241 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
242 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
243 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
244};
245
227static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { 246static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
228 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 247 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
229 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 248 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
230 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 249 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
231 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 250 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
232 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 251 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
233 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 252 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
234 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 253 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
235 {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
236}; 254};
237 255
238static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = { 256static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
239 {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 257 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
240 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 258 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
241 {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 259 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
242 {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 260 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
243 {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 261 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
244 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 262 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
245 {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 263 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
246 {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
247}; 264};
248 265
249struct dplls omap5_dplls_es1 = { 266struct dplls omap5_dplls_es1 = {
@@ -276,10 +293,12 @@ struct dplls omap5_dplls_es2 = {
276 293
277struct dplls dra7xx_dplls = { 294struct dplls dra7xx_dplls = {
278 .mpu = mpu_dpll_params_1ghz, 295 .mpu = mpu_dpll_params_1ghz,
279 .core = core_dpll_params_2128mhz_ddr532_dra7xx, 296 .core = core_dpll_params_2128mhz_dra7xx,
280 .per = per_dpll_params_768mhz_dra7xx, 297 .per = per_dpll_params_768mhz_dra7xx,
298 .abe = abe_dpll_params_sysclk2_361267khz,
299 .iva = iva_dpll_params_2330mhz_dra7xx,
281 .usb = usb_dpll_params_1920mhz, 300 .usb = usb_dpll_params_1920mhz,
282 .ddr = ddr_dpll_params_1066mhz, 301 .ddr = ddr_dpll_params_2128mhz,
283}; 302};
284 303
285struct pmic_data palmas = { 304struct pmic_data palmas = {
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index db779f2d62..fdf204fd71 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -943,6 +943,7 @@ struct prcm_regs const dra7xx_prcm = {
943 /* l4 wkup regs */ 943 /* l4 wkup regs */
944 .cm_abe_pll_ref_clksel = 0x4ae0610c, 944 .cm_abe_pll_ref_clksel = 0x4ae0610c,
945 .cm_sys_clksel = 0x4ae06110, 945 .cm_sys_clksel = 0x4ae06110,
946 .cm_abe_pll_sys_clksel = 0x4ae06118,
946 .cm_wkup_clkstctrl = 0x4ae07800, 947 .cm_wkup_clkstctrl = 0x4ae07800,
947 .cm_wkup_l4wkup_clkctrl = 0x4ae07820, 948 .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
948 .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, 949 .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index f544edfbd0..e94fae6f2a 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -76,7 +76,7 @@
76#define CM_CLKSEL_DCC_EN_MASK (1 << 22) 76#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
77 77
78/* CM_SYS_CLKSEL */ 78/* CM_SYS_CLKSEL */
79#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 79#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
80 80
81/* CM_CLKSEL_CORE */ 81/* CM_CLKSEL_CORE */
82#define CLKSEL_CORE_SHIFT 0 82#define CLKSEL_CORE_SHIFT 0
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index cfcf51d0f9..41c4f660bf 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -81,7 +81,7 @@
81#define CM_CLKSEL_DCC_EN_MASK (1 << 22) 81#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
82 82
83/* CM_SYS_CLKSEL */ 83/* CM_SYS_CLKSEL */
84#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 84#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
85 85
86/* CM_CLKSEL_CORE */ 86/* CM_CLKSEL_CORE */
87#define CLKSEL_CORE_SHIFT 0 87#define CLKSEL_CORE_SHIFT 0
@@ -98,6 +98,12 @@
98#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 98#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
99#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 99#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
100 100
101/* CM_CLKSEL_ABE_PLL_SYS */
102#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0
103#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1
104#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0
105#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1
106
101/* CM_BYPCLK_DPLL_IVA */ 107/* CM_BYPCLK_DPLL_IVA */
102#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 108#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
103#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 109#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 700717763c..86ddd65b60 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -29,7 +29,7 @@
29 29
30#include <common.h> 30#include <common.h>
31 31
32#define NUM_SYS_CLKS 8 32#define NUM_SYS_CLKS 7
33 33
34struct prcm_regs { 34struct prcm_regs {
35 /* cm1.ckgen */ 35 /* cm1.ckgen */
@@ -301,6 +301,7 @@ struct prcm_regs {
301 /* l4 wkup regs */ 301 /* l4 wkup regs */
302 u32 cm_abe_pll_ref_clksel; 302 u32 cm_abe_pll_ref_clksel;
303 u32 cm_sys_clksel; 303 u32 cm_sys_clksel;
304 u32 cm_abe_pll_sys_clksel;
304 u32 cm_wkup_clkstctrl; 305 u32 cm_wkup_clkstctrl;
305 u32 cm_wkup_l4wkup_clkctrl; 306 u32 cm_wkup_l4wkup_clkctrl;
306 u32 cm_wkup_wdtimer1_clkctrl; 307 u32 cm_wkup_wdtimer1_clkctrl;
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index fc35f2f9a8..6b37e1dc83 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -45,4 +45,5 @@
45#define NON_SECURE_SRAM_START 0x40300000 45#define NON_SECURE_SRAM_START 0x40300000
46#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ 46#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
47 47
48#define CONFIG_SYS_OMAP_ABE_SYSCK
48#endif /* __CONFIG_DRA7XX_EVM_H */ 49#endif /* __CONFIG_DRA7XX_EVM_H */