ARM: DRA7xx: clocks: Update PLL values

Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>

7 files changed, 72 insertions, 46 deletions

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 928327ab63..88d93926cb 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -50,13 +50,12 @@
 
 const u32 sys_clk_array[8] = {
         12000000,              /* 12 MHz */
-        13000000,              /* 13 MHz */
+        20000000,               /* 20 MHz */
         16800000,              /* 16.8 MHz */
         19200000,              /* 19.2 MHz */
         26000000,              /* 26 MHz */
         27000000,              /* 27 MHz */
         38400000,              /* 38.4 MHz */
-        20000000,               /* 20 MHz */
 };
 
 static inline u32 __get_sys_clk_index(void)
@@ -75,13 +74,6 @@ static inline u32 __get_sys_clk_index(void)
                 /* SYS_CLKSEL - 1 to match the dpll param array indices */
                 ind = (readl((*prcm)->cm_sys_clksel) &
                         CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
-                /*
-                 * SYS_CLKSEL value for 20MHz is 0. This is introduced newly
-                 * in DRA7XX socs. SYS_CLKSEL -1 will be greater than
-                 * NUM_SYS_CLK. So considering the last 3 bits as the index
-                 * for the dpll param array.
-                 */
-                ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
         }
         return ind;
 }
@@ -441,6 +433,12 @@ static void setup_non_essential_dplls(void)
         params = get_abe_dpll_params(*dplls_data);
 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
         abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+
+        if (omap_revision() == DRA752_ES1_0)
+                /* Select the sys clk for dpll_abe */
+                clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
+                                CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
+                                CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
 #else
         abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
         /*
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 53aea93077..83033907d9 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -100,14 +100,13 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
 };
 
 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
-        {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
-        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
-        {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
-        {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
-        {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
+        {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
+        {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz   */
+        {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
+        {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
+        {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 26 MHz   */
         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
-        {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
-        {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}          /* 20 MHz   */
+        {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 38.4 MHz */
 };
 
 static const struct dpll_params
@@ -133,15 +132,14 @@ static const struct dpll_params
 };
 
 static const struct dpll_params
-                core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
-        {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},             /* 12 MHz   */
-        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
-        {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},             /* 16.8 MHz */
-        {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},             /* 19.2 MHz */
-        {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},             /* 26 MHz   */
+                core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
+        {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 12 MHz   */
+        {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 20 MHz   */
+        {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 16.8 MHz */
+        {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 19.2 MHz */
+        {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 26 MHz   */
         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
-        {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6},             /* 38.4 MHz */
-        {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}              /* 20 MHz   */
+        {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 38.4 MHz */
 };
 
 static const struct dpll_params
@@ -187,14 +185,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 };
 
 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
-        {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 12 MHz   */
-        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
-        {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},           /* 16.8 MHz */
-        {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 19.2 MHz */
-        {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},          /* 26 MHz   */
+        {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 12 MHz   */
+        {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 20 MHz   */
+        {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 16.8 MHz */
+        {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 19.2 MHz */
+        {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},           /* 26 MHz   */
         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
-        {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 38.4 MHz */
-        {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}             /* 20 MHz   */
+        {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 38.4 MHz */
 };
 
 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
@@ -207,6 +204,16 @@ static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
         {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}           /* 38.4 MHz */
 };
 
+static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
+        {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
+        {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz */
+        {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
+        {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
+        {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
+        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
+        {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 38.4 MHz */
+};
+
 /* ABE M & N values with sys_clk as source */
 static const struct dpll_params
                 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
@@ -224,26 +231,36 @@ static const struct dpll_params abe_dpll_params_32k_196608khz = {
         750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
 };
 
+/* ABE M & N values with sysclk2(22.5792 MHz) as input */
+static const struct dpll_params
+                abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
+        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
+        {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
+        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 16.8 MHz */
+        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
+        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
+        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
+        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
+};
+
 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
         {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
-        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
+        {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 20 MHz   */
         {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
         {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
         {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
         {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
-        {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}          /* 20 MHz   */
 };
 
-static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = {
-        {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
-        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
-        {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
-        {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},          /* 19.2 MHz */
-        {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},           /* 26 MHz   */
+static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
+        {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 12 MHz   */
+        {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
+        {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
+        {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
+        {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
-        {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1},         /* 38.4 MHz */
-        {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}          /* 20 MHz   */
+        {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 38.4 MHz */
 };
 
 struct dplls omap5_dplls_es1 = {
@@ -276,10 +293,12 @@ struct dplls omap5_dplls_es2 = {
 
 struct dplls dra7xx_dplls = {
         .mpu = mpu_dpll_params_1ghz,
-        .core = core_dpll_params_2128mhz_ddr532_dra7xx,
+        .core = core_dpll_params_2128mhz_dra7xx,
         .per = per_dpll_params_768mhz_dra7xx,
+        .abe = abe_dpll_params_sysclk2_361267khz,
+        .iva = iva_dpll_params_2330mhz_dra7xx,
         .usb = usb_dpll_params_1920mhz,
-        .ddr = ddr_dpll_params_1066mhz,
+        .ddr = ddr_dpll_params_2128mhz,
 };
 
 struct pmic_data palmas = {
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index db779f2d62..fdf204fd71 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -943,6 +943,7 @@ struct prcm_regs const dra7xx_prcm = {
         /* l4 wkup regs */
         .cm_abe_pll_ref_clksel                  = 0x4ae0610c,
         .cm_sys_clksel                          = 0x4ae06110,
+        .cm_abe_pll_sys_clksel                  = 0x4ae06118,
         .cm_wkup_clkstctrl                      = 0x4ae07800,
         .cm_wkup_l4wkup_clkctrl                 = 0x4ae07820,
         .cm_wkup_wdtimer1_clkctrl               = 0x4ae07828,
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index f544edfbd0..e94fae6f2a 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -76,7 +76,7 @@
 #define CM_CLKSEL_DCC_EN_MASK                   (1 << 22)
 
 /* CM_SYS_CLKSEL */
-#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK   7
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
 
 /* CM_CLKSEL_CORE */
 #define CLKSEL_CORE_SHIFT       0
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index cfcf51d0f9..41c4f660bf 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -81,7 +81,7 @@
 #define CM_CLKSEL_DCC_EN_MASK                   (1 << 22)
 
 /* CM_SYS_CLKSEL */
-#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK   7
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
 
 /* CM_CLKSEL_CORE */
 #define CLKSEL_CORE_SHIFT       0
@@ -98,6 +98,12 @@
 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK     0
 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK     1
 
+/* CM_CLKSEL_ABE_PLL_SYS */
+#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT      0
+#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK       1
+#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1           0
+#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2           1
+
 /* CM_BYPCLK_DPLL_IVA */
 #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT         0
 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK          3
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 700717763c..86ddd65b60 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -29,7 +29,7 @@
 
 #include <common.h>
 
-#define NUM_SYS_CLKS    8
+#define NUM_SYS_CLKS    7
 
 struct prcm_regs {
         /* cm1.ckgen */
@@ -301,6 +301,7 @@ struct prcm_regs {
         /* l4 wkup regs */
         u32 cm_abe_pll_ref_clksel;
         u32 cm_sys_clksel;
+        u32 cm_abe_pll_sys_clksel;
         u32 cm_wkup_clkstctrl;
         u32 cm_wkup_l4wkup_clkctrl;
         u32 cm_wkup_wdtimer1_clkctrl;
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index fc35f2f9a8..6b37e1dc83 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -45,4 +45,5 @@
 #define NON_SECURE_SRAM_START   0x40300000
 #define NON_SECURE_SRAM_END     0x40380000      /* Not inclusive */
 
+#define CONFIG_SYS_OMAP_ABE_SYSCK
 #endif /* __CONFIG_DRA7XX_EVM_H */