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authorSRICHARAN R2013-04-23 19:41:22 -0500
committerTom Rini2013-05-10 07:25:56 -0500
commitf92f2277a6cadfdc703a6700593cac3d8211bf53 (patch)
tree28279dfce87e60de4587eefe89e155c7d04a8dfa
parent76db5b8f59d0c9c9eb73f1595f8fbc557e7a16eb (diff)
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ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines common
These defines are same across OMAP4/5. So move them to omap_common.h. This is required for the patches that follow. Signed-off-by: Sricharan R <r.sricharan@ti.com>
-rw-r--r--arch/arm/cpu/armv7/omap4/emif.c4
-rw-r--r--arch/arm/cpu/armv7/omap4/hw_data.c2
-rw-r--r--arch/arm/cpu/armv7/omap4/hwinit.c3
-rw-r--r--arch/arm/cpu/armv7/omap5/emif.c4
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c2
-rw-r--r--arch/arm/cpu/armv7/omap5/hwinit.c3
-rw-r--r--arch/arm/include/asm/arch-omap4/omap.h12
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h13
-rw-r--r--arch/arm/include/asm/omap_common.h14
9 files changed, 24 insertions, 33 deletions
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 53f60635b1..0ddf35f79b 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -31,8 +31,8 @@
31#include <asm/utils.h> 31#include <asm/utils.h>
32 32
33#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 33#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
34u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM; 34u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
35u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN; 35u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
36#endif 36#endif
37 37
38#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 38#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 04977b4f2b..06a2fc8c2f 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -40,7 +40,7 @@ struct dplls const **dplls_data =
40struct vcores_data const **omap_vcores = 40struct vcores_data const **omap_vcores =
41 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; 41 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
42struct omap_sys_ctrl_regs const **ctrl = 42struct omap_sys_ctrl_regs const **ctrl =
43 (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL; 43 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
44 44
45/* 45/*
46 * The M & N values in the following tables are created using the 46 * The M & N values in the following tables are created using the
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
index 2db517b1bf..81f5a48e50 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -34,10 +34,11 @@
34#include <asm/sizes.h> 34#include <asm/sizes.h>
35#include <asm/emif.h> 35#include <asm/emif.h>
36#include <asm/arch/gpio.h> 36#include <asm/arch/gpio.h>
37#include <asm/omap_common.h>
37 38
38DECLARE_GLOBAL_DATA_PTR; 39DECLARE_GLOBAL_DATA_PTR;
39 40
40u32 *const omap_si_rev = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV; 41u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
41 42
42static const struct gpio_bank gpio_bank_44xx[6] = { 43static const struct gpio_bank gpio_bank_44xx[6] = {
43 { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX }, 44 { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
diff --git a/arch/arm/cpu/armv7/omap5/emif.c b/arch/arm/cpu/armv7/omap5/emif.c
index 3f37abdf83..b4c1319adc 100644
--- a/arch/arm/cpu/armv7/omap5/emif.c
+++ b/arch/arm/cpu/armv7/omap5/emif.c
@@ -32,8 +32,8 @@
32 32
33#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 33#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
34#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) 34#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
35static u32 *const T_num = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_NUM; 35static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
36static u32 *const T_den = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_DEN; 36static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
37#endif 37#endif
38 38
39#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 39#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 5698876960..604fa42b1b 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -41,7 +41,7 @@ struct dplls const **dplls_data =
41struct vcores_data const **omap_vcores = 41struct vcores_data const **omap_vcores =
42 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; 42 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
43struct omap_sys_ctrl_regs const **ctrl = 43struct omap_sys_ctrl_regs const **ctrl =
44 (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL; 44 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
45 45
46/* OPP HIGH FREQUENCY for ES2.0 */ 46/* OPP HIGH FREQUENCY for ES2.0 */
47static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { 47static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index d29df78720..e192fea0eb 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -37,10 +37,11 @@
37#include <asm/utils.h> 37#include <asm/utils.h>
38#include <asm/arch/gpio.h> 38#include <asm/arch/gpio.h>
39#include <asm/emif.h> 39#include <asm/emif.h>
40#include <asm/omap_common.h>
40 41
41DECLARE_GLOBAL_DATA_PTR; 42DECLARE_GLOBAL_DATA_PTR;
42 43
43u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV; 44u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
44 45
45static struct gpio_bank gpio_bank_54xx[6] = { 46static struct gpio_bank gpio_bank_54xx[6] = {
46 { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX }, 47 { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 9ad1e821ec..e9a6ffeb83 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -143,16 +143,4 @@ struct s32ktimer {
143#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ 143#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
144/* base address for indirect vectors (internal boot mode) */ 144/* base address for indirect vectors (internal boot mode) */
145#define SRAM_ROM_VECT_BASE 0x4030D000 145#define SRAM_ROM_VECT_BASE 0x4030D000
146/* Temporary SRAM stack used while low level init is done */
147#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
148/* SRAM scratch space entries */
149#define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR
150#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
151#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
152#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
153#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
154#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
155#define OMAP4_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
156#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
157
158#endif 146#endif
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 3bf5afae1a..4f43a903d8 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -191,19 +191,6 @@ struct s32ktimer {
191/* base address for indirect vectors (internal boot mode) */ 191/* base address for indirect vectors (internal boot mode) */
192#define SRAM_ROM_VECT_BASE 0x4031F000 192#define SRAM_ROM_VECT_BASE 0x4031F000
193 193
194#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
195/*
196 * SRAM scratch space entries
197 */
198#define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR
199#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
200#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
201#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
202#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
203#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
204#define OMAP5_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
205#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
206
207/* Silicon revisions */ 194/* Silicon revisions */
208#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF 195#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
209#define OMAP4430_ES1_0 0x44300100 196#define OMAP4430_ES1_0 0x44300100
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 6d377d5b59..837b69fdab 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -584,4 +584,18 @@ static inline u32 omap_revision(void)
584 584
585/* DRA7XX */ 585/* DRA7XX */
586#define DRA752_ES1_0 0x07520100 586#define DRA752_ES1_0 0x07520100
587
588/*
589 * SRAM scratch space entries
590 */
591#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
592#define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR
593#define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
594#define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
595#define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
596#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
597#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
598#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
599#define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
600#define OMAP_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
587#endif /* _OMAP_COMMON_H_ */ 601#endif /* _OMAP_COMMON_H_ */