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authorAneesh V2011-06-16 18:30:47 -0500
committerAlbert ARIBAUD2011-07-04 03:55:25 -0500
commit2c451f7831208741d0ff7ca6046cffcd9ee49def (patch)
treeec885d6ce9bc97eca3128e83e9af35c5b063ffe1 /README
parent4c93da7c392737f2036130c240e2b4bea773d703 (diff)
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armv7: cache maintenance operations for armv7
- Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU - Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache - D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache - Add maintenance functions for TLB, branch predictor array etc. - Enable -march=armv7-a so that armv7 assembly instructions can be used Signed-off-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'README')
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diff --git a/README b/README
index a760cf3567..7ee16323d1 100644
--- a/README
+++ b/README
@@ -460,6 +460,11 @@ The following options need to be configured:
460 Note: If a "bootargs" environment is defined, it will overwride 460 Note: If a "bootargs" environment is defined, it will overwride
461 the defaults discussed just above. 461 the defaults discussed just above.
462 462
463- Cache Configuration:
464 CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot
465 CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot
466 CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
467
463- Serial Ports: 468- Serial Ports:
464 CONFIG_PL010_SERIAL 469 CONFIG_PL010_SERIAL
465 470