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authorTom Rini2012-09-25 14:23:55 -0500
committerTom Rini2012-09-25 14:23:55 -0500
commit5675b509165b67465a20e5cf71e07f40b449ef0c (patch)
tree9886f3e8fa8734ec9f8d9cb484fcaa87ff70203f /nand_spl
parentee1f4caaa2a3f79d692155eec8a4c7289d60e106 (diff)
parentd69dba367aed051663d0ee1ece013c8232bfa9f5 (diff)
downloadu-boot-5675b509165b67465a20e5cf71e07f40b449ef0c.tar.gz
u-boot-5675b509165b67465a20e5cf71e07f40b449ef0c.tar.xz
u-boot-5675b509165b67465a20e5cf71e07f40b449ef0c.zip
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'nand_spl')
-rw-r--r--nand_spl/board/freescale/common.c40
-rw-r--r--nand_spl/board/freescale/p1010rdb/Makefile6
-rw-r--r--nand_spl/board/freescale/p1010rdb/nand_boot.c77
-rw-r--r--nand_spl/board/freescale/p1023rds/Makefile6
-rw-r--r--nand_spl/board/freescale/p1023rds/nand_boot.c59
-rw-r--r--nand_spl/board/freescale/p1_p2_rdb_pc/Makefile6
-rw-r--r--nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c60
-rw-r--r--nand_spl/nand_boot_fsl_elbc.c47
8 files changed, 187 insertions, 114 deletions
diff --git a/nand_spl/board/freescale/common.c b/nand_spl/board/freescale/common.c
new file mode 100644
index 0000000000..0e099bc7c6
--- /dev/null
+++ b/nand_spl/board/freescale/common.c
@@ -0,0 +1,40 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Author: Matthew McClintock <msm@freescale.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 *
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 *
21 */
22
23#include <common.h>
24#include <asm/processor.h>
25#include <asm/global_data.h>
26
27DECLARE_GLOBAL_DATA_PTR;
28
29#ifndef CONFIG_SYS_FSL_TBCLK_DIV
30#define CONFIG_SYS_FSL_TBCLK_DIV 8
31#endif
32
33void udelay(unsigned long usec)
34{
35 u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
36 u32 ticks = ticks_per_usec * usec;
37 u32 s = mfspr(SPRN_TBRL);
38
39 while ((mfspr(SPRN_TBRL) - s) < ticks);
40}
diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile
index 8d240eadd9..cdbd49292c 100644
--- a/nand_spl/board/freescale/p1010rdb/Makefile
+++ b/nand_spl/board/freescale/p1010rdb/Makefile
@@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL
39 39
40SOBJS = start.o resetvec.o ticks.o 40SOBJS = start.o resetvec.o ticks.o
41COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ 41COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
42 nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o 42 nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o \
43 ../common.o
43 44
44SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) 45SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
45OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) 46OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -123,6 +124,9 @@ ifneq ($(OBJTREE), $(SRCTREE))
123$(obj)nand_boot.c: 124$(obj)nand_boot.c:
124 @rm -f $(obj)nand_boot.c 125 @rm -f $(obj)nand_boot.c
125 ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c 126 ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
127$(obj)../common.c:
128 @rm -f $(obj)../common.c
129 ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
126endif 130endif
127 131
128######################################################################### 132#########################################################################
diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c
index 16eeb61d85..9c356901b1 100644
--- a/nand_spl/board/freescale/p1010rdb/nand_boot.c
+++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c
@@ -27,51 +27,61 @@
27#include <asm/immap_85xx.h> 27#include <asm/immap_85xx.h>
28#include <asm/fsl_ddr_sdram.h> 28#include <asm/fsl_ddr_sdram.h>
29#include <asm/fsl_law.h> 29#include <asm/fsl_law.h>
30#include <asm/global_data.h>
30 31
31#define udelay(x) { int j; for (j = 0; j < x * 10000; j++) isync(); } 32DECLARE_GLOBAL_DATA_PTR;
32 33
33unsigned long ddr_freq_mhz; 34unsigned long ddr_freq_mhz;
34 35
35void sdram_init(void) 36void sdram_init(void)
36{ 37{
37 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; 38 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
39 /* mask off E bit */
40 u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
38 41
39 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE); 42 __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
40 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); 43 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
41 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); 44 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
42 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); 45 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
43 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); 46 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
44 47
45 if (ddr_freq_mhz < 700) { 48 if (ddr_freq_mhz < 700) {
46 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667); 49 __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
47 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667); 50 __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
48 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667); 51 __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
49 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667); 52 __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
50 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667); 53 __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
51 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667); 54 __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
52 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667); 55 __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
53 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667); 56 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
54 out_be32(&ddr->ddr_wrlvl_cntl, 57 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
55 CONFIG_SYS_DDR_WRLVL_CONTROL_667);
56 } else { 58 } else {
57 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800); 59 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
58 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800); 60 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
59 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800); 61 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
60 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800); 62 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
61 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800); 63 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
62 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800); 64 __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
63 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800); 65 __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
64 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800); 66 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
65 out_be32(&ddr->ddr_wrlvl_cntl, 67 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
66 CONFIG_SYS_DDR_WRLVL_CONTROL_800);
67 } 68 }
68 69
69 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); 70 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
70 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); 71 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
71 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); 72 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
73
74 /* P1014 and it's derivatives support max 16bit DDR width */
75 if (svr == SVR_P1014) {
76 __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
77 __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
78 /* For CS0_BNDS we divide the start and end address by 2, so we can just
79 * shift the entire register to achieve the desired result and the mask
80 * the value so we don't write reserved fields */
81 __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
82 }
72 83
73 /* mimic 500us delay, with busy isync() loop */ 84 udelay(500);
74 udelay(100);
75 85
76 /* Let the controller go */ 86 /* Let the controller go */
77 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); 87 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
@@ -82,20 +92,19 @@ void sdram_init(void)
82void board_init_f(ulong bootflag) 92void board_init_f(ulong bootflag)
83{ 93{
84 u32 plat_ratio, ddr_ratio; 94 u32 plat_ratio, ddr_ratio;
85 unsigned long bus_clk;
86 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 95 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
87 96
88 /* initialize selected port with appropriate baud rate */ 97 /* initialize selected port with appropriate baud rate */
89 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; 98 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
90 plat_ratio >>= 1; 99 plat_ratio >>= 1;
91 bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; 100 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
92 101
93 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; 102 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
94 ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; 103 ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
95 ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000; 104 ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
96 105
97 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 106 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
98 bus_clk / 16 / CONFIG_BAUDRATE); 107 gd->bus_clk / 16 / CONFIG_BAUDRATE);
99 108
100 puts("\nNAND boot... "); 109 puts("\nNAND boot... ");
101 110
diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile
index 168e868641..da435213fc 100644
--- a/nand_spl/board/freescale/p1023rds/Makefile
+++ b/nand_spl/board/freescale/p1023rds/Makefile
@@ -34,7 +34,8 @@ CFLAGS += -DCONFIG_NAND_SPL
34 34
35SOBJS = start.o resetvec.o 35SOBJS = start.o resetvec.o
36COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ 36COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
37 nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o 37 nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \
38 ../common.o
38 39
39SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) 40SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
40OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) 41OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -114,6 +115,9 @@ ifneq ($(OBJTREE), $(SRCTREE))
114$(obj)nand_boot.c: 115$(obj)nand_boot.c:
115 @rm -f $(obj)nand_boot.c 116 @rm -f $(obj)nand_boot.c
116 ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c 117 ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
118$(obj)../common.c:
119 @rm -f $(obj)../common.c
120 ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
117endif 121endif
118 122
119######################################################################### 123#########################################################################
diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c
index 0065c876de..89e339d512 100644
--- a/nand_spl/board/freescale/p1023rds/nand_boot.c
+++ b/nand_spl/board/freescale/p1023rds/nand_boot.c
@@ -25,6 +25,10 @@
25#include <asm/io.h> 25#include <asm/io.h>
26#include <nand.h> 26#include <nand.h>
27#include <asm/fsl_law.h> 27#include <asm/fsl_law.h>
28#include <asm/fsl_ddr_sdram.h>
29#include <asm/global_data.h>
30
31DECLARE_GLOBAL_DATA_PTR;
28 32
29/* Fixed sdram init -- doesn't use serial presence detect. */ 33/* Fixed sdram init -- doesn't use serial presence detect. */
30void sdram_init(void) 34void sdram_init(void)
@@ -33,40 +37,47 @@ void sdram_init(void)
33 37
34 set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); 38 set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
35 39
36 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); 40 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
37 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); 41 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
38 out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); 42 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
39 out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); 43 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
40 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 44 __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
41 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 45 __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
42 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 46 __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
43 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 47 __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
44 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2); 48 __raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2);
45 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); 49 __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
46 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); 50 __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
47 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); 51 __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
48 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); 52 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
49 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); 53 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
50 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); 54 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
51 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); 55 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
52 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); 56 __raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl);
53 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); 57 __raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl);
54 out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); 58 __raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1);
55 out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2); 59 __raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2);
56 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); 60 /* Set, but do not enable the memory */
61 __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
62
63 asm volatile("sync;isync");
64 udelay(500);
65
66 /* Let the controller go */
67 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
57} 68}
58 69
59void board_init_f(ulong bootflag) 70void board_init_f(ulong bootflag)
60{ 71{
61 u32 plat_ratio, bus_clk; 72 u32 plat_ratio;
62 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 73 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
63 74
64 /* initialize selected port with appropriate baud rate */ 75 /* initialize selected port with appropriate baud rate */
65 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; 76 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
66 plat_ratio >>= 1; 77 plat_ratio >>= 1;
67 bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; 78 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
68 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 79 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
69 bus_clk / 16 / CONFIG_BAUDRATE); 80 gd->bus_clk / 16 / CONFIG_BAUDRATE);
70 81
71 puts("\nNAND boot... "); 82 puts("\nNAND boot... ");
72 /* Initialize the DDR3 */ 83 /* Initialize the DDR3 */
diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
index 475cc496b3..46cf7099b6 100644
--- a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
@@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL
39 39
40SOBJS = start.o resetvec.o 40SOBJS = start.o resetvec.o
41COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ 41COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
42 nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o 42 nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \
43 ../common.o
43 44
44SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) 45SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
45OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) 46OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -119,6 +120,9 @@ ifneq ($(OBJTREE), $(SRCTREE))
119$(obj)nand_boot.c: 120$(obj)nand_boot.c:
120 @rm -f $(obj)nand_boot.c 121 @rm -f $(obj)nand_boot.c
121 ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c 122 ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
123$(obj)../common.c:
124 @rm -f $(obj)../common.c
125 ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
122endif 126endif
123 127
124######################################################################### 128#########################################################################
diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
index b9796ea6c9..4c140c1572 100644
--- a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
+++ b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
@@ -25,11 +25,9 @@
25#include <nand.h> 25#include <nand.h>
26#include <asm/fsl_law.h> 26#include <asm/fsl_law.h>
27#include <asm/fsl_ddr_sdram.h> 27#include <asm/fsl_ddr_sdram.h>
28#include <asm/global_data.h>
28 29
29#define udelay(x) {int i, j; \ 30DECLARE_GLOBAL_DATA_PTR;
30 for (i = 0; i < x; i++) \
31 for (j = 0; j < 10000; j++) \
32 ; }
33 31
34/* 32/*
35 * Fixed sdram init -- doesn't use serial presence detect. 33 * Fixed sdram init -- doesn't use serial presence detect.
@@ -38,32 +36,32 @@ void sdram_init(void)
38{ 36{
39 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; 37 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
40 38
41 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); 39 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
42 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); 40 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
43#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 41#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
44 out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); 42 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
45 out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); 43 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
46#endif 44#endif
47 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 45 __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
48 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 46 __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
49 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 47 __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
50 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 48 __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
51 49
52 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); 50 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
53 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); 51 __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
54 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); 52 __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
55 53
56 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); 54 __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
57 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); 55 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
58 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); 56 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
59 57
60 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); 58 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
61 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); 59 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
62 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); 60 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
63 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CONTROL); 61 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
64 62
65 /* Set, but do not enable the memory */ 63 /* Set, but do not enable the memory */
66 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN); 64 __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
67 65
68 asm volatile("sync;isync"); 66 asm volatile("sync;isync");
69 udelay(500); 67 udelay(500);
@@ -76,7 +74,7 @@ void sdram_init(void)
76 74
77void board_init_f(ulong bootflag) 75void board_init_f(ulong bootflag)
78{ 76{
79 u32 plat_ratio, bus_clk; 77 u32 plat_ratio;
80 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 78 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
81#ifndef CONFIG_QE 79#ifndef CONFIG_QE
82 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); 80 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
@@ -85,22 +83,22 @@ void board_init_f(ulong bootflag)
85 /* initialize selected port with appropriate baud rate */ 83 /* initialize selected port with appropriate baud rate */
86 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; 84 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
87 plat_ratio >>= 1; 85 plat_ratio >>= 1;
88 bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; 86 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
89 87
90 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 88 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
91 bus_clk / 16 / CONFIG_BAUDRATE); 89 gd->bus_clk / 16 / CONFIG_BAUDRATE);
92 90
93 puts("\nNAND boot... "); 91 puts("\nNAND boot... ");
94 92
95#ifndef CONFIG_QE 93#ifndef CONFIG_QE
96 /* init DDR3 reset signal */ 94 /* init DDR3 reset signal */
97 out_be32(&pgpio->gpdir, 0x02000000); 95 __raw_writel(0x02000000, &pgpio->gpdir);
98 out_be32(&pgpio->gpodr, 0x00200000); 96 __raw_writel(0x00200000, &pgpio->gpodr);
99 out_be32(&pgpio->gpdat, 0x00000000); 97 __raw_writel(0x00000000, &pgpio->gpdat);
100 udelay(1000); 98 udelay(1000);
101 out_be32(&pgpio->gpdat, 0x00200000); 99 __raw_writel(0x00200000, &pgpio->gpdat);
102 udelay(1000); 100 udelay(1000);
103 out_be32(&pgpio->gpdir, 0x00000000); 101 __raw_writel(0x00000000, &pgpio->gpdir);
104#endif 102#endif
105 103
106 /* Initialize the DDR3 */ 104 /* Initialize the DDR3 */
diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c
index 502605b1d5..e9d649743e 100644
--- a/nand_spl/nand_boot_fsl_elbc.c
+++ b/nand_spl/nand_boot_fsl_elbc.c
@@ -66,39 +66,42 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
66 66
67 if (large) { 67 if (large) {
68 fmr |= FMR_ECCM; 68 fmr |= FMR_ECCM;
69 out_be32(&regs->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | 69 __raw_writel((NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
70 (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); 70 (NAND_CMD_READSTART << FCR_CMD1_SHIFT),
71 out_be32(&regs->fir, 71 &regs->fcr);
72 (FIR_OP_CW0 << FIR_OP0_SHIFT) | 72 __raw_writel(
73 (FIR_OP_CA << FIR_OP1_SHIFT) | 73 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
74 (FIR_OP_PA << FIR_OP2_SHIFT) | 74 (FIR_OP_CA << FIR_OP1_SHIFT) |
75 (FIR_OP_CW1 << FIR_OP3_SHIFT) | 75 (FIR_OP_PA << FIR_OP2_SHIFT) |
76 (FIR_OP_RBW << FIR_OP4_SHIFT)); 76 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
77 (FIR_OP_RBW << FIR_OP4_SHIFT),
78 &regs->fir);
77 } else { 79 } else {
78 out_be32(&regs->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); 80 __raw_writel(NAND_CMD_READ0 << FCR_CMD0_SHIFT, &regs->fcr);
79 out_be32(&regs->fir, 81 __raw_writel(
80 (FIR_OP_CW0 << FIR_OP0_SHIFT) | 82 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
81 (FIR_OP_CA << FIR_OP1_SHIFT) | 83 (FIR_OP_CA << FIR_OP1_SHIFT) |
82 (FIR_OP_PA << FIR_OP2_SHIFT) | 84 (FIR_OP_PA << FIR_OP2_SHIFT) |
83 (FIR_OP_RBW << FIR_OP3_SHIFT)); 85 (FIR_OP_RBW << FIR_OP3_SHIFT),
86 &regs->fir);
84 } 87 }
85 88
86 out_be32(&regs->fbcr, 0); 89 __raw_writel(0, &regs->fbcr);
87 clrsetbits_be32(&regs->bank[0].br, BR_DECC, BR_DECC_CHK_GEN);
88 90
89 while (pos < uboot_size) { 91 while (pos < uboot_size) {
90 int i = 0; 92 int i = 0;
91 out_be32(&regs->fbar, offs >> block_shift); 93 __raw_writel(offs >> block_shift, &regs->fbar);
92 94
93 do { 95 do {
94 int j; 96 int j;
95 unsigned int page_offs = (offs & (block_size - 1)) << 1; 97 unsigned int page_offs = (offs & (block_size - 1)) << 1;
96 98
97 out_be32(&regs->ltesr, ~0); 99 __raw_writel(~0, &regs->ltesr);
98 out_be32(&regs->lteatr, 0); 100 __raw_writel(0, &regs->lteatr);
99 out_be32(&regs->fpar, page_offs); 101 __raw_writel(page_offs, &regs->fpar);
100 out_be32(&regs->fmr, fmr); 102 __raw_writel(fmr, &regs->fmr);
101 out_be32(&regs->lsor, 0); 103 sync();
104 __raw_writel(0, &regs->lsor);
102 nand_wait(); 105 nand_wait();
103 106
104 page_offs %= WINDOW_SIZE; 107 page_offs %= WINDOW_SIZE;
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