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authorMatthew McClintock2012-08-13 03:10:42 -0500
committerAndy Fleming2012-08-23 10:24:17 -0500
commitae6beb24d7589f1b8b7aa3519afb3c7cdf8e66e5 (patch)
tree52381b535873eb38846efb0f11f6315b9018705f /nand_spl
parent02ea538ce9fa8325f7d15c69cf87c950c5fe1f57 (diff)
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nand_spl: change out_be32 to raw_writel and depend on subsequent sync
This change reduces the SPL size by removing the redundant syncs produced by out_be32 and just replies on one final sync Done with: sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/` Signed-off-by: Matthew McClintock <msm@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'nand_spl')
-rw-r--r--nand_spl/board/freescale/p1010rdb/nand_boot.c54
-rw-r--r--nand_spl/board/freescale/p1023rds/nand_boot.c42
-rw-r--r--nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c48
3 files changed, 71 insertions, 73 deletions
diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c
index a0755098fe..9c356901b1 100644
--- a/nand_spl/board/freescale/p1010rdb/nand_boot.c
+++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c
@@ -39,39 +39,37 @@ void sdram_init(void)
39 /* mask off E bit */ 39 /* mask off E bit */
40 u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR)); 40 u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
41 41
42 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE); 42 __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
43 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); 43 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
44 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); 44 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
45 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); 45 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
46 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); 46 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
47 47
48 if (ddr_freq_mhz < 700) { 48 if (ddr_freq_mhz < 700) {
49 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667); 49 __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
50 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667); 50 __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
51 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667); 51 __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
52 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667); 52 __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
53 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667); 53 __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
54 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667); 54 __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
55 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667); 55 __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
56 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667); 56 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
57 out_be32(&ddr->ddr_wrlvl_cntl, 57 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
58 CONFIG_SYS_DDR_WRLVL_CONTROL_667);
59 } else { 58 } else {
60 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800); 59 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
61 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800); 60 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
62 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800); 61 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
63 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800); 62 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
64 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800); 63 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
65 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800); 64 __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
66 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800); 65 __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
67 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800); 66 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
68 out_be32(&ddr->ddr_wrlvl_cntl, 67 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
69 CONFIG_SYS_DDR_WRLVL_CONTROL_800);
70 } 68 }
71 69
72 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); 70 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
73 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); 71 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
74 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); 72 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
75 73
76 /* P1014 and it's derivatives support max 16bit DDR width */ 74 /* P1014 and it's derivatives support max 16bit DDR width */
77 if (svr == SVR_P1014) { 75 if (svr == SVR_P1014) {
diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c
index 6ab1f50378..89e339d512 100644
--- a/nand_spl/board/freescale/p1023rds/nand_boot.c
+++ b/nand_spl/board/freescale/p1023rds/nand_boot.c
@@ -37,28 +37,28 @@ void sdram_init(void)
37 37
38 set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); 38 set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
39 39
40 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); 40 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
41 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); 41 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
42 out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); 42 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
43 out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); 43 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
44 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 44 __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
45 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 45 __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
46 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 46 __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
47 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 47 __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
48 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2); 48 __raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2);
49 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); 49 __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
50 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); 50 __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
51 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); 51 __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
52 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); 52 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
53 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); 53 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
54 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); 54 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
55 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); 55 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
56 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); 56 __raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl);
57 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); 57 __raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl);
58 out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); 58 __raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1);
59 out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2); 59 __raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2);
60 /* Set, but do not enable the memory */ 60 /* Set, but do not enable the memory */
61 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN); 61 __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
62 62
63 asm volatile("sync;isync"); 63 asm volatile("sync;isync");
64 udelay(500); 64 udelay(500);
diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
index fcff382493..4c140c1572 100644
--- a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
+++ b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
@@ -36,32 +36,32 @@ void sdram_init(void)
36{ 36{
37 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; 37 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
38 38
39 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); 39 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
40 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); 40 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
41#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 41#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
42 out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); 42 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
43 out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); 43 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
44#endif 44#endif
45 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 45 __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
46 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 46 __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
47 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 47 __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
48 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 48 __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
49 49
50 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); 50 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
51 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); 51 __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
52 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); 52 __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
53 53
54 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); 54 __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
55 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); 55 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
56 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); 56 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
57 57
58 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); 58 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
59 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); 59 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
60 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); 60 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
61 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CONTROL); 61 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
62 62
63 /* Set, but do not enable the memory */ 63 /* Set, but do not enable the memory */
64 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN); 64 __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
65 65
66 asm volatile("sync;isync"); 66 asm volatile("sync;isync");
67 udelay(500); 67 udelay(500);
@@ -92,13 +92,13 @@ void board_init_f(ulong bootflag)
92 92
93#ifndef CONFIG_QE 93#ifndef CONFIG_QE
94 /* init DDR3 reset signal */ 94 /* init DDR3 reset signal */
95 out_be32(&pgpio->gpdir, 0x02000000); 95 __raw_writel(0x02000000, &pgpio->gpdir);
96 out_be32(&pgpio->gpodr, 0x00200000); 96 __raw_writel(0x00200000, &pgpio->gpodr);
97 out_be32(&pgpio->gpdat, 0x00000000); 97 __raw_writel(0x00000000, &pgpio->gpdat);
98 udelay(1000); 98 udelay(1000);
99 out_be32(&pgpio->gpdat, 0x00200000); 99 __raw_writel(0x00200000, &pgpio->gpdat);
100 udelay(1000); 100 udelay(1000);
101 out_be32(&pgpio->gpdir, 0x00000000); 101 __raw_writel(0x00000000, &pgpio->gpdir);
102#endif 102#endif
103 103
104 /* Initialize the DDR3 */ 104 /* Initialize the DDR3 */
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