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-rw-r--r--arch/arm/cpu/armv7/omap-common/emif-common.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index cdb4439721..11e830a533 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1075,6 +1075,11 @@ static void do_sdram_init(u32 base)
1075 else 1075 else
1076 ddr3_init(base, regs); 1076 ddr3_init(base, regs);
1077 } 1077 }
1078 if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
1079 set_lpmode_selfrefresh(base);
1080 emif_reset_phy(base);
1081 ddr3_leveling(base, regs);
1082 }
1078 1083
1079 /* Write to the shadow registers */ 1084 /* Write to the shadow registers */
1080 emif_update_timings(base, regs); 1085 emif_update_timings(base, regs);
@@ -1262,10 +1267,10 @@ void sdram_init(void)
1262 in_sdram = running_from_sdram(); 1267 in_sdram = running_from_sdram();
1263 debug("in_sdram = %d\n", in_sdram); 1268 debug("in_sdram = %d\n", in_sdram);
1264 1269
1265 if (!(in_sdram || warm_reset())) { 1270 if (!in_sdram) {
1266 if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) 1271 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1267 bypass_dpll((*prcm)->cm_clkmode_dpll_core); 1272 bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1268 else 1273 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1269 writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); 1274 writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1270 } 1275 }
1271 1276