diff options
-rw-r--r-- | arch/arm/cpu/armv7/omap-common/clocks-common.c | 58 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 10 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-omap5/clocks.h | 30 | ||||
-rw-r--r-- | arch/arm/include/asm/omap_common.h | 11 |
4 files changed, 97 insertions, 12 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 1861df4fa5..928327ab63 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c | |||
@@ -521,6 +521,38 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) | |||
521 | gpio_direction_output(pmic->gpio, 1); | 521 | gpio_direction_output(pmic->gpio, 1); |
522 | } | 522 | } |
523 | 523 | ||
524 | static u32 optimize_vcore_voltage(struct volts const *v) | ||
525 | { | ||
526 | u32 val; | ||
527 | if (!v->value) | ||
528 | return 0; | ||
529 | if (!v->efuse.reg) | ||
530 | return v->value; | ||
531 | |||
532 | switch (v->efuse.reg_bits) { | ||
533 | case 16: | ||
534 | val = readw(v->efuse.reg); | ||
535 | break; | ||
536 | case 32: | ||
537 | val = readl(v->efuse.reg); | ||
538 | break; | ||
539 | default: | ||
540 | printf("Error: efuse 0x%08x bits=%d unknown\n", | ||
541 | v->efuse.reg, v->efuse.reg_bits); | ||
542 | return v->value; | ||
543 | } | ||
544 | |||
545 | if (!val) { | ||
546 | printf("Error: efuse 0x%08x bits=%d val=0, using %d\n", | ||
547 | v->efuse.reg, v->efuse.reg_bits, v->value); | ||
548 | return v->value; | ||
549 | } | ||
550 | |||
551 | debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n", | ||
552 | __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val); | ||
553 | return val; | ||
554 | } | ||
555 | |||
524 | /* | 556 | /* |
525 | * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva | 557 | * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva |
526 | * We set the maximum voltages allowed here because Smart-Reflex is not | 558 | * We set the maximum voltages allowed here because Smart-Reflex is not |
@@ -529,23 +561,25 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) | |||
529 | */ | 561 | */ |
530 | void scale_vcores(struct vcores_data const *vcores) | 562 | void scale_vcores(struct vcores_data const *vcores) |
531 | { | 563 | { |
532 | do_scale_vcore(vcores->core.addr, vcores->core.value, | 564 | u32 val; |
533 | vcores->core.pmic); | 565 | |
566 | val = optimize_vcore_voltage(&vcores->core); | ||
567 | do_scale_vcore(vcores->core.addr, val, vcores->core.pmic); | ||
534 | 568 | ||
535 | do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, | 569 | val = optimize_vcore_voltage(&vcores->mpu); |
536 | vcores->mpu.pmic); | 570 | do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic); |
537 | 571 | ||
538 | do_scale_vcore(vcores->mm.addr, vcores->mm.value, | 572 | val = optimize_vcore_voltage(&vcores->mm); |
539 | vcores->mm.pmic); | 573 | do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic); |
540 | 574 | ||
541 | do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, | 575 | val = optimize_vcore_voltage(&vcores->gpu); |
542 | vcores->gpu.pmic); | 576 | do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic); |
543 | 577 | ||
544 | do_scale_vcore(vcores->eve.addr, vcores->eve.value, | 578 | val = optimize_vcore_voltage(&vcores->eve); |
545 | vcores->eve.pmic); | 579 | do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic); |
546 | 580 | ||
547 | do_scale_vcore(vcores->iva.addr, vcores->iva.value, | 581 | val = optimize_vcore_voltage(&vcores->iva); |
548 | vcores->iva.pmic); | 582 | do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic); |
549 | 583 | ||
550 | if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { | 584 | if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { |
551 | /* Configure LDO SRAM "magic" bits */ | 585 | /* Configure LDO SRAM "magic" bits */ |
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index e9d34c13b1..53aea93077 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c | |||
@@ -338,22 +338,32 @@ struct vcores_data omap5430_volts_es2 = { | |||
338 | 338 | ||
339 | struct vcores_data dra752_volts = { | 339 | struct vcores_data dra752_volts = { |
340 | .mpu.value = VDD_MPU_DRA752, | 340 | .mpu.value = VDD_MPU_DRA752, |
341 | .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, | ||
342 | .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, | ||
341 | .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU, | 343 | .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU, |
342 | .mpu.pmic = &tps659038, | 344 | .mpu.pmic = &tps659038, |
343 | 345 | ||
344 | .eve.value = VDD_EVE_DRA752, | 346 | .eve.value = VDD_EVE_DRA752, |
347 | .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, | ||
348 | .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, | ||
345 | .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE, | 349 | .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE, |
346 | .eve.pmic = &tps659038, | 350 | .eve.pmic = &tps659038, |
347 | 351 | ||
348 | .gpu.value = VDD_GPU_DRA752, | 352 | .gpu.value = VDD_GPU_DRA752, |
353 | .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, | ||
354 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, | ||
349 | .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU, | 355 | .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU, |
350 | .gpu.pmic = &tps659038, | 356 | .gpu.pmic = &tps659038, |
351 | 357 | ||
352 | .core.value = VDD_CORE_DRA752, | 358 | .core.value = VDD_CORE_DRA752, |
359 | .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, | ||
360 | .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, | ||
353 | .core.addr = TPS659038_REG_ADDR_SMPS7_CORE, | 361 | .core.addr = TPS659038_REG_ADDR_SMPS7_CORE, |
354 | .core.pmic = &tps659038, | 362 | .core.pmic = &tps659038, |
355 | 363 | ||
356 | .iva.value = VDD_IVA_DRA752, | 364 | .iva.value = VDD_IVA_DRA752, |
365 | .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, | ||
366 | .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, | ||
357 | .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA, | 367 | .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA, |
358 | .iva.pmic = &tps659038, | 368 | .iva.pmic = &tps659038, |
359 | }; | 369 | }; |
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index b43737ed42..cfcf51d0f9 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h | |||
@@ -219,6 +219,36 @@ | |||
219 | #define VDD_CORE_DRA752 1030 | 219 | #define VDD_CORE_DRA752 1030 |
220 | #define VDD_IVA_DRA752 1060 | 220 | #define VDD_IVA_DRA752 1060 |
221 | 221 | ||
222 | /* Efuse register offsets for DRA7xx platform */ | ||
223 | #define DRA752_EFUSE_BASE 0x4A002000 | ||
224 | #define DRA752_EFUSE_REGBITS 16 | ||
225 | /* STD_FUSE_OPP_VMIN_IVA_2 */ | ||
226 | #define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC) | ||
227 | /* STD_FUSE_OPP_VMIN_IVA_3 */ | ||
228 | #define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0) | ||
229 | /* STD_FUSE_OPP_VMIN_IVA_4 */ | ||
230 | #define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4) | ||
231 | /* STD_FUSE_OPP_VMIN_DSPEVE_2 */ | ||
232 | #define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0) | ||
233 | /* STD_FUSE_OPP_VMIN_DSPEVE_3 */ | ||
234 | #define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4) | ||
235 | /* STD_FUSE_OPP_VMIN_DSPEVE_4 */ | ||
236 | #define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8) | ||
237 | /* STD_FUSE_OPP_VMIN_CORE_2 */ | ||
238 | #define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4) | ||
239 | /* STD_FUSE_OPP_VMIN_GPU_2 */ | ||
240 | #define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08) | ||
241 | /* STD_FUSE_OPP_VMIN_GPU_3 */ | ||
242 | #define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) | ||
243 | /* STD_FUSE_OPP_VMIN_GPU_4 */ | ||
244 | #define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) | ||
245 | /* STD_FUSE_OPP_VMIN_MPU_2 */ | ||
246 | #define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) | ||
247 | /* STD_FUSE_OPP_VMIN_MPU_3 */ | ||
248 | #define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24) | ||
249 | /* STD_FUSE_OPP_VMIN_MPU_4 */ | ||
250 | #define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) | ||
251 | |||
222 | /* Standard offset is 0.5v expressed in uv */ | 252 | /* Standard offset is 0.5v expressed in uv */ |
223 | #define PALMAS_SMPS_BASE_VOLT_UV 500000 | 253 | #define PALMAS_SMPS_BASE_VOLT_UV 500000 |
224 | 254 | ||
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 6b28f2e3f7..14356742d2 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h | |||
@@ -500,9 +500,20 @@ struct pmic_data { | |||
500 | int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); | 500 | int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); |
501 | }; | 501 | }; |
502 | 502 | ||
503 | /** | ||
504 | * struct volts_efuse_data - efuse definition for voltage | ||
505 | * @reg: register address for efuse | ||
506 | * @reg_bits: Number of bits in a register address, mandatory. | ||
507 | */ | ||
508 | struct volts_efuse_data { | ||
509 | u32 reg; | ||
510 | u8 reg_bits; | ||
511 | }; | ||
512 | |||
503 | struct volts { | 513 | struct volts { |
504 | u32 value; | 514 | u32 value; |
505 | u32 addr; | 515 | u32 addr; |
516 | struct volts_efuse_data efuse; | ||
506 | struct pmic_data *pmic; | 517 | struct pmic_data *pmic; |
507 | }; | 518 | }; |
508 | 519 | ||