diff options
-rw-r--r-- | arch/arm/cpu/armv7/omap-common/emif-common.c | 26 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 21 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap5/hwinit.c | 19 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap5/sdram.c | 170 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-omap5/omap.h | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/emif.h | 12 | ||||
-rw-r--r-- | arch/arm/include/asm/omap_common.h | 1 |
8 files changed, 220 insertions, 31 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 11e830a533..f925e82d41 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c | |||
@@ -209,7 +209,8 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) | |||
209 | writel(regs->temp_alert_config, &emif->emif_temp_alert_config); | 209 | writel(regs->temp_alert_config, &emif->emif_temp_alert_config); |
210 | writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); | 210 | writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); |
211 | 211 | ||
212 | if (omap_revision() >= OMAP5430_ES1_0) { | 212 | if ((omap_revision() >= OMAP5430_ES1_0) || |
213 | (omap_revision() == DRA752_ES1_0)) { | ||
213 | writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, | 214 | writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, |
214 | &emif->emif_l3_config); | 215 | &emif->emif_l3_config); |
215 | } else if (omap_revision() >= OMAP4460_ES1_0) { | 216 | } else if (omap_revision() >= OMAP4460_ES1_0) { |
@@ -263,6 +264,18 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs) | |||
263 | __udelay(130); | 264 | __udelay(130); |
264 | } | 265 | } |
265 | 266 | ||
267 | static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs) | ||
268 | { | ||
269 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | ||
270 | |||
271 | writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); | ||
272 | writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); | ||
273 | config_data_eye_leveling_samples(base); | ||
274 | |||
275 | writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); | ||
276 | writel(regs->sdram_config, &emif->emif_sdram_config); | ||
277 | } | ||
278 | |||
266 | static void ddr3_init(u32 base, const struct emif_regs *regs) | 279 | static void ddr3_init(u32 base, const struct emif_regs *regs) |
267 | { | 280 | { |
268 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | 281 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
@@ -273,6 +286,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) | |||
273 | * defined, contents of mode Registers must be fully initialized. | 286 | * defined, contents of mode Registers must be fully initialized. |
274 | * H/W takes care of this initialization | 287 | * H/W takes care of this initialization |
275 | */ | 288 | */ |
289 | writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); | ||
276 | writel(regs->sdram_config_init, &emif->emif_sdram_config); | 290 | writel(regs->sdram_config_init, &emif->emif_sdram_config); |
277 | 291 | ||
278 | writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); | 292 | writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); |
@@ -290,7 +304,10 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) | |||
290 | /* enable leveling */ | 304 | /* enable leveling */ |
291 | writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); | 305 | writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); |
292 | 306 | ||
293 | ddr3_leveling(base, regs); | 307 | if (omap_revision() == DRA752_ES1_0) |
308 | ddr3_sw_leveling(base, regs); | ||
309 | else | ||
310 | ddr3_leveling(base, regs); | ||
294 | } | 311 | } |
295 | 312 | ||
296 | #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS | 313 | #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
@@ -1078,7 +1095,10 @@ static void do_sdram_init(u32 base) | |||
1078 | if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) { | 1095 | if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) { |
1079 | set_lpmode_selfrefresh(base); | 1096 | set_lpmode_selfrefresh(base); |
1080 | emif_reset_phy(base); | 1097 | emif_reset_phy(base); |
1081 | ddr3_leveling(base, regs); | 1098 | if (omap_revision() == DRA752_ES1_0) |
1099 | ddr3_sw_leveling(base, regs); | ||
1100 | else | ||
1101 | ddr3_leveling(base, regs); | ||
1082 | } | 1102 | } |
1083 | 1103 | ||
1084 | /* Write to the shadow registers */ | 1104 | /* Write to the shadow registers */ |
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 83033907d9..9374c6a82e 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c | |||
@@ -602,6 +602,17 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = { | |||
602 | .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, | 602 | .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, |
603 | }; | 603 | }; |
604 | 604 | ||
605 | const struct ctrl_ioregs ioregs_dra7xx_es1 = { | ||
606 | .ctrl_ddrch = 0x40404040, | ||
607 | .ctrl_lpddr2ch = 0x40404040, | ||
608 | .ctrl_ddr3ch = 0x80808080, | ||
609 | .ctrl_ddrio_0 = 0xbae8c631, | ||
610 | .ctrl_ddrio_1 = 0xb46318d8, | ||
611 | .ctrl_ddrio_2 = 0x84210000, | ||
612 | .ctrl_emif_sdram_config_ext = 0xb2c00000, | ||
613 | .ctrl_ddr_ctrl_ext_0 = 0xA2000000, | ||
614 | }; | ||
615 | |||
605 | void hw_data_init(void) | 616 | void hw_data_init(void) |
606 | { | 617 | { |
607 | u32 omap_rev = omap_revision(); | 618 | u32 omap_rev = omap_revision(); |
@@ -644,14 +655,16 @@ void get_ioregs(const struct ctrl_ioregs **regs) | |||
644 | case OMAP5430_ES1_0: | 655 | case OMAP5430_ES1_0: |
645 | case OMAP5430_ES2_0: | 656 | case OMAP5430_ES2_0: |
646 | *regs = &ioregs_omap5430; | 657 | *regs = &ioregs_omap5430; |
647 | break; | 658 | break; |
648 | case OMAP5432_ES1_0: | 659 | case OMAP5432_ES1_0: |
649 | *regs = &ioregs_omap5432_es1; | 660 | *regs = &ioregs_omap5432_es1; |
650 | break; | 661 | break; |
651 | case OMAP5432_ES2_0: | 662 | case OMAP5432_ES2_0: |
652 | case DRA752_ES1_0: | ||
653 | *regs = &ioregs_omap5432_es2; | 663 | *regs = &ioregs_omap5432_es2; |
654 | break; | 664 | break; |
665 | case DRA752_ES1_0: | ||
666 | *regs = &ioregs_dra7xx_es1; | ||
667 | break; | ||
655 | 668 | ||
656 | default: | 669 | default: |
657 | printf("\n INVALID OMAP REVISION "); | 670 | printf("\n INVALID OMAP REVISION "); |
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 784aa11933..50a938cf51 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c | |||
@@ -100,16 +100,21 @@ static void io_settings_ddr3(void) | |||
100 | writel(ioregs->ctrl_emif_sdram_config_ext, | 100 | writel(ioregs->ctrl_emif_sdram_config_ext, |
101 | (*ctrl)->control_emif2_sdram_config_ext); | 101 | (*ctrl)->control_emif2_sdram_config_ext); |
102 | 102 | ||
103 | /* Disable DLL select */ | 103 | if (is_omap54xx()) { |
104 | io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) | 104 | /* Disable DLL select */ |
105 | io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) | ||
105 | & 0xFFEFFFFF); | 106 | & 0xFFEFFFFF); |
106 | writel(io_settings, | 107 | writel(io_settings, |
107 | (*ctrl)->control_port_emif1_sdram_config); | 108 | (*ctrl)->control_port_emif1_sdram_config); |
108 | 109 | ||
109 | io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) | 110 | io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) |
110 | & 0xFFEFFFFF); | 111 | & 0xFFEFFFFF); |
111 | writel(io_settings, | 112 | writel(io_settings, |
112 | (*ctrl)->control_port_emif2_sdram_config); | 113 | (*ctrl)->control_port_emif2_sdram_config); |
114 | } else { | ||
115 | writel(ioregs->ctrl_ddr_ctrl_ext_0, | ||
116 | (*ctrl)->control_ddr_control_ext_0); | ||
117 | } | ||
113 | } | 118 | } |
114 | 119 | ||
115 | /* | 120 | /* |
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index fdf204fd71..331117c35c 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c | |||
@@ -436,6 +436,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { | |||
436 | .control_srcomp_east_side = 0x4A002E7C, | 436 | .control_srcomp_east_side = 0x4A002E7C, |
437 | .control_srcomp_west_side = 0x4A002E80, | 437 | .control_srcomp_west_side = 0x4A002E80, |
438 | .control_srcomp_code_latch = 0x4A002E84, | 438 | .control_srcomp_code_latch = 0x4A002E84, |
439 | .control_ddr_control_ext_0 = 0x4A002E88, | ||
439 | .control_padconf_core_base = 0x4A003400, | 440 | .control_padconf_core_base = 0x4A003400, |
440 | .control_port_emif1_sdram_config = 0x4AE0C110, | 441 | .control_port_emif1_sdram_config = 0x4AE0C110, |
441 | .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, | 442 | .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, |
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 6b461e4846..1b445a61eb 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c | |||
@@ -108,6 +108,7 @@ const struct emif_regs emif_regs_266_mhz_2cs = { | |||
108 | const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { | 108 | const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { |
109 | .sdram_config_init = 0x61851B32, | 109 | .sdram_config_init = 0x61851B32, |
110 | .sdram_config = 0x61851B32, | 110 | .sdram_config = 0x61851B32, |
111 | .sdram_config2 = 0x0, | ||
111 | .ref_ctrl = 0x00001035, | 112 | .ref_ctrl = 0x00001035, |
112 | .sdram_tim1 = 0xCCCF36B3, | 113 | .sdram_tim1 = 0xCCCF36B3, |
113 | .sdram_tim2 = 0x308F7FDA, | 114 | .sdram_tim2 = 0x308F7FDA, |
@@ -131,6 +132,7 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { | |||
131 | const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { | 132 | const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { |
132 | .sdram_config_init = 0x61851B32, | 133 | .sdram_config_init = 0x61851B32, |
133 | .sdram_config = 0x61851B32, | 134 | .sdram_config = 0x61851B32, |
135 | .sdram_config2 = 0x0, | ||
134 | .ref_ctrl = 0x00001035, | 136 | .ref_ctrl = 0x00001035, |
135 | .sdram_tim1 = 0xCCCF36B3, | 137 | .sdram_tim1 = 0xCCCF36B3, |
136 | .sdram_tim2 = 0x308F7FDA, | 138 | .sdram_tim2 = 0x308F7FDA, |
@@ -151,6 +153,54 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { | |||
151 | .emif_rd_wr_exec_thresh = 0x40000305 | 153 | .emif_rd_wr_exec_thresh = 0x40000305 |
152 | }; | 154 | }; |
153 | 155 | ||
156 | const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { | ||
157 | .sdram_config_init = 0x61851ab2, | ||
158 | .sdram_config = 0x61851ab2, | ||
159 | .sdram_config2 = 0x08000000, | ||
160 | .ref_ctrl = 0x00001035, | ||
161 | .sdram_tim1 = 0xCCCF36B3, | ||
162 | .sdram_tim2 = 0x308F7FDA, | ||
163 | .sdram_tim3 = 0x027F88A8, | ||
164 | .read_idle_ctrl = 0x00050000, | ||
165 | .zq_config = 0x0007190B, | ||
166 | .temp_alert_config = 0x00000000, | ||
167 | .emif_ddr_phy_ctlr_1_init = 0x0E20400A, | ||
168 | .emif_ddr_phy_ctlr_1 = 0x0E24400A, | ||
169 | .emif_ddr_ext_phy_ctrl_1 = 0x04040100, | ||
170 | .emif_ddr_ext_phy_ctrl_2 = 0x009E009E, | ||
171 | .emif_ddr_ext_phy_ctrl_3 = 0x009E009E, | ||
172 | .emif_ddr_ext_phy_ctrl_4 = 0x009E009E, | ||
173 | .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, | ||
174 | .emif_rd_wr_lvl_rmp_win = 0x00000000, | ||
175 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, | ||
176 | .emif_rd_wr_lvl_ctl = 0x00000000, | ||
177 | .emif_rd_wr_exec_thresh = 0x00000305 | ||
178 | }; | ||
179 | |||
180 | const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { | ||
181 | .sdram_config_init = 0x61851B32, | ||
182 | .sdram_config = 0x61851B32, | ||
183 | .sdram_config2 = 0x08000000, | ||
184 | .ref_ctrl = 0x00001035, | ||
185 | .sdram_tim1 = 0xCCCF36B3, | ||
186 | .sdram_tim2 = 0x308F7FDA, | ||
187 | .sdram_tim3 = 0x027F88A8, | ||
188 | .read_idle_ctrl = 0x00050000, | ||
189 | .zq_config = 0x0007190B, | ||
190 | .temp_alert_config = 0x00000000, | ||
191 | .emif_ddr_phy_ctlr_1_init = 0x0020400A, | ||
192 | .emif_ddr_phy_ctlr_1 = 0x0E24400A, | ||
193 | .emif_ddr_ext_phy_ctrl_1 = 0x04040100, | ||
194 | .emif_ddr_ext_phy_ctrl_2 = 0x009D009D, | ||
195 | .emif_ddr_ext_phy_ctrl_3 = 0x009D009D, | ||
196 | .emif_ddr_ext_phy_ctrl_4 = 0x009D009D, | ||
197 | .emif_ddr_ext_phy_ctrl_5 = 0x009D009D, | ||
198 | .emif_rd_wr_lvl_rmp_win = 0x00000000, | ||
199 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, | ||
200 | .emif_rd_wr_lvl_ctl = 0x00000000, | ||
201 | .emif_rd_wr_exec_thresh = 0x00000305 | ||
202 | }; | ||
203 | |||
154 | const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { | 204 | const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { |
155 | .dmm_lisa_map_0 = 0x0, | 205 | .dmm_lisa_map_0 = 0x0, |
156 | .dmm_lisa_map_1 = 0x0, | 206 | .dmm_lisa_map_1 = 0x0, |
@@ -159,11 +209,39 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { | |||
159 | .is_ma_present = 0x1 | 209 | .is_ma_present = 0x1 |
160 | }; | 210 | }; |
161 | 211 | ||
162 | const struct dmm_lisa_map_regs lisa_map_512M_x_1 = { | 212 | /* |
213 | * DRA752 EVM board has 1.5 GB of memory | ||
214 | * EMIF1 --> 2Gb * 2 = 512MB | ||
215 | * EMIF2 --> 2Gb * 4 = 1GB | ||
216 | * so mapping 1GB interleaved and 512MB non-interleaved | ||
217 | */ | ||
218 | const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = { | ||
219 | .dmm_lisa_map_0 = 0x0, | ||
220 | .dmm_lisa_map_1 = 0x80640300, | ||
221 | .dmm_lisa_map_2 = 0xC0500220, | ||
222 | .dmm_lisa_map_3 = 0xFF020100, | ||
223 | .is_ma_present = 0x1 | ||
224 | }; | ||
225 | |||
226 | /* | ||
227 | * DRA752 EVM EMIF1 ONLY CONFIGURATION | ||
228 | */ | ||
229 | const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { | ||
163 | .dmm_lisa_map_0 = 0x0, | 230 | .dmm_lisa_map_0 = 0x0, |
164 | .dmm_lisa_map_1 = 0x0, | 231 | .dmm_lisa_map_1 = 0x0, |
165 | .dmm_lisa_map_2 = 0x0, | 232 | .dmm_lisa_map_2 = 0x80500100, |
166 | .dmm_lisa_map_3 = 0x80500100, | 233 | .dmm_lisa_map_3 = 0xFF020100, |
234 | .is_ma_present = 0x1 | ||
235 | }; | ||
236 | |||
237 | /* | ||
238 | * DRA752 EVM EMIF2 ONLY CONFIGURATION | ||
239 | */ | ||
240 | const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { | ||
241 | .dmm_lisa_map_0 = 0x0, | ||
242 | .dmm_lisa_map_1 = 0x0, | ||
243 | .dmm_lisa_map_2 = 0x80600200, | ||
244 | .dmm_lisa_map_3 = 0xFF020100, | ||
167 | .is_ma_present = 0x1 | 245 | .is_ma_present = 0x1 |
168 | }; | 246 | }; |
169 | 247 | ||
@@ -180,9 +258,20 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) | |||
180 | *regs = &emif_regs_532_mhz_2cs_es2; | 258 | *regs = &emif_regs_532_mhz_2cs_es2; |
181 | break; | 259 | break; |
182 | case OMAP5432_ES2_0: | 260 | case OMAP5432_ES2_0: |
261 | *regs = &emif_regs_ddr3_532_mhz_1cs_es2; | ||
262 | break; | ||
183 | case DRA752_ES1_0: | 263 | case DRA752_ES1_0: |
264 | switch (emif_nr) { | ||
265 | case 1: | ||
266 | *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; | ||
267 | break; | ||
268 | case 2: | ||
269 | *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1; | ||
270 | break; | ||
271 | } | ||
272 | break; | ||
184 | default: | 273 | default: |
185 | *regs = &emif_regs_ddr3_532_mhz_1cs_es2; | 274 | *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; |
186 | } | 275 | } |
187 | } | 276 | } |
188 | 277 | ||
@@ -201,7 +290,7 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs | |||
201 | break; | 290 | break; |
202 | case DRA752_ES1_0: | 291 | case DRA752_ES1_0: |
203 | default: | 292 | default: |
204 | *dmm_lisa_regs = &lisa_map_512M_x_1; | 293 | *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2; |
205 | } | 294 | } |
206 | 295 | ||
207 | } | 296 | } |
@@ -252,7 +341,8 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { | |||
252 | 0x00000000, | 341 | 0x00000000, |
253 | 0x00000000, | 342 | 0x00000000, |
254 | 0x00000000, | 343 | 0x00000000, |
255 | 0x00000077 | 344 | 0x00000077, |
345 | 0x0 | ||
256 | }; | 346 | }; |
257 | 347 | ||
258 | const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { | 348 | const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { |
@@ -274,7 +364,8 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { | |||
274 | 0x00000000, | 364 | 0x00000000, |
275 | 0x00000000, | 365 | 0x00000000, |
276 | 0x00000000, | 366 | 0x00000000, |
277 | 0x00000057 | 367 | 0x00000057, |
368 | 0x0 | ||
278 | }; | 369 | }; |
279 | 370 | ||
280 | const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { | 371 | const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { |
@@ -296,7 +387,56 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { | |||
296 | 0x00000000, | 387 | 0x00000000, |
297 | 0x00000000, | 388 | 0x00000000, |
298 | 0x00000000, | 389 | 0x00000000, |
299 | 0x00000057 | 390 | 0x00000057, |
391 | 0x0 | ||
392 | }; | ||
393 | |||
394 | const u32 | ||
395 | dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = { | ||
396 | 0x009E009E, | ||
397 | 0x002E002E, | ||
398 | 0x002E002E, | ||
399 | 0x002E002E, | ||
400 | 0x002E002E, | ||
401 | 0x002E002E, | ||
402 | 0x004D004D, | ||
403 | 0x004D004D, | ||
404 | 0x004D004D, | ||
405 | 0x004D004D, | ||
406 | 0x004D004D, | ||
407 | 0x004D004D, | ||
408 | 0x004D004D, | ||
409 | 0x004D004D, | ||
410 | 0x004D004D, | ||
411 | 0x004D004D, | ||
412 | 0x0, | ||
413 | 0x600020, | ||
414 | 0x40010080, | ||
415 | 0x8102040 | ||
416 | }; | ||
417 | |||
418 | const u32 | ||
419 | dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = { | ||
420 | 0x009D009D, | ||
421 | 0x002D002D, | ||
422 | 0x002D002D, | ||
423 | 0x002D002D, | ||
424 | 0x002D002D, | ||
425 | 0x002D002D, | ||
426 | 0x00570057, | ||
427 | 0x00570057, | ||
428 | 0x00570057, | ||
429 | 0x00570057, | ||
430 | 0x00570057, | ||
431 | 0x00570057, | ||
432 | 0x00570057, | ||
433 | 0x00570057, | ||
434 | 0x00570057, | ||
435 | 0x00570057, | ||
436 | 0x0, | ||
437 | 0x600020, | ||
438 | 0x40010080, | ||
439 | 0x8102040 | ||
300 | }; | 440 | }; |
301 | 441 | ||
302 | const struct lpddr2_mr_regs mr_regs = { | 442 | const struct lpddr2_mr_regs mr_regs = { |
@@ -307,7 +447,7 @@ const struct lpddr2_mr_regs mr_regs = { | |||
307 | .mr16 = MR16_REF_FULL_ARRAY | 447 | .mr16 = MR16_REF_FULL_ARRAY |
308 | }; | 448 | }; |
309 | 449 | ||
310 | static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) | 450 | static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs) |
311 | { | 451 | { |
312 | switch (omap_revision()) { | 452 | switch (omap_revision()) { |
313 | case OMAP5430_ES1_0: | 453 | case OMAP5430_ES1_0: |
@@ -318,7 +458,14 @@ static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) | |||
318 | *regs = ddr3_ext_phy_ctrl_const_base_es1; | 458 | *regs = ddr3_ext_phy_ctrl_const_base_es1; |
319 | break; | 459 | break; |
320 | case OMAP5432_ES2_0: | 460 | case OMAP5432_ES2_0: |
461 | *regs = ddr3_ext_phy_ctrl_const_base_es2; | ||
462 | break; | ||
321 | case DRA752_ES1_0: | 463 | case DRA752_ES1_0: |
464 | if (emif_nr == 1) | ||
465 | *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; | ||
466 | else | ||
467 | *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2; | ||
468 | break; | ||
322 | default: | 469 | default: |
323 | *regs = ddr3_ext_phy_ctrl_const_base_es2; | 470 | *regs = ddr3_ext_phy_ctrl_const_base_es2; |
324 | 471 | ||
@@ -334,9 +481,12 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) | |||
334 | { | 481 | { |
335 | u32 *ext_phy_ctrl_base = 0; | 482 | u32 *ext_phy_ctrl_base = 0; |
336 | u32 *emif_ext_phy_ctrl_base = 0; | 483 | u32 *emif_ext_phy_ctrl_base = 0; |
484 | u32 emif_nr; | ||
337 | const u32 *ext_phy_ctrl_const_regs; | 485 | const u32 *ext_phy_ctrl_const_regs; |
338 | u32 i = 0; | 486 | u32 i = 0; |
339 | 487 | ||
488 | emif_nr = (base == EMIF1_BASE) ? 1 : 2; | ||
489 | |||
340 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | 490 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
341 | 491 | ||
342 | ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); | 492 | ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); |
@@ -353,7 +503,7 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) | |||
353 | * external phy 6-24 registers do not change with | 503 | * external phy 6-24 registers do not change with |
354 | * ddr frequency | 504 | * ddr frequency |
355 | */ | 505 | */ |
356 | emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs); | 506 | emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs); |
357 | for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { | 507 | for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { |
358 | writel(ext_phy_ctrl_const_regs[i], | 508 | writel(ext_phy_ctrl_const_regs[i], |
359 | emif_ext_phy_ctrl_base++); | 509 | emif_ext_phy_ctrl_base++); |
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 63378fb10c..e7d79fc3c4 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h | |||
@@ -191,6 +191,7 @@ struct ctrl_ioregs { | |||
191 | u32 ctrl_ddrio_1; | 191 | u32 ctrl_ddrio_1; |
192 | u32 ctrl_ddrio_2; | 192 | u32 ctrl_ddrio_2; |
193 | u32 ctrl_emif_sdram_config_ext; | 193 | u32 ctrl_emif_sdram_config_ext; |
194 | u32 ctrl_ddr_ctrl_ext_0; | ||
194 | }; | 195 | }; |
195 | #endif /* __ASSEMBLY__ */ | 196 | #endif /* __ASSEMBLY__ */ |
196 | #endif | 197 | #endif |
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 5f11d7b72e..1b94a99c54 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h | |||
@@ -581,7 +581,7 @@ | |||
581 | (0xFF << EMIF_SYS_ADDR_SHIFT)) | 581 | (0xFF << EMIF_SYS_ADDR_SHIFT)) |
582 | 582 | ||
583 | #define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 | 583 | #define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 |
584 | #define EMIF_EXT_PHY_CTRL_CONST_REG 0x13 | 584 | #define EMIF_EXT_PHY_CTRL_CONST_REG 0x14 |
585 | 585 | ||
586 | /* Reg mapping structure */ | 586 | /* Reg mapping structure */ |
587 | struct emif_reg_struct { | 587 | struct emif_reg_struct { |
@@ -855,13 +855,10 @@ struct dmm_lisa_map_regs { | |||
855 | #define DPD_ENABLE 1 | 855 | #define DPD_ENABLE 1 |
856 | 856 | ||
857 | /* Maximum delay before Low Power Modes */ | 857 | /* Maximum delay before Low Power Modes */ |
858 | #ifndef CONFIG_OMAP54XX | ||
859 | #define REG_CS_TIM 0xF | ||
860 | #else | ||
861 | #define REG_CS_TIM 0x0 | 858 | #define REG_CS_TIM 0x0 |
862 | #endif | 859 | #define REG_SR_TIM 0x0 |
863 | #define REG_SR_TIM 0xF | 860 | #define REG_PD_TIM 0x0 |
864 | #define REG_PD_TIM 0xF | 861 | |
865 | 862 | ||
866 | /* EMIF_PWR_MGMT_CTRL register */ | 863 | /* EMIF_PWR_MGMT_CTRL register */ |
867 | #define EMIF_PWR_MGMT_CTRL (\ | 864 | #define EMIF_PWR_MGMT_CTRL (\ |
@@ -1113,6 +1110,7 @@ struct emif_regs { | |||
1113 | u32 freq; | 1110 | u32 freq; |
1114 | u32 sdram_config_init; | 1111 | u32 sdram_config_init; |
1115 | u32 sdram_config; | 1112 | u32 sdram_config; |
1113 | u32 sdram_config2; | ||
1116 | u32 ref_ctrl; | 1114 | u32 ref_ctrl; |
1117 | u32 sdram_tim1; | 1115 | u32 sdram_tim1; |
1118 | u32 sdram_tim2; | 1116 | u32 sdram_tim2; |
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 86ddd65b60..fa2835846a 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h | |||
@@ -396,6 +396,7 @@ struct omap_sys_ctrl_regs { | |||
396 | u32 control_ddrio_0; | 396 | u32 control_ddrio_0; |
397 | u32 control_ddrio_1; | 397 | u32 control_ddrio_1; |
398 | u32 control_ddrio_2; | 398 | u32 control_ddrio_2; |
399 | u32 control_ddr_control_ext_0; | ||
399 | u32 control_lpddr2io1_0; | 400 | u32 control_lpddr2io1_0; |
400 | u32 control_lpddr2io1_1; | 401 | u32 control_lpddr2io1_1; |
401 | u32 control_lpddr2io1_2; | 402 | u32 control_lpddr2io1_2; |