diff options
Diffstat (limited to 'arch/arm/cpu/armv7/omap5/hw_data.c')
-rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 9374c6a82e..3f46211b50 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c | |||
@@ -186,7 +186,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { | |||
186 | 186 | ||
187 | static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { | 187 | static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { |
188 | {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ | 188 | {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ |
189 | {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ | 189 | {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */ |
190 | {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ | 190 | {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ |
191 | {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ | 191 | {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ |
192 | {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ | 192 | {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ |
@@ -423,6 +423,7 @@ void enable_basic_clocks(void) | |||
423 | (*prcm)->cm_wkup_wdtimer2_clkctrl, | 423 | (*prcm)->cm_wkup_wdtimer2_clkctrl, |
424 | (*prcm)->cm_l4per_uart3_clkctrl, | 424 | (*prcm)->cm_l4per_uart3_clkctrl, |
425 | (*prcm)->cm_l4per_i2c1_clkctrl, | 425 | (*prcm)->cm_l4per_i2c1_clkctrl, |
426 | (*prcm)->cm_l4per_qspi_clkctrl, | ||
426 | 0 | 427 | 0 |
427 | }; | 428 | }; |
428 | 429 | ||
@@ -451,6 +452,8 @@ void enable_basic_clocks(void) | |||
451 | clk_modules_explicit_en_essential, | 452 | clk_modules_explicit_en_essential, |
452 | 1); | 453 | 1); |
453 | 454 | ||
455 | setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); | ||
456 | |||
454 | /* Enable SCRM OPT clocks for PER and CORE dpll */ | 457 | /* Enable SCRM OPT clocks for PER and CORE dpll */ |
455 | setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, | 458 | setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, |
456 | OPTFCLKEN_SCRM_PER_MASK); | 459 | OPTFCLKEN_SCRM_PER_MASK); |