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* board: dra7xxx: modfiy mux data.HEADti2013.04.02ti-u-boot-2013.04+masterSourav Poddar2013-06-081-10/+11
| | | | | | Modify qspi pin configuartions Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* Fix offset detail and add sysboot settingsSourav Poddar2013-06-071-9/+8
| | | | | | Fix u-bot offset details and add qspi sysboot setings. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* README: qspi usecase and testing documentation.Sourav Poddar2013-06-072-0/+76
| | | | | | | Contains documentation and testing details for qspi flash interface. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* drivers: mtd: spi: Modify read/write command for sfl256s flash.Sourav Poddar2013-06-071-5/+34
| | | | | | | | | | Reading using the already supported read command is causing regression even while reading 4k bytes, as a result doing a page by page read. At the end of the write sequence, write enable latch should be disabled and re enabled while doing the next page programming. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* dra7xx_evm: add SPL API, QSPI, and serial flash supportMatt Porter2013-06-072-24/+310
| | | | | | | | Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode. Signed-off-by: Matt Porter <mporter@ti.com> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* spi: add TI QSPI driverMatt Porter2013-06-072-0/+263
| | | | | | | Adds a SPI master driver for the TI QSPI peripheral. Signed-off-by: Matt Porter <mporter@ti.com> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* omap5: add qspi supportMatt Porter2013-06-075-1/+10
| | | | | | | Add QSPI definitions and clock configuration support. Signed-off-by: Matt Porter <mporter@ti.com> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* ARM: DRA7xx: EMIF: Change settings required for EVM boardSricharan R2013-05-298-31/+220
| | | | | | | | | | | DRA7 EVM board has the below configuration. Adding the settings for the same here. 2Gb_1_35V_DDR3L part * 2 on EMIF1 2Gb_1_35V_DDR3L part * 4 on EMIF2 Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7xx: clocks: Update PLL valuesLokesh Vutla2013-05-297-46/+72
| | | | | | | | | | | Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>
* ARM: DRA7xx: Update pinmux dataLokesh Vutla2013-05-292-16/+29
| | | | | | | Updating pinmux data as specified in the latest DM Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Balaji T K <balajitk@ti.com>
* mmc: omap_hsmmc: add mmc1 pbias, ldo1Balaji T K2013-05-296-20/+48
| | | | | | | add dra mmc pbias support and ldo1 power on Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7xx: Correct SRAM END addressSricharan R2013-05-293-7/+6
| | | | | | | NON SECURE SRAM is 512KB in DRA7xx devices. So fixing it here. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* ARM: DRA7xx: Correct the SYS_CLK to 20MHZSricharan R2013-05-293-1/+7
| | | | | | | The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* ARM: DRA7xx: Change the Debug UART to UART1Sricharan R2013-05-293-4/+7
| | | | | | | Serial UART is connected to UART1. So add the change for the same. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc'sLokesh Vutla2013-05-292-0/+11
| | | | | | | | Slew rate compensation cells are not present for DRA7xx Soc's. So return from function srcomp_enable() if soc is not OMAP54xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP5: DRA7xx: support class 0 optimized voltagesNishanth Menon2013-05-294-12/+97
| | | | | | | | | | | | DRA752 now uses AVS Class 0 voltages which are voltages in efuse. This means that we can now use the optimized voltages which are stored as mV values in efuse and program PMIC accordingly. This allows us to go with higher OPP as needed in the system without the need for implementing complex AVS logic. Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: DRA7xx: clocks: Fixing i2c_init for PMICLokesh Vutla2013-05-292-2/+1
| | | | | | | | In DRA7xx Soc's voltage scaling is done using GPI2C. So i2c_init should happen before scaling. I2C driver uses __udelay which needs timer to be initialized. So moving timer_init just before voltage scaling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7xx: power Add support for tps659038 PMICLokesh Vutla2013-05-296-1/+80
| | | | | | | | TPS659038 is the power IC used in DRA7XX boards. Adding support for this and also adding pmic data for DRA7XX boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7xx: Add control id code for DRA7xxLokesh Vutla2013-05-292-3/+11
| | | | | | | | The registers that are used for device identification are changed from OMAP5 to DRA7xx. Using the correct registers for DRA7xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP4+: pmic: Make generic bus init and write functionsLokesh Vutla2013-05-297-8/+33
| | | | | | | | | | Voltage scaling can be done in two ways: -> Using SR I2C -> Using GP I2C In order to support both, have a function pointer in pmic_data so that we can call as per our requirement. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP5: clocks: Do not enable sgx clocksSricharan R2013-05-291-6/+0
| | | | | | | SGX clocks should be enabled only for OMAP5 ES1.0. So this can be removed. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* ARM: OMAP4+: Cleanup header filesLokesh Vutla2013-05-2913-140/+40
| | | | | | | After having the u-boot clean up series, there are many definitions that are unused in header files. Removing all those unused ones. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP: Add arch_cpu_init functionSRICHARAN R2013-05-107-0/+30
| | | | | | | | | | | | The boot parameters passed from SPL to UBOOT must be saved as a part of uboot's gd data as early as possible, before we will inadvertently overwrite it. So adding a arch_cpu_init for the required Socs to save it. Signed-off-by: Sricharan R <r.sricharan@ti.com> [trini: Add igep0033 hunk] Signed-off-by: Tom Rini <trini@ti.com>
* ARM: OMAP: Cleanup boot parameters usageSRICHARAN R2013-05-1012-91/+39
| | | | | | | | | | | The boot parameters are read from individual variables assigned for each of them. This been corrected and now they are stored as a part of the global data 'gd' structure. So read them from 'gd' instead. Signed-off-by: Sricharan R <r.sricharan@ti.com> [trini: Add igep0033 hunk] Signed-off-by: Tom Rini <trini@ti.com>
* ARM: OMAP: Correct save_boot_params and replace with 'C' functionSRICHARAN R2013-05-104-7/+56
| | | | | | | | | | | Currently save_boot_params saves the boot parameters passed from romcode. But this is not stored in a writable location consistently. So the current code would not work for a 'XIP' boot. Change this by saving the boot parameters in 'gd' which is always writable. Also add a 'C' function instead of an assembly code that is more readable. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines commonSRICHARAN R2013-05-109-33/+24
| | | | | | | | These defines are same across OMAP4/5. So move them to omap_common.h. This is required for the patches that follow. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* ARM: OMAP: Make omap_boot_parameters common across socsSRICHARAN R2013-05-104-72/+49
| | | | | | | | omap_boot_parameters is same and defined for each soc. So move this to a common place to reuse it across socs. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* am33xx: Fix warning with CONFIG_DISPLAY_CPUINFOTom Rini2013-05-101-5/+1
| | | | | | | | The arm_freq and ddr_freq variables are unused, so remove. Fixup whitespace slightly while in here. Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com>
* davinci: handle CONFIG_SYS_CLE_MASK and CONFIG_SYS_ALE_MASKEric Benard2013-05-105-8/+17
| | | | | | | | | | | | | these variables are curently defined in several config files but the driver doesn't use them and defaults to hardcoded values in nand_defs.h It's interesting to be able to change this hardcoded valude when the hardware is not using the default adress signals to drive ALE and CLE and two configuration defines already exist for this purpose so use them. Signed-off-by: Eric Bénard <eric@eukrea.com>
* da850: provide davinci_enable_uart0Eric Benard2013-05-102-0/+10
| | | | | | | | this is needed to bring UART0 out of reset but this function currently only exists for dm644x/355/365/646x when da850 (at least am1808 also need it). Signed-off-by: Eric Bénard <eric@eukrea.com>
* cm-t35: update config fileIgor Grinberg2013-05-101-13/+5
| | | | | | | Several minor updates to the cm-t35 config file. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
* MAINTAINERS: fix the cm-t35 board nameIgor Grinberg2013-05-101-1/+1
| | | | | | | "cm-t35" in U-Boot source code is called "cm_t35". Make the change "cm-t35" -> "cm_t35" for better greppability. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* cm-t35: move cm-t35 to live in compulab directoryIgor Grinberg2013-05-107-10/+11
| | | | | | | | | Currently the cm-t35 support code lives under board/cm_t35 directory. Some of the code can be shared with other/future CompuLab boards, so move the cm-t35 to live under board/compulab/cm_t35 directory. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
* ARM: Panda: Add flag to allow runtime enviroment varibale modsDan Murphy2013-05-101-0/+2
| | | | | | | | Add the flag to allow runtime enviroment variable modifications. This is being added so that the board-name can be modified at runtime to indicate either a panda(4430) or a panda-es(4460) Signed-off-by: Dan Murphy <dmurphy@ti.com>
* ARM:Panda:Fix device tree loading for the panda-esDan Murphy2013-05-102-1/+9
| | | | | | | | | | | Fix the device tree loading for panda(4430) and panda-es(4460) Modify the board name if a 4460 panda or panda-es is detected at run time. In the findfdt add a check for the panda-es board name and load the panda-es device tree blob. Signed-off-by: Dan Murphy <dmurphy@ti.com>
* ARM: OMAP5: Fix warm reset with USB cable connectedLokesh Vutla2013-05-1011-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Warm reset on OMAP5 freezes when USB cable is connected. Fix requires PRM_RSTTIME.RSTTIME1 to be programmed with the time for which reset should be held low for the voltages and the oscillator to reach stable state. There are 3 parameters to be considered for calculating the time, which are mostly board and PMIC dependent. -1- Time taken by the Oscillator to shut + restart -2- PMIC OTP times -3- Voltage rail ramp times, which inturn depends on the PMIC slew rate and value of the voltage ramp needed. In order to keep the code in u-boot simple, have a way for boards to specify a pre computed time directly using the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' option. If boards fail to specify the time, use a default as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead. Using the default value translates into some ~22ms and should work in all cases. However in order to avoid this large delay hiding other bugs, its recommended that all boards look at their respective data sheets and specify a pre computed and optimal value using 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' In order to help future board additions to compute this config option value, add a README at doc/README.omap-reset-time which explains how to compute the value. Also update the toplevel README with the additional option and pointers to doc/README.omap-reset-time. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [rnayak@ti.com: Updated changelog and added the README] Signed-off-by: Rajendra Nayak <rnayak@ti.com>
* Remove duplicate / unused #defines on AM335x boardsMark Jackson2013-05-102-11/+3
| | | | | | | | | | | | | As part of a review of a recent patch to add a new AM335x board, Tom found several duplicate and/or unused #defines. This patch simply removes them. The two affected configs have been recompiled to check nothing was broken (from a compilation point of view !!) Reported-by: Tom Rini <trini@ti.com> Signed-off-by: Mark Jackson <mpfj-list@mimc.co.uk>
* omap5_common: Add optargs variable for kernel command line argsTom Rini2013-05-101-0/+2
| | | | | | | | Add 'optargs' variable to be set to additional kernel arguments, similar to omap3*/am3* usage. Cc: Sricharan R <r.sricharan@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* OMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to workLubomir Popov2013-05-101-1/+1
| | | | | | | | | | | | USB TLL clocks do not support 'explicit_en', only 'hw_auto' control (R. Sricharan). cm_l3init_hsusbtll_clkctrl has to be moved to the clk_modules_hw_auto_essential[] array in order to make the clock work. This fix is needed (but not sufficient) for USB EHCI operation in U-Boot. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
* ARM: Add support for IGEP COM AQUILA/CYGNUSEnric Balletbo i Serra2013-05-107-0/+680
| | | | | | | | | | | | | | | | The IGEP COM AQUILA and CYGNUS are industrial processors modules with following highlights: o AM3352/AM3354 Texas Instruments processor o Cortex-A8 ARM CPU o 3.3 volts Inputs / Outputs use industrial o 256 MB DDR3 SDRAM / 128 Megabytes FLASH o MicroSD card reader on-board o Ethernet controller on-board o JTAG debug connector available o Designed for industrial range purposes Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
* Add DDR3 support for IGEP COM AQUILA/CYGNUS.Enric Balletbo i Serra2013-05-101-0/+17
| | | | | | These boards uses Samsung K4B2G1646E-BIH9 a 2Gb E-die DDR3 SDRAM. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
* arm: omap: emif: Fix DDR3 init after warm resetLokesh Vutla2013-05-101-3/+8
| | | | | | | | | | | | | | | | EMIF supports a global warm reset mode, during which the EMIF keeps the SDRAM content. But if leveling is enabled at the time of warm reset for DDR3, the following steps needs to be done after warm reset: 1) Keep EMIF in self refresh mode. 2) Reset PHY to bring back the PHY to a known state. 3) Start Levelling procedure. Doing the same. And also enabling DLL lock and code output after warm reset. Tested on OMAP5432 ES2.0 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* beagleboard: Update comment in get_board_rev()Tom Rini2013-05-101-2/+3
| | | | | | | | We are able to tell the difference between xM Rev Ax/Bx and xM Rev Cx, and have been for some time. The comment above the function however did not list this, so update. Signed-off-by: Tom Rini <trini@ti.com>
* OMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5Lubomir Popov2013-05-101-1/+1
| | | | | | | | | | | I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. In order to be able to select one of these buses however, I2C_BUS_MAX has to be set to 5; do this here. Please note that for working bus selection, a fix to the i2c driver is required as well (subject of a separate patch). Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
* OMAP5: I2C: Add I2C4 and I2C5 basesLubomir Popov2013-05-101-0/+2
| | | | | | | | I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. The I2C4 and I2C5 base addresses were however not defined; do this here. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
* OMAP5: I2C: Enable i2c5 clocksLubomir Popov2013-05-101-0/+1
| | | | | | | I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. The i2c5 clock was however not enabled; do this here. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
* palmas: add header guardNishanth Menon2013-05-101-0/+4
| | | | | | | Add an header guard to common header file to prevent multiple includes messing things up. Signed-off-by: Nishanth Menon <nm@ti.com>
* palmas: use palmas_i2c_[read|write]_u8Nishanth Menon2013-05-102-26/+16
| | | | | | | | | | | | | | | | | commit 21144298 (power: twl6035: add palmas PMIC support) introduced twl6035_i2c_[read|write]_u8 Then, commit dd23e59d (omap5: pbias ldo9 turn on) introduced palmas_[read|write]_u8 for precisely the same access function. TWL6035 belongs to the palmas family, so instead of having an twl6035 API, we could use an generic palmas API instead. To stay consistent with the function naming of twl4030,6030 accessors, we use palmas_i2c_[read|write]_u8 Cc: Balaji T K <balajitk@ti.com> Cc: Sricharan R <r.sricharan@ti.com> Reported-by: Ruchika Kharwar <ruchika@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* palmas: rename twl6035_mmc1_poweron_ldo with an palmas generic functionNishanth Menon2013-05-103-3/+3
| | | | | | | | Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs, rename twl6035_mmc1_poweron_ldo by a more generic palmas_mmc1_poweron_ldo function. Signed-off-by: Nishanth Menon <nm@ti.com>
* palmas: rename init_settings to an generic palmas initNishanth Menon2013-05-103-3/+3
| | | | | | | Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs, rename twl6035_init_settings with an more generic palmas_init_settings Signed-off-by: Nishanth Menon <nm@ti.com>