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authorChris Wilson2016-08-20 12:36:42 -0500
committerChris Wilson2017-01-27 14:00:38 -0600
commit1bd35da961312aeb33fc7af586fa0d1f207a2d5f (patch)
tree6aeed9c99c04faf5073307b939baa4fb421058db
parenta3d715ee14b29d2680ceaf44955679205795140c (diff)
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intel: Allow the client to control implicit synchronisation
The kernel allows implicit synchronisation to be disabled on individual buffers. Use at your own risk. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-rw-r--r--intel/intel_bufmgr.h4
-rw-r--r--intel/intel_bufmgr_gem.c49
2 files changed, 49 insertions, 4 deletions
diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index 85e4ff78..f43ee470 100644
--- a/intel/intel_bufmgr.h
+++ b/intel/intel_bufmgr.h
@@ -184,6 +184,10 @@ int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo);
184int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo); 184int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
185int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo); 185int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
186 186
187#define HAVE_DRM_INTEL_GEM_BO_DISABLE_IMPLICIT_SYNC 1
188int drm_intel_bufmgr_gem_can_disable_implicit_sync(drm_intel_bufmgr *bufmgr);
189void drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo);
190
187void *drm_intel_gem_bo_map__cpu(drm_intel_bo *bo); 191void *drm_intel_gem_bo_map__cpu(drm_intel_bo *bo);
188void *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo); 192void *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo);
189void *drm_intel_gem_bo_map__wc(drm_intel_bo *bo); 193void *drm_intel_gem_bo_map__wc(drm_intel_bo *bo);
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index c47cb9b2..554d079b 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -149,6 +149,7 @@ typedef struct _drm_intel_bufmgr_gem {
149 unsigned int bo_reuse : 1; 149 unsigned int bo_reuse : 1;
150 unsigned int no_exec : 1; 150 unsigned int no_exec : 1;
151 unsigned int has_vebox : 1; 151 unsigned int has_vebox : 1;
152 unsigned int has_exec_async : 1;
152 bool fenced_relocs; 153 bool fenced_relocs;
153 154
154 struct { 155 struct {
@@ -195,6 +196,8 @@ struct _drm_intel_bo_gem {
195 uint32_t swizzle_mode; 196 uint32_t swizzle_mode;
196 unsigned long stride; 197 unsigned long stride;
197 198
199 unsigned long kflags;
200
198 time_t free_time; 201 time_t free_time;
199 202
200 /** Array passed to the DRM containing relocation information. */ 203 /** Array passed to the DRM containing relocation information. */
@@ -575,12 +578,11 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
575 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count; 578 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
576 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs; 579 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
577 bufmgr_gem->exec2_objects[index].alignment = bo->align; 580 bufmgr_gem->exec2_objects[index].alignment = bo->align;
578 bufmgr_gem->exec2_objects[index].offset = bo_gem->is_softpin ? 581 bufmgr_gem->exec2_objects[index].offset = bo->offset64;
579 bo->offset64 : 0; 582 bufmgr_gem->exec2_objects[index].flags = flags | bo_gem->kflags;
580 bufmgr_gem->exec_bos[index] = bo;
581 bufmgr_gem->exec2_objects[index].flags = flags;
582 bufmgr_gem->exec2_objects[index].rsvd1 = 0; 583 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
583 bufmgr_gem->exec2_objects[index].rsvd2 = 0; 584 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
585 bufmgr_gem->exec_bos[index] = bo;
584 bufmgr_gem->exec_count++; 586 bufmgr_gem->exec_count++;
585} 587}
586 588
@@ -1368,6 +1370,7 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
1368 for (i = 0; i < bo_gem->softpin_target_count; i++) 1370 for (i = 0; i < bo_gem->softpin_target_count; i++)
1369 drm_intel_gem_bo_unreference_locked_timed(bo_gem->softpin_target[i], 1371 drm_intel_gem_bo_unreference_locked_timed(bo_gem->softpin_target[i],
1370 time); 1372 time);
1373 bo_gem->kflags = 0;
1371 bo_gem->reloc_count = 0; 1374 bo_gem->reloc_count = 0;
1372 bo_gem->used_as_reloc_target = false; 1375 bo_gem->used_as_reloc_target = false;
1373 bo_gem->softpin_target_count = 0; 1376 bo_gem->softpin_target_count = 0;
@@ -2766,6 +2769,40 @@ drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
2766} 2769}
2767 2770
2768/** 2771/**
2772 * Disables implicit synchronisation before executing the bo
2773 *
2774 * This will cause rendering corruption unless you correctly manage explicit
2775 * fences for all rendering involving this buffer - including use by others.
2776 * Disabling the implicit serialisation is only required if that serialisation
2777 * is too coarse (for example, you have split the buffer into many
2778 * non-overlapping regions and are sharing the whole buffer between concurrent
2779 * independent command streams).
2780 *
2781 * Note the kernel must advertise support via I915_PARAM_HAS_EXEC_ASYNC,
2782 * which can be checked using drm_intel_bufmgr_can_disable_implicit_sync,
2783 * or subsequent execbufs involving the bo will generate EINVAL.
2784 */
2785void
2786drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo)
2787{
2788 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2789
2790 bo_gem->kflags |= EXEC_OBJECT_ASYNC;
2791}
2792
2793/**
2794 * Query whether the kernel supports disabling of its implicit synchronisation
2795 * before execbuf. See drm_intel_gem_bo_disable_implicit_sync()
2796 */
2797int
2798drm_intel_bufmgr_gem_can_disable_implicit_sync(drm_intel_bufmgr *bufmgr)
2799{
2800 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2801
2802 return bufmgr_gem->has_exec_async;
2803}
2804
2805/**
2769 * Enable use of fenced reloc type. 2806 * Enable use of fenced reloc type.
2770 * 2807 *
2771 * New code should enable this to avoid unnecessary fence register 2808 * New code should enable this to avoid unnecessary fence register
@@ -3635,6 +3672,10 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
3635 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); 3672 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3636 bufmgr_gem->has_relaxed_fencing = ret == 0; 3673 bufmgr_gem->has_relaxed_fencing = ret == 0;
3637 3674
3675 gp.param = I915_PARAM_HAS_EXEC_ASYNC;
3676 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3677 bufmgr_gem->has_exec_async = ret == 0;
3678
3638 bufmgr_gem->bufmgr.bo_alloc_userptr = check_bo_alloc_userptr; 3679 bufmgr_gem->bufmgr.bo_alloc_userptr = check_bo_alloc_userptr;
3639 3680
3640 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT; 3681 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;