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author | Rodrigo Vivi | 2018-02-08 00:46:43 -0600 |
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committer | Rodrigo Vivi | 2018-03-05 17:13:05 -0600 |
commit | 7b12381723021fd5fbcf761e6832dd16a14f52d4 (patch) | |
tree | 49d420e937ca3f089dcf93677b53c0be393c7e37 | |
parent | 85ae22af0f209e73c954d8867d9189ab2cfeb3e1 (diff) | |
download | external-libdrm-7b12381723021fd5fbcf761e6832dd16a14f52d4.tar.gz external-libdrm-7b12381723021fd5fbcf761e6832dd16a14f52d4.tar.xz external-libdrm-7b12381723021fd5fbcf761e6832dd16a14f52d4.zip |
intel/intel_chipset.h: Sync Cannonlake IDs.
Let's sync CNL ids with Spec and kernel.
Sync with kernel commit '3f43031b1693 ("drm/i915/cnl:
Add Cannonlake PCI IDs for another SKU.")' and
commit 'e3890d05b342 ("drm/i915/cnl: Sync PCI ID with Spec.")'
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
-rw-r--r-- | intel/intel_chipset.h | 52 |
1 files changed, 28 insertions, 24 deletions
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 3818e71e..01d250e8 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h | |||
@@ -241,16 +241,20 @@ | |||
241 | #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 | 241 | #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 |
242 | #define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 | 242 | #define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 |
243 | 243 | ||
244 | #define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52 | 244 | #define PCI_CHIP_CANNONLAKE_0 0x5A51 |
245 | #define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A | 245 | #define PCI_CHIP_CANNONLAKE_1 0x5A59 |
246 | #define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42 | 246 | #define PCI_CHIP_CANNONLAKE_2 0x5A41 |
247 | #define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A | 247 | #define PCI_CHIP_CANNONLAKE_3 0x5A49 |
248 | #define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51 | 248 | #define PCI_CHIP_CANNONLAKE_4 0x5A52 |
249 | #define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59 | 249 | #define PCI_CHIP_CANNONLAKE_5 0x5A5A |
250 | #define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41 | 250 | #define PCI_CHIP_CANNONLAKE_6 0x5A42 |
251 | #define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49 | 251 | #define PCI_CHIP_CANNONLAKE_7 0x5A4A |
252 | #define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71 | 252 | #define PCI_CHIP_CANNONLAKE_8 0x5A50 |
253 | #define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79 | 253 | #define PCI_CHIP_CANNONLAKE_9 0x5A40 |
254 | #define PCI_CHIP_CANNONLAKE_10 0x5A54 | ||
255 | #define PCI_CHIP_CANNONLAKE_11 0x5A5C | ||
256 | #define PCI_CHIP_CANNONLAKE_12 0x5A44 | ||
257 | #define PCI_CHIP_CANNONLAKE_13 0x5A4C | ||
254 | 258 | ||
255 | #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ | 259 | #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ |
256 | (devid) == PCI_CHIP_I915_GM || \ | 260 | (devid) == PCI_CHIP_I915_GM || \ |
@@ -515,20 +519,20 @@ | |||
515 | IS_GEMINILAKE(devid) || \ | 519 | IS_GEMINILAKE(devid) || \ |
516 | IS_COFFEELAKE(devid)) | 520 | IS_COFFEELAKE(devid)) |
517 | 521 | ||
518 | #define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \ | 522 | #define IS_CANNONLAKE(devid) ((devid) == PCI_CHIP_CANNONLAKE_0 || \ |
519 | (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \ | 523 | (devid) == PCI_CHIP_CANNONLAKE_1 || \ |
520 | (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \ | 524 | (devid) == PCI_CHIP_CANNONLAKE_2 || \ |
521 | (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \ | 525 | (devid) == PCI_CHIP_CANNONLAKE_3 || \ |
522 | (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \ | 526 | (devid) == PCI_CHIP_CANNONLAKE_4 || \ |
523 | (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5) | 527 | (devid) == PCI_CHIP_CANNONLAKE_5 || \ |
524 | 528 | (devid) == PCI_CHIP_CANNONLAKE_6 || \ | |
525 | #define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \ | 529 | (devid) == PCI_CHIP_CANNONLAKE_7 || \ |
526 | (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \ | 530 | (devid) == PCI_CHIP_CANNONLAKE_8 || \ |
527 | (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \ | 531 | (devid) == PCI_CHIP_CANNONLAKE_9 || \ |
528 | (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3) | 532 | (devid) == PCI_CHIP_CANNONLAKE_10 || \ |
529 | 533 | (devid) == PCI_CHIP_CANNONLAKE_11 || \ | |
530 | #define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \ | 534 | (devid) == PCI_CHIP_CANNONLAKE_12 || \ |
531 | IS_CNL_Y(devid)) | 535 | (devid) == PCI_CHIP_CANNONLAKE_13) |
532 | 536 | ||
533 | #define IS_GEN10(devid) (IS_CANNONLAKE(devid)) | 537 | #define IS_GEN10(devid) (IS_CANNONLAKE(devid)) |
534 | 538 | ||