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author | Anusha Srivatsa | 2017-06-21 13:17:37 -0500 |
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committer | Rodrigo Vivi | 2017-06-29 12:51:29 -0500 |
commit | 4c98652cb5cd3b0ef3681b1a7b2892c14b7f5c34 (patch) | |
tree | 29225b9b1a2bd6df68f4f28eeb3a81f6014e736b | |
parent | 2b48faf30e03cdafccffd7d6c6a715c2f969fc31 (diff) | |
download | external-libdrm-4c98652cb5cd3b0ef3681b1a7b2892c14b7f5c34.tar.gz external-libdrm-4c98652cb5cd3b0ef3681b1a7b2892c14b7f5c34.tar.xz external-libdrm-4c98652cb5cd3b0ef3681b1a7b2892c14b7f5c34.zip |
intel: PCI Ids for U SKU in CFL
Add the PCI IDs for U SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-rw-r--r-- | intel/intel_chipset.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index fed5a0d8..891b50fc 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h | |||
@@ -228,6 +228,10 @@ | |||
228 | #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 | 228 | #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 |
229 | #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B | 229 | #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B |
230 | #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 | 230 | #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 |
231 | #define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5 | ||
232 | #define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6 | ||
233 | #define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7 | ||
234 | #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8 | ||
231 | 235 | ||
232 | #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ | 236 | #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ |
233 | (devid) == PCI_CHIP_I915_GM || \ | 237 | (devid) == PCI_CHIP_I915_GM || \ |
@@ -469,8 +473,14 @@ | |||
469 | #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ | 473 | #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ |
470 | (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) | 474 | (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) |
471 | 475 | ||
476 | #define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ | ||
477 | (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \ | ||
478 | (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \ | ||
479 | (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4) | ||
480 | |||
472 | #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ | 481 | #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ |
473 | IS_CFL_H(devid)) | 482 | IS_CFL_H(devid) || \ |
483 | IS_CFL_U(devid)) | ||
474 | 484 | ||
475 | #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ | 485 | #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ |
476 | IS_BROXTON(devid) || \ | 486 | IS_BROXTON(devid) || \ |