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authorEric Anholt2017-06-21 12:23:23 -0500
committerDaniel Stone2017-06-22 04:49:00 -0500
commitb9549c954e190010a79e6691983b6ae16eac83d5 (patch)
treecd914eac8412cb9741c37844d26bb5fe12cccec8
parent7e6bf88cac315a9fa41818cf72a7b5d18a2cb1fc (diff)
downloadexternal-libdrm-b9549c954e190010a79e6691983b6ae16eac83d5.tar.gz
external-libdrm-b9549c954e190010a79e6691983b6ae16eac83d5.tar.xz
external-libdrm-b9549c954e190010a79e6691983b6ae16eac83d5.zip
headers: Update drm_fourcc and vc4_drm.h with new VC4 tiling UAPI.
Taken from make headers_install of drm-misc-next (34c8ea400ff6383b028f63df2453914163afc07c) Reviewed-by: Daniel Stone <daniels@collabora.com>
-rw-r--r--include/drm/drm_fourcc.h23
-rw-r--r--include/drm/vc4_drm.h22
2 files changed, 41 insertions, 4 deletions
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 55e30104..7586c46f 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -182,6 +182,7 @@ extern "C" {
182#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 182#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
183#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 183#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
184#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 184#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
185#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
185/* add more to the end as needed */ 186/* add more to the end as needed */
186 187
187#define fourcc_mod_code(vendor, val) \ 188#define fourcc_mod_code(vendor, val) \
@@ -306,7 +307,6 @@ extern "C" {
306 */ 307 */
307#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 308#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
308 309
309
310/* NVIDIA Tegra frame buffer modifiers */ 310/* NVIDIA Tegra frame buffer modifiers */
311 311
312/* 312/*
@@ -351,6 +351,27 @@ extern "C" {
351 */ 351 */
352#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) 352#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
353 353
354/*
355 * Broadcom VC4 "T" format
356 *
357 * This is the primary layout that the V3D GPU can texture from (it
358 * can't do linear). The T format has:
359 *
360 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
361 * pixels at 32 bit depth.
362 *
363 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
364 * 16x16 pixels).
365 *
366 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
367 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
368 * they're (TR, BR, BL, TL), where bottom left is start of memory.
369 *
370 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
371 * tiles) or right-to-left (odd rows of 4k tiles).
372 */
373#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
374
354#if defined(__cplusplus) 375#if defined(__cplusplus)
355} 376}
356#endif 377#endif
diff --git a/include/drm/vc4_drm.h b/include/drm/vc4_drm.h
index 319881d8..6ac4c5c0 100644
--- a/include/drm/vc4_drm.h
+++ b/include/drm/vc4_drm.h
@@ -21,8 +21,8 @@
21 * IN THE SOFTWARE. 21 * IN THE SOFTWARE.
22 */ 22 */
23 23
24#ifndef _VC4_DRM_H_ 24#ifndef _UAPI_VC4_DRM_H_
25#define _VC4_DRM_H_ 25#define _UAPI_VC4_DRM_H_
26 26
27#include "drm.h" 27#include "drm.h"
28 28
@@ -38,6 +38,8 @@ extern "C" {
38#define DRM_VC4_CREATE_SHADER_BO 0x05 38#define DRM_VC4_CREATE_SHADER_BO 0x05
39#define DRM_VC4_GET_HANG_STATE 0x06 39#define DRM_VC4_GET_HANG_STATE 0x06
40#define DRM_VC4_GET_PARAM 0x07 40#define DRM_VC4_GET_PARAM 0x07
41#define DRM_VC4_SET_TILING 0x08
42#define DRM_VC4_GET_TILING 0x09
41 43
42#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) 44#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
43#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) 45#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
@@ -47,6 +49,8 @@ extern "C" {
47#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) 49#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
48#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) 50#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
49#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) 51#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
52#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
53#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
50 54
51struct drm_vc4_submit_rcl_surface { 55struct drm_vc4_submit_rcl_surface {
52 __u32 hindex; /* Handle index, or ~0 if not present. */ 56 __u32 hindex; /* Handle index, or ~0 if not present. */
@@ -295,8 +299,20 @@ struct drm_vc4_get_param {
295 __u64 value; 299 __u64 value;
296}; 300};
297 301
302struct drm_vc4_get_tiling {
303 __u32 handle;
304 __u32 flags;
305 __u64 modifier;
306};
307
308struct drm_vc4_set_tiling {
309 __u32 handle;
310 __u32 flags;
311 __u64 modifier;
312};
313
298#if defined(__cplusplus) 314#if defined(__cplusplus)
299} 315}
300#endif 316#endif
301 317
302#endif /* _VC4_DRM_H_ */ 318#endif /* _UAPI_VC4_DRM_H_ */