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authorJammy Zhou2015-05-29 05:59:59 -0500
committerAlex Deucher2015-08-05 12:47:50 -0500
commit40c53360437fec5faee83f0b64bb6756926d2fe0 (patch)
tree8b6a890d59082799ce18369ab00c9a0d12244189 /amdgpu/amdgpu_internal.h
parentef9aa370bb3a5e1725998a4b31237ffc14a062b0 (diff)
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amdgpu: get rid of IB pool management v3
v1: by Jammy Zhou v2: remove bo wait when destroy IB by Jammy Zhou v3: more cleanups by Marek Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian K├Ânig <christian.koenig@amd.com>
Diffstat (limited to 'amdgpu/amdgpu_internal.h')
-rw-r--r--amdgpu/amdgpu_internal.h20
1 files changed, 1 insertions, 19 deletions
diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h
index c1cd4da7..e5a457ab 100644
--- a/amdgpu/amdgpu_internal.h
+++ b/amdgpu/amdgpu_internal.h
@@ -97,42 +97,24 @@ struct amdgpu_bo_list {
97 uint32_t handle; 97 uint32_t handle;
98}; 98};
99 99
100/*
101 * There are three mutexes.
102 * To avoid deadlock, only hold the mutexes in this order:
103 * sequence_mutex -> pendings_mutex -> pool_mutex.
104*/
105struct amdgpu_context { 100struct amdgpu_context {
106 struct amdgpu_device *dev; 101 struct amdgpu_device *dev;
107 /** Mutex for accessing fences and to maintain command submissions 102 /** Mutex for accessing fences and to maintain command submissions
108 and pending lists in good sequence. */ 103 in good sequence. */
109 pthread_mutex_t sequence_mutex; 104 pthread_mutex_t sequence_mutex;
110 /** Buffer for user fences */ 105 /** Buffer for user fences */
111 struct amdgpu_ib *fence_ib; 106 struct amdgpu_ib *fence_ib;
112 /** The newest expired fence for the ring of the ip blocks. */ 107 /** The newest expired fence for the ring of the ip blocks. */
113 uint64_t expired_fences[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS]; 108 uint64_t expired_fences[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
114 /** Mutex for accessing pendings list. */
115 pthread_mutex_t pendings_mutex;
116 /** Pending IBs. */
117 struct list_head pendings[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
118 /** Freed IBs not yet in pool */
119 struct list_head freed;
120 /** Mutex for accessing free ib pool. */
121 pthread_mutex_t pool_mutex;
122 /** Internal free IB pools. */
123 struct list_head ib_pools[AMDGPU_CS_IB_SIZE_NUM];
124 /* context id*/ 109 /* context id*/
125 uint32_t id; 110 uint32_t id;
126}; 111};
127 112
128struct amdgpu_ib { 113struct amdgpu_ib {
129 amdgpu_context_handle context; 114 amdgpu_context_handle context;
130 struct list_head list_node;
131 amdgpu_bo_handle buf_handle; 115 amdgpu_bo_handle buf_handle;
132 void *cpu; 116 void *cpu;
133 uint64_t virtual_mc_base_address; 117 uint64_t virtual_mc_base_address;
134 enum amdgpu_cs_ib_size ib_size;
135 uint64_t cs_handle;
136}; 118};
137 119
138/** 120/**