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author | Rob Clark | 2017-08-23 14:00:12 -0500 |
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committer | Rob Clark | 2017-11-04 16:23:20 -0500 |
commit | 62e0767b816cb52b35226d439090ef580bd60b01 (patch) | |
tree | 11810b38102bbe341f63bbe5f1af3d6f53610dcd /freedreno | |
parent | 2fe4c07b38ded7f4b9341512da6e670d3321012b (diff) | |
download | external-libdrm-62e0767b816cb52b35226d439090ef580bd60b01.tar.gz external-libdrm-62e0767b816cb52b35226d439090ef580bd60b01.tar.xz external-libdrm-62e0767b816cb52b35226d439090ef580bd60b01.zip |
freedreno: sync uapi header (driver version 1.3.0)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Diffstat (limited to 'freedreno')
-rw-r--r-- | freedreno/msm/msm_drm.h | 40 |
1 files changed, 34 insertions, 6 deletions
diff --git a/freedreno/msm/msm_drm.h b/freedreno/msm/msm_drm.h index ed4c8d47..dac49e59 100644 --- a/freedreno/msm/msm_drm.h +++ b/freedreno/msm/msm_drm.h | |||
@@ -73,6 +73,8 @@ struct drm_msm_timespec { | |||
73 | #define MSM_PARAM_CHIP_ID 0x03 | 73 | #define MSM_PARAM_CHIP_ID 0x03 |
74 | #define MSM_PARAM_MAX_FREQ 0x04 | 74 | #define MSM_PARAM_MAX_FREQ 0x04 |
75 | #define MSM_PARAM_TIMESTAMP 0x05 | 75 | #define MSM_PARAM_TIMESTAMP 0x05 |
76 | #define MSM_PARAM_GMEM_BASE 0x06 | ||
77 | #define MSM_PARAM_NR_RINGS 0x07 | ||
76 | 78 | ||
77 | struct drm_msm_param { | 79 | struct drm_msm_param { |
78 | __u32 pipe; /* in, MSM_PIPE_x */ | 80 | __u32 pipe; /* in, MSM_PIPE_x */ |
@@ -104,10 +106,14 @@ struct drm_msm_gem_new { | |||
104 | __u32 handle; /* out */ | 106 | __u32 handle; /* out */ |
105 | }; | 107 | }; |
106 | 108 | ||
109 | #define MSM_INFO_IOVA 0x01 | ||
110 | |||
111 | #define MSM_INFO_FLAGS (MSM_INFO_IOVA) | ||
112 | |||
107 | struct drm_msm_gem_info { | 113 | struct drm_msm_gem_info { |
108 | __u32 handle; /* in */ | 114 | __u32 handle; /* in */ |
109 | __u32 pad; | 115 | __u32 flags; /* in - combination of MSM_INFO_* flags */ |
110 | __u64 offset; /* out, offset to pass to mmap() */ | 116 | __u64 offset; /* out, mmap() offset or iova */ |
111 | }; | 117 | }; |
112 | 118 | ||
113 | #define MSM_PREP_READ 0x01 | 119 | #define MSM_PREP_READ 0x01 |
@@ -167,7 +173,7 @@ struct drm_msm_gem_submit_cmd { | |||
167 | __u32 size; /* in, cmdstream size */ | 173 | __u32 size; /* in, cmdstream size */ |
168 | __u32 pad; | 174 | __u32 pad; |
169 | __u32 nr_relocs; /* in, number of submit_reloc's */ | 175 | __u32 nr_relocs; /* in, number of submit_reloc's */ |
170 | __u64 __user relocs; /* in, ptr to array of submit_reloc's */ | 176 | __u64 relocs; /* in, ptr to array of submit_reloc's */ |
171 | }; | 177 | }; |
172 | 178 | ||
173 | /* Each buffer referenced elsewhere in the cmdstream submit (ie. the | 179 | /* Each buffer referenced elsewhere in the cmdstream submit (ie. the |
@@ -211,9 +217,10 @@ struct drm_msm_gem_submit { | |||
211 | __u32 fence; /* out */ | 217 | __u32 fence; /* out */ |
212 | __u32 nr_bos; /* in, number of submit_bo's */ | 218 | __u32 nr_bos; /* in, number of submit_bo's */ |
213 | __u32 nr_cmds; /* in, number of submit_cmd's */ | 219 | __u32 nr_cmds; /* in, number of submit_cmd's */ |
214 | __u64 __user bos; /* in, ptr to array of submit_bo's */ | 220 | __u64 bos; /* in, ptr to array of submit_bo's */ |
215 | __u64 __user cmds; /* in, ptr to array of submit_cmd's */ | 221 | __u64 cmds; /* in, ptr to array of submit_cmd's */ |
216 | __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ | 222 | __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ |
223 | __u32 queueid; /* in, submitqueue id */ | ||
217 | }; | 224 | }; |
218 | 225 | ||
219 | /* The normal way to synchronize with the GPU is just to CPU_PREP on | 226 | /* The normal way to synchronize with the GPU is just to CPU_PREP on |
@@ -227,6 +234,7 @@ struct drm_msm_wait_fence { | |||
227 | __u32 fence; /* in */ | 234 | __u32 fence; /* in */ |
228 | __u32 pad; | 235 | __u32 pad; |
229 | struct drm_msm_timespec timeout; /* in */ | 236 | struct drm_msm_timespec timeout; /* in */ |
237 | __u32 queueid; /* in, submitqueue id */ | ||
230 | }; | 238 | }; |
231 | 239 | ||
232 | /* madvise provides a way to tell the kernel in case a buffers contents | 240 | /* madvise provides a way to tell the kernel in case a buffers contents |
@@ -250,6 +258,20 @@ struct drm_msm_gem_madvise { | |||
250 | __u32 retained; /* out, whether backing store still exists */ | 258 | __u32 retained; /* out, whether backing store still exists */ |
251 | }; | 259 | }; |
252 | 260 | ||
261 | /* | ||
262 | * Draw queues allow the user to set specific submission parameter. Command | ||
263 | * submissions specify a specific submitqueue to use. ID 0 is reserved for | ||
264 | * backwards compatibility as a "default" submitqueue | ||
265 | */ | ||
266 | |||
267 | #define MSM_SUBMITQUEUE_FLAGS (0) | ||
268 | |||
269 | struct drm_msm_submitqueue { | ||
270 | __u32 flags; /* in, MSM_SUBMITQUEUE_x */ | ||
271 | __u32 prio; /* in, Priority level */ | ||
272 | __u32 id; /* out, identifier */ | ||
273 | }; | ||
274 | |||
253 | #define DRM_MSM_GET_PARAM 0x00 | 275 | #define DRM_MSM_GET_PARAM 0x00 |
254 | /* placeholder: | 276 | /* placeholder: |
255 | #define DRM_MSM_SET_PARAM 0x01 | 277 | #define DRM_MSM_SET_PARAM 0x01 |
@@ -261,7 +283,11 @@ struct drm_msm_gem_madvise { | |||
261 | #define DRM_MSM_GEM_SUBMIT 0x06 | 283 | #define DRM_MSM_GEM_SUBMIT 0x06 |
262 | #define DRM_MSM_WAIT_FENCE 0x07 | 284 | #define DRM_MSM_WAIT_FENCE 0x07 |
263 | #define DRM_MSM_GEM_MADVISE 0x08 | 285 | #define DRM_MSM_GEM_MADVISE 0x08 |
264 | #define DRM_MSM_NUM_IOCTLS 0x09 | 286 | /* placeholder: |
287 | #define DRM_MSM_GEM_SVM_NEW 0x09 | ||
288 | */ | ||
289 | #define DRM_MSM_SUBMITQUEUE_NEW 0x0A | ||
290 | #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B | ||
265 | 291 | ||
266 | #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) | 292 | #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) |
267 | #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) | 293 | #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) |
@@ -271,6 +297,8 @@ struct drm_msm_gem_madvise { | |||
271 | #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) | 297 | #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) |
272 | #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) | 298 | #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) |
273 | #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) | 299 | #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) |
300 | #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) | ||
301 | #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) | ||
274 | 302 | ||
275 | #if defined(__cplusplus) | 303 | #if defined(__cplusplus) |
276 | } | 304 | } |