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author | Rob Clark | 2016-08-15 11:52:31 -0500 |
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committer | Rob Clark | 2016-11-05 09:17:54 -0500 |
commit | 9270d984cde31a8abc5f9ec31cbd86a10b883864 (patch) | |
tree | 89818b9d0df9f28b499e9c20e2b34133782dda38 /freedreno | |
parent | f803a45e744272190aaaab1ad7c702641190d002 (diff) | |
download | external-libdrm-9270d984cde31a8abc5f9ec31cbd86a10b883864.tar.gz external-libdrm-9270d984cde31a8abc5f9ec31cbd86a10b883864.tar.xz external-libdrm-9270d984cde31a8abc5f9ec31cbd86a10b883864.zip |
freedreno: sync uapi header
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Diffstat (limited to 'freedreno')
-rw-r--r-- | freedreno/msm/msm_drm.h | 22 | ||||
-rw-r--r-- | freedreno/msm/msm_ringbuffer.c | 2 |
2 files changed, 22 insertions, 2 deletions
diff --git a/freedreno/msm/msm_drm.h b/freedreno/msm/msm_drm.h index cbf75c3d..ed4c8d47 100644 --- a/freedreno/msm/msm_drm.h +++ b/freedreno/msm/msm_drm.h | |||
@@ -50,6 +50,15 @@ extern "C" { | |||
50 | #define MSM_PIPE_2D1 0x02 | 50 | #define MSM_PIPE_2D1 0x02 |
51 | #define MSM_PIPE_3D0 0x10 | 51 | #define MSM_PIPE_3D0 0x10 |
52 | 52 | ||
53 | /* The pipe-id just uses the lower bits, so can be OR'd with flags in | ||
54 | * the upper 16 bits (which could be extended further, if needed, maybe | ||
55 | * we extend/overload the pipe-id some day to deal with multiple rings, | ||
56 | * but even then I don't think we need the full lower 16 bits). | ||
57 | */ | ||
58 | #define MSM_PIPE_ID_MASK 0xffff | ||
59 | #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) | ||
60 | #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) | ||
61 | |||
53 | /* timeouts are specified in clock-monotonic absolute times (to simplify | 62 | /* timeouts are specified in clock-monotonic absolute times (to simplify |
54 | * restarting interrupted ioctls). The following struct is logically the | 63 | * restarting interrupted ioctls). The following struct is logically the |
55 | * same as 'struct timespec' but 32/64b ABI safe. | 64 | * same as 'struct timespec' but 32/64b ABI safe. |
@@ -183,17 +192,28 @@ struct drm_msm_gem_submit_bo { | |||
183 | __u64 presumed; /* in/out, presumed buffer address */ | 192 | __u64 presumed; /* in/out, presumed buffer address */ |
184 | }; | 193 | }; |
185 | 194 | ||
195 | /* Valid submit ioctl flags: */ | ||
196 | #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */ | ||
197 | #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */ | ||
198 | #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */ | ||
199 | #define MSM_SUBMIT_FLAGS ( \ | ||
200 | MSM_SUBMIT_NO_IMPLICIT | \ | ||
201 | MSM_SUBMIT_FENCE_FD_IN | \ | ||
202 | MSM_SUBMIT_FENCE_FD_OUT | \ | ||
203 | 0) | ||
204 | |||
186 | /* Each cmdstream submit consists of a table of buffers involved, and | 205 | /* Each cmdstream submit consists of a table of buffers involved, and |
187 | * one or more cmdstream buffers. This allows for conditional execution | 206 | * one or more cmdstream buffers. This allows for conditional execution |
188 | * (context-restore), and IB buffers needed for per tile/bin draw cmds. | 207 | * (context-restore), and IB buffers needed for per tile/bin draw cmds. |
189 | */ | 208 | */ |
190 | struct drm_msm_gem_submit { | 209 | struct drm_msm_gem_submit { |
191 | __u32 pipe; /* in, MSM_PIPE_x */ | 210 | __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ |
192 | __u32 fence; /* out */ | 211 | __u32 fence; /* out */ |
193 | __u32 nr_bos; /* in, number of submit_bo's */ | 212 | __u32 nr_bos; /* in, number of submit_bo's */ |
194 | __u32 nr_cmds; /* in, number of submit_cmd's */ | 213 | __u32 nr_cmds; /* in, number of submit_cmd's */ |
195 | __u64 __user bos; /* in, ptr to array of submit_bo's */ | 214 | __u64 __user bos; /* in, ptr to array of submit_bo's */ |
196 | __u64 __user cmds; /* in, ptr to array of submit_cmd's */ | 215 | __u64 __user cmds; /* in, ptr to array of submit_cmd's */ |
216 | __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ | ||
197 | }; | 217 | }; |
198 | 218 | ||
199 | /* The normal way to synchronize with the GPU is just to CPU_PREP on | 219 | /* The normal way to synchronize with the GPU is just to CPU_PREP on |
diff --git a/freedreno/msm/msm_ringbuffer.c b/freedreno/msm/msm_ringbuffer.c index a78806c8..60f03154 100644 --- a/freedreno/msm/msm_ringbuffer.c +++ b/freedreno/msm/msm_ringbuffer.c | |||
@@ -399,7 +399,7 @@ static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start | |||
399 | { | 399 | { |
400 | struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring); | 400 | struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring); |
401 | struct drm_msm_gem_submit req = { | 401 | struct drm_msm_gem_submit req = { |
402 | .pipe = to_msm_pipe(ring->pipe)->pipe, | 402 | .flags = to_msm_pipe(ring->pipe)->pipe, |
403 | }; | 403 | }; |
404 | uint32_t i; | 404 | uint32_t i; |
405 | int ret; | 405 | int ret; |